stm32f3: i2c support now in f3 directory.
Very few functions can be shared (~ 3). A possible solutions is to move i2c_common_all to i2c_common_f124, create i2c_common_all and move f3/i2c to i2c_common_f3. Who agrees?
This commit is contained in:
Federico Ruiz Ugalde
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
8f3675fbfd
commit
4673348ff7
@@ -34,9 +34,9 @@ CFLAGS = -Os -g \
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# ARFLAGS = rcsv
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ARFLAGS = rcs
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OBJS = rcc.o gpio.o adc.o exti2.o
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OBJS = rcc.o gpio.o adc.o exti2.o i2c.o
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OBJS += gpio_common_all.o gpio_common_f234.o i2c_common_all.o\
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OBJS += gpio_common_all.o gpio_common_f234.o \
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dac_common_all.o usart_common_all.o crc_common_all.o\
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iwdg_common_all.o spi_common_all.o dma_common_f13.o\
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timer_common_all.o timer_common_f24.o flash_common_f234.o
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@@ -29,5 +29,374 @@ LGPL License Terms @ref lgpl_license
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*/
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#include <libopencm3/stm32/i2c.h>
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#include <libopencm3/stm32/common/i2c_common_all.h>
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#include <libopencm3/stm32/rcc.h>
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/**@{*/
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Reset.
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The I2C peripheral and all its associated configuration registers are placed in
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the reset condition. The reset is effected via the RCC peripheral reset system.
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@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
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*/
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void i2c_reset(uint32_t i2c)
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{
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switch (i2c) {
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case I2C1:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST);
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break;
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case I2C2:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST);
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break;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Peripheral Enable.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_peripheral_enable(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_PE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Peripheral Disable.
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This must not be reset while in Master mode until a communication has finished.
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In Slave mode, the peripheral is disabled only after communication has ended.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_peripheral_disable(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_PE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Start Condition.
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If in Master mode this will cause a restart condition to occur at the end of the
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current transmission. If in Slave mode, this will initiate a start condition
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when the current bus activity is completed.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_send_start(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_START;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Stop Condition.
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After the current byte transfer this will initiate a stop condition if in Master
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mode, or simply release the bus if in Slave mode.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_send_stop(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_STOP;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Clear Stop Flag.
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Clear the "Send Stop" flag in the I2C config register
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_clear_stop(uint32_t i2c)
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{
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I2C_ICR(i2c) |= I2C_ICR_STOPCF;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set the 7 bit Slave Address for the Peripheral.
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This sets an address for Slave mode operation, in 7 bit form.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] slave Unsigned int8. Slave address 0...127.
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*/
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void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
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{
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I2C_OAR1(i2c) = (uint16_t)(slave << 1);
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I2C_OAR1(i2c) &= ~I2C_OAR1_OA1MODE;
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I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Set the 10 bit Slave Address for the Peripheral.
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This sets an address for Slave mode operation, in 10 bit form.
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@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] slave Unsigned int16. Slave address 0...1023.
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*/
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void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
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{
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I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_OA1MODE | slave);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Send Data.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] data Unsigned int8. Byte to send.
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*/
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void i2c_send_data(uint32_t i2c, uint8_t data)
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{
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I2C_TXDR(i2c) = data;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Get Data.
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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uint8_t i2c_get_data(uint32_t i2c)
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{
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return(I2C_RXDR(i2c) & 0xff);
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}
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void i2c_enable_analog_filter(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF;
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}
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void i2c_disable_analog_filter(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_ANFOFF;
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}
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void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting)
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{
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I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting;
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}
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/* t_presc= (presc+1)*t_i2cclk */
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void i2c_set_prescaler(uint32_t i2c, uint8_t presc)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) | (presc << I2C_TIMINGR_PRESC_SHIFT);
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}
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void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) | (s_time << I2C_TIMINGR_SCLDEL_SHIFT);
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}
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void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) | (h_time << I2C_TIMINGR_SDADEL_SHIFT);
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}
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void i2c_set_scl_high_period(uint32_t i2c, uint8_t period)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) | (period << I2C_TIMINGR_SCLH_SHIFT);
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}
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void i2c_set_scl_low_period(uint32_t i2c, uint8_t period)
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{
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I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) | (period << I2C_TIMINGR_SCLL_SHIFT);
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}
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void i2c_enable_stretching(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH;
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}
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void i2c_disable_stretching(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH;
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}
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void i2c_100khz_i2cclk8mhz(uint32_t i2c)
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{
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i2c_set_prescaler(i2c, 1);
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i2c_set_scl_low_period(i2c, 0x13);
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i2c_set_scl_high_period(i2c, 0xF);
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i2c_set_data_hold_time(i2c, 0x2);
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i2c_set_data_setup_time(i2c, 0x4);
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}
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void i2c_set_7bit_addr_mode(uint32_t i2c)
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{
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I2C_CR2(i2c) &= ~I2C_CR2_ADD10;
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}
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void i2c_set_10bit_addr_mode(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_ADD10;
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}
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void i2c_set_7bit_address(uint32_t i2c, uint8_t addr)
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{
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I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) | ((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT);
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}
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void i2c_set_10bit_address(uint32_t i2c, uint16_t addr)
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{
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I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) | ((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT);
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}
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void i2c_set_write_transfer_dir(uint32_t i2c)
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{
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I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN;
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}
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void i2c_set_read_transfer_dir(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_RD_WRN;
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}
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void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes)
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{
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I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) | (n_bytes << I2C_CR2_NBYTES_SHIFT);
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}
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uint8_t i2c_is_start(uint32_t i2c)
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{
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if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) {
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return(1);
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} else {
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return(0);
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}
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}
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void i2c_enable_autoend(uint32_t i2c)
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{
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I2C_CR2(i2c) |= I2C_CR2_AUTOEND;
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}
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void i2c_disable_autoend(uint32_t i2c)
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{
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I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND;
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}
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uint8_t i2c_nack(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) {
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return(1);
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} else {
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return(0);
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}
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}
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uint8_t i2c_busy(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) {
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return(1);
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} else {
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return(0);
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}
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}
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uint8_t i2c_transmit_int_status(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) {
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return(1);
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} else {
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return(0);
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}
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}
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uint8_t i2c_transfer_complete(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) {
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return(1);
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} else {
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return(0);
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}
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}
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uint8_t i2c_received_data(uint32_t i2c)
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{
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if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) {
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return(1);
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} else {
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return(0);
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable Interrupt
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] interrupt Unsigned int32. Interrupt to enable.
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*/
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void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
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{
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I2C_CR1(i2c) |= interrupt;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable Interrupt
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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@param[in] interrupt Unsigned int32. Interrupt to disable.
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*/
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void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
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{
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I2C_CR1(i2c) &= ~interrupt;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable reception DMA
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_enable_rxdma(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_RXDMAEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable reception DMA
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_disable_rxdma(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Enable transmission DMA
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_enable_txdma(uint32_t i2c)
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{
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I2C_CR1(i2c) |= I2C_CR1_TXDMAEN;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief I2C Disable transmission DMA
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@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
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*/
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void i2c_disable_txdma(uint32_t i2c)
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{
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I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN;
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}
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/**@}*/
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