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stm32/timers: clarify "advanced timers" restriction

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by making it vaguer.  These days, there's extra timers that support the
BDTR register, so the simple "advanced" timer description is no longer
sufficiently clear.  You have to check your particular reference manual.

Fixes: https://github.com/libopencm3/libopencm3/issues/1378
This commit is contained in:
Karl Palsson
2022-02-01 13:15:13 +00:00
parent 1b83a3ce47
commit 3f52b7784c
1 changed files with 14 additions and 14 deletions
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28
lib/stm32/common/timer_common_all.c
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@@ -1347,7 +1347,7 @@ Enables the output in the Break feature of an advanced timer. This does not
enable the break functionality itself but only sets the Master Output Enable in
the Break and Deadtime Register.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@note It is necessary to call this function to enable the output on an advanced
timer <b>even if break or deadtime features are not being used</b>.
@@ -1367,7 +1367,7 @@ void timer_enable_break_main_output(uint32_t timer_peripheral)
Disables the output in the Break feature of an advanced timer. This clears
the Master Output Enable in the Break and Deadtime Register.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1385,7 +1385,7 @@ Enables the automatic output feature of the Break function of an advanced
timer so that the output is re-enabled at the next update event following a
break event.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1403,7 +1403,7 @@ Disables the automatic output feature of the Break function of an advanced
timer so that the output is re-enabled at the next update event following a
break event.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1419,7 +1419,7 @@ void timer_disable_break_automatic_output(uint32_t timer_peripheral)
Sets the break function to activate when the break input becomes high.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1435,7 +1435,7 @@ void timer_set_break_polarity_high(uint32_t timer_peripheral)
Sets the break function to activate when the break input becomes low.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1451,7 +1451,7 @@ void timer_set_break_polarity_low(uint32_t timer_peripheral)
Enables the break function of an advanced timer.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1467,7 +1467,7 @@ void timer_enable_break(uint32_t timer_peripheral)
Disables the break function of an advanced timer.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1487,7 +1487,7 @@ if no complementary output is present. When the capture-compare output is
disabled while the complementary output is enabled, the output is set to its
inactive level as defined by the output polarity.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1506,7 +1506,7 @@ timer in which the complementary outputs have been configured. It has no effect
if no complementary output is present. When the capture-compare output is
disabled, the output is also disabled.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1524,7 +1524,7 @@ Enables the off-state in idle mode for the break function of an advanced
timer. When the master output is disabled the output is set to its
inactive level as defined by the output polarity.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1541,7 +1541,7 @@ void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral)
Disables the off-state in idle mode for the break function of an advanced
timer. When the master output is disabled the output is also disabled.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1559,7 +1559,7 @@ Set the lock bits for an advanced timer. Three levels of lock providing
protection against software errors. Once written they cannot be changed until a
timer reset has occurred.
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8
@@ -1583,7 +1583,7 @@ terms of the number of DTSC cycles:
@li Bits 7:5 = 110, deadtime = 8x(32+bits(5:0))
@li Bits 7:5 = 111, deadtime = 16x(32+bits(5:0))
@note This setting is only valid for the advanced timers.
@note Not all timers support Break/Deadtime features
@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or
TIM8