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Added functions for entering l4 power modes

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This commit is contained in:
andrewmcg1
2024-10-16 05:20:49 -04:00
committed by Piotr Esden-Tempski
parent 49e347923b
commit 3b892e4a18
4 changed files with 66 additions and 0 deletions
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4
include/libopencm3/cm3/scb.h
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@@ -554,6 +554,10 @@ struct scb_exception_stack_frame {
} while (0)
void scb_reset_system(void) __attribute__((noreturn));
void scb_set_sleepdeep(void);
void scb_clear_sleepdeep(void);
void scb_set_sleeponexit(void);
void scb_clear_sleeponexit(void);
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)

8
include/libopencm3/stm32/l4/pwr.h
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@@ -77,11 +77,15 @@ specific memorymap.h header before including this header file.*/
#define PWR_CR1_LPMS_SHIFT 0
#define PWR_CR1_LPMS_MASK 0x07
/** @defgroup pwr_cr1_lpms LPMS mode selection
* @ingroup STM32L4_pwr_defines
@{*/
#define PWR_CR1_LPMS_STOP_0 0
#define PWR_CR1_LPMS_STOP_1 1
#define PWR_CR1_LPMS_STOP_2 2
#define PWR_CR1_LPMS_STANDBY 3
#define PWR_CR1_LPMS_SHUTDOWN 4
/**@}*/
/* --- PWR_CR2 values ------------------------------------------------------- */
@@ -173,6 +177,10 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale);
void pwr_disable_backup_domain_write_protect(void);
void pwr_enable_backup_domain_write_protect(void);
void pwr_enable_low_power_run(void);
void pwr_disable_low_power_run(void);
void pwr_set_low_power_mode_selection(uint32_t lpms);
END_DECLS
#endif

20
lib/cm3/scb.c
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@@ -58,6 +58,26 @@ void scb_reset_system(void)
while (1);
}
void scb_set_sleepdeep(void)
{
SCB_SCR |= SCB_SCR_SLEEPDEEP;
}
void scb_clear_sleepdeep(void)
{
SCB_SCR &= ~SCB_SCR_SLEEPDEEP;
}
void scb_set_sleeponexit(void)
{
SCB_SCR |= SCB_SCR_SLEEPONEXIT;
}
void scb_clear_sleeponexit(void)
{
SCB_SCR &= ~SCB_SCR_SLEEPONEXIT;
}
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
void scb_set_priority_grouping(uint32_t prigroup)

34
lib/stm32/l4/pwr.c
View File

@@ -72,4 +72,38 @@ void pwr_enable_backup_domain_write_protect(void)
PWR_CR1 &= ~PWR_CR1_DBP;
}
/** Enable Low Power Run
*
* This enables low power run mode. The clock frequency is limited to 2 MHz in this mode
* and must be set before entering low power run mode.
*/
void pwr_enable_low_power_run(void)
{
PWR_CR1 |= PWR_CR1_LPR;
}
/** Disable Low Power Run
*
* This disables low power run mode
*/
void pwr_disable_low_power_run(void)
{
PWR_CR1 &= ~PWR_CR1_LPR;
}
/** @brief Select the low power mode used in deep sleep.
*
* Set which power mode is entered when the processor enters deep sleep.
*
* @param[in] lpms low power mode @ref pwr_cr1_lpms
*/
void pwr_set_low_power_mode_selection(uint32_t lpms)
{
uint32_t reg32;
reg32 = PWR_CR1;
reg32 &= ~(PWR_CR1_LPMS_MASK << PWR_CR1_LPMS_SHIFT);
PWR_CR1 = (reg32 | (lpms << PWR_CR1_LPMS_SHIFT));
}
/**@}*/