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stm32l/stm32f: name space standardization [BREAKING]

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As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.

    Let's not hide the fact that these variables are structs/enums.

    We are filling up the namespace badly enough, we should be prefixing as
    much as we can with the module names at least. As users we already run
    often enough in namespace colisions we don't have to make it worse.

    * CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
    * clock enums (PLL, HSI, HSE ...) prefixed with RCC_
    * scale enum of pwr module prefixed with PWR_
This commit is contained in:
Karl Palsson
2015-11-08 15:53:31 +00:00
committed by Piotr Esden-Tempski
parent d680be81b5
commit 3a7cbec776
14 changed files with 580 additions and 580 deletions
Download Patch File Download Diff File Expand all files Collapse all files

114
lib/stm32/f2/rcc.c
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@@ -48,7 +48,7 @@ uint32_t rcc_ahb_frequency = 16000000;
uint32_t rcc_apb1_frequency = 16000000;
uint32_t rcc_apb2_frequency = 16000000;
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = {
const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
{ /* 120MHz */
.pllm = 8,
.plln = 240,
@@ -67,19 +67,19 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = {
void rcc_osc_ready_int_clear(osc_t osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CIR |= RCC_CIR_PLLRDYC;
break;
case HSE:
case RCC_HSE:
RCC_CIR |= RCC_CIR_HSERDYC;
break;
case HSI:
case RCC_HSI:
RCC_CIR |= RCC_CIR_HSIRDYC;
break;
case LSE:
case RCC_LSE:
RCC_CIR |= RCC_CIR_LSERDYC;
break;
case LSI:
case RCC_LSI:
RCC_CIR |= RCC_CIR_LSIRDYC;
break;
}
@@ -88,19 +88,19 @@ void rcc_osc_ready_int_clear(osc_t osc)
void rcc_osc_ready_int_enable(osc_t osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CIR |= RCC_CIR_PLLRDYIE;
break;
case HSE:
case RCC_HSE:
RCC_CIR |= RCC_CIR_HSERDYIE;
break;
case HSI:
case RCC_HSI:
RCC_CIR |= RCC_CIR_HSIRDYIE;
break;
case LSE:
case RCC_LSE:
RCC_CIR |= RCC_CIR_LSERDYIE;
break;
case LSI:
case RCC_LSI:
RCC_CIR |= RCC_CIR_LSIRDYIE;
break;
}
@@ -109,19 +109,19 @@ void rcc_osc_ready_int_enable(osc_t osc)
void rcc_osc_ready_int_disable(osc_t osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
break;
case HSE:
case RCC_HSE:
RCC_CIR &= ~RCC_CIR_HSERDYIE;
break;
case HSI:
case RCC_HSI:
RCC_CIR &= ~RCC_CIR_HSIRDYIE;
break;
case LSE:
case RCC_LSE:
RCC_CIR &= ~RCC_CIR_LSERDYIE;
break;
case LSI:
case RCC_LSI:
RCC_CIR &= ~RCC_CIR_LSIRDYIE;
break;
}
@@ -130,19 +130,19 @@ void rcc_osc_ready_int_disable(osc_t osc)
int rcc_osc_ready_int_flag(osc_t osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
case HSE:
case RCC_HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
case HSI:
case RCC_HSI:
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
break;
case LSE:
case RCC_LSE:
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
break;
case LSI:
case RCC_LSI:
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
break;
}
@@ -163,19 +163,19 @@ int rcc_css_int_flag(void)
void rcc_wait_for_osc_ready(osc_t osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
break;
case HSE:
case RCC_HSE:
while ((RCC_CR & RCC_CR_HSERDY) == 0);
break;
case HSI:
case RCC_HSI:
while ((RCC_CR & RCC_CR_HSIRDY) == 0);
break;
case LSE:
case RCC_LSE:
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
break;
case LSI:
case RCC_LSI:
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
break;
}
@@ -184,13 +184,13 @@ void rcc_wait_for_osc_ready(osc_t osc)
void rcc_wait_for_sysclk_status(osc_t osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
break;
case HSE:
case RCC_HSE:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
break;
case HSI:
case RCC_HSI:
while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
break;
default:
@@ -202,19 +202,19 @@ void rcc_wait_for_sysclk_status(osc_t osc)
void rcc_osc_on(osc_t osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case HSE:
case RCC_HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case HSI:
case RCC_HSI:
RCC_CR |= RCC_CR_HSION;
break;
case LSE:
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case LSI:
case RCC_LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
@@ -223,19 +223,19 @@ void rcc_osc_on(osc_t osc)
void rcc_osc_off(osc_t osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case HSE:
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case HSI:
case RCC_HSI:
RCC_CR &= ~RCC_CR_HSION;
break;
case LSE:
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case LSI:
case RCC_LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
@@ -254,15 +254,15 @@ void rcc_css_disable(void)
void rcc_osc_bypass_enable(osc_t osc)
{
switch (osc) {
case HSE:
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case LSE:
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
@@ -271,15 +271,15 @@ void rcc_osc_bypass_enable(osc_t osc)
void rcc_osc_bypass_disable(osc_t osc)
{
switch (osc) {
case HSE:
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case LSE:
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case PLL:
case HSI:
case LSI:
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
@@ -364,18 +364,18 @@ uint32_t rcc_system_clock_source(void)
return (RCC_CFGR & 0x000c) >> 2;
}
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
/* Enable external high-speed oscillator 8MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
/*
* Set prescalers for AHB, ADC, ABP1, ABP2.
@@ -389,8 +389,8 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
clock->pllp, clock->pllq);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Configure flash settings. */
flash_set_ws(clock->flash_config);
@@ -399,7 +399,7 @@ void rcc_clock_setup_hse_3v3(const clock_scale_t *clock)
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
/* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL);
rcc_wait_for_sysclk_status(RCC_PLL);
/* Set the peripheral clock frequencies used. */
rcc_apb1_frequency = clock->apb1_frequency;