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stm32l/stm32f: name space standardization [BREAKING]

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As done by esden for the F4, remove typedefs and add prefixes to clock enums
This extends this to all stm32 families.

    Let's not hide the fact that these variables are structs/enums.

    We are filling up the namespace badly enough, we should be prefixing as
    much as we can with the module names at least. As users we already run
    often enough in namespace colisions we don't have to make it worse.

    * CLOCK_3V3_xxx enums renamed to RCC_CLOCK_3V3_xxx
    * clock enums (PLL, HSI, HSE ...) prefixed with RCC_
    * scale enum of pwr module prefixed with PWR_
This commit is contained in:
Karl Palsson
2015-11-08 15:53:31 +00:00
committed by Piotr Esden-Tempski
parent d680be81b5
commit 3a7cbec776
14 changed files with 580 additions and 580 deletions
Download Patch File Download Diff File Expand all files Collapse all files

224
lib/stm32/f1/rcc.c
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@@ -70,25 +70,25 @@ use.
void rcc_osc_ready_int_clear(enum rcc_osc osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CIR |= RCC_CIR_PLLRDYC;
break;
case PLL2:
case RCC_PLL2:
RCC_CIR |= RCC_CIR_PLL2RDYC;
break;
case PLL3:
case RCC_PLL3:
RCC_CIR |= RCC_CIR_PLL3RDYC;
break;
case HSE:
case RCC_HSE:
RCC_CIR |= RCC_CIR_HSERDYC;
break;
case HSI:
case RCC_HSI:
RCC_CIR |= RCC_CIR_HSIRDYC;
break;
case LSE:
case RCC_LSE:
RCC_CIR |= RCC_CIR_LSERDYC;
break;
case LSI:
case RCC_LSI:
RCC_CIR |= RCC_CIR_LSIRDYC;
break;
}
@@ -103,25 +103,25 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc)
void rcc_osc_ready_int_enable(enum rcc_osc osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CIR |= RCC_CIR_PLLRDYIE;
break;
case PLL2:
case RCC_PLL2:
RCC_CIR |= RCC_CIR_PLL2RDYIE;
break;
case PLL3:
case RCC_PLL3:
RCC_CIR |= RCC_CIR_PLL3RDYIE;
break;
case HSE:
case RCC_HSE:
RCC_CIR |= RCC_CIR_HSERDYIE;
break;
case HSI:
case RCC_HSI:
RCC_CIR |= RCC_CIR_HSIRDYIE;
break;
case LSE:
case RCC_LSE:
RCC_CIR |= RCC_CIR_LSERDYIE;
break;
case LSI:
case RCC_LSI:
RCC_CIR |= RCC_CIR_LSIRDYIE;
break;
}
@@ -136,25 +136,25 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc)
void rcc_osc_ready_int_disable(enum rcc_osc osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CIR &= ~RCC_CIR_PLLRDYIE;
break;
case PLL2:
case RCC_PLL2:
RCC_CIR &= ~RCC_CIR_PLL2RDYIE;
break;
case PLL3:
case RCC_PLL3:
RCC_CIR &= ~RCC_CIR_PLL3RDYIE;
break;
case HSE:
case RCC_HSE:
RCC_CIR &= ~RCC_CIR_HSERDYIE;
break;
case HSI:
case RCC_HSI:
RCC_CIR &= ~RCC_CIR_HSIRDYIE;
break;
case LSE:
case RCC_LSE:
RCC_CIR &= ~RCC_CIR_LSERDYIE;
break;
case LSI:
case RCC_LSI:
RCC_CIR &= ~RCC_CIR_LSIRDYIE;
break;
}
@@ -170,25 +170,25 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc)
int rcc_osc_ready_int_flag(enum rcc_osc osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
break;
case PLL2:
case RCC_PLL2:
return ((RCC_CIR & RCC_CIR_PLL2RDYF) != 0);
break;
case PLL3:
case RCC_PLL3:
return ((RCC_CIR & RCC_CIR_PLL3RDYF) != 0);
break;
case HSE:
case RCC_HSE:
return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
break;
case HSI:
case RCC_HSI:
return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
break;
case LSE:
case RCC_LSE:
return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
break;
case LSI:
case RCC_LSI:
return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
break;
}
@@ -226,25 +226,25 @@ int rcc_css_int_flag(void)
void rcc_wait_for_osc_ready(enum rcc_osc osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
while ((RCC_CR & RCC_CR_PLLRDY) == 0);
break;
case PLL2:
case RCC_PLL2:
while ((RCC_CR & RCC_CR_PLL2RDY) == 0);
break;
case PLL3:
case RCC_PLL3:
while ((RCC_CR & RCC_CR_PLL3RDY) == 0);
break;
case HSE:
case RCC_HSE:
while ((RCC_CR & RCC_CR_HSERDY) == 0);
break;
case HSI:
case RCC_HSI:
while ((RCC_CR & RCC_CR_HSIRDY) == 0);
break;
case LSE:
case RCC_LSE:
while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
break;
case LSI:
case RCC_LSI:
while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
break;
}
@@ -268,25 +268,25 @@ pwr_disable_backup_domain_write_protect).
void rcc_osc_on(enum rcc_osc osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CR |= RCC_CR_PLLON;
break;
case PLL2:
case RCC_PLL2:
RCC_CR |= RCC_CR_PLL2ON;
break;
case PLL3:
case RCC_PLL3:
RCC_CR |= RCC_CR_PLL3ON;
break;
case HSE:
case RCC_HSE:
RCC_CR |= RCC_CR_HSEON;
break;
case HSI:
case RCC_HSI:
RCC_CR |= RCC_CR_HSION;
break;
case LSE:
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEON;
break;
case LSI:
case RCC_LSI:
RCC_CSR |= RCC_CSR_LSION;
break;
}
@@ -309,25 +309,25 @@ backup domain write protection has been removed (see
void rcc_osc_off(enum rcc_osc osc)
{
switch (osc) {
case PLL:
case RCC_PLL:
RCC_CR &= ~RCC_CR_PLLON;
break;
case PLL2:
case RCC_PLL2:
RCC_CR &= ~RCC_CR_PLL2ON;
break;
case PLL3:
case RCC_PLL3:
RCC_CR &= ~RCC_CR_PLL3ON;
break;
case HSE:
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEON;
break;
case HSI:
case RCC_HSI:
RCC_CR &= ~RCC_CR_HSION;
break;
case LSE:
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEON;
break;
case LSI:
case RCC_LSI:
RCC_CSR &= ~RCC_CSR_LSION;
break;
}
@@ -370,17 +370,17 @@ pwr_disable_backup_domain_write_protect).
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case HSE:
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case LSE:
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case PLL:
case PLL2:
case PLL3:
case HSI:
case LSI:
case RCC_PLL:
case RCC_PLL2:
case RCC_PLL3:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
@@ -403,17 +403,17 @@ pwr_disable_backup_domain_write_protect) or the backup domain has been reset
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case HSE:
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case LSE:
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case PLL:
case PLL2:
case PLL3:
case HSI:
case LSI:
case RCC_PLL:
case RCC_PLL2:
case RCC_PLL3:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
@@ -533,7 +533,7 @@ void rcc_set_rtc_clock_source(enum rcc_osc clock_source)
uint32_t reg32;
switch (clock_source) {
case LSE:
case RCC_LSE:
/* Turn the LSE on and wait while it stabilises. */
RCC_BDCR |= RCC_BDCR_LSEON;
while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0);
@@ -542,7 +542,7 @@ void rcc_set_rtc_clock_source(enum rcc_osc clock_source)
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 8);
break;
case LSI:
case RCC_LSI:
/* Turn the LSI on and wait while it stabilises. */
RCC_CSR |= RCC_CSR_LSION;
while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0);
@@ -551,7 +551,7 @@ void rcc_set_rtc_clock_source(enum rcc_osc clock_source)
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 9);
break;
case HSE:
case RCC_HSE:
/* Turn the HSE on and wait while it stabilises. */
RCC_CR |= RCC_CR_HSEON;
while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0);
@@ -560,10 +560,10 @@ void rcc_set_rtc_clock_source(enum rcc_osc clock_source)
RCC_BDCR &= ~((1 << 8) | (1 << 9));
RCC_BDCR |= (1 << 9) | (1 << 8);
break;
case PLL:
case PLL2:
case PLL3:
case HSI:
case RCC_PLL:
case RCC_PLL2:
case RCC_PLL3:
case RCC_HSI:
/* Unusable clock source, here to prevent warnings. */
/* Turn off clock sources to RTC. */
RCC_BDCR &= ~((1 << 8) | (1 << 9));
@@ -694,8 +694,8 @@ uint32_t rcc_system_clock_source(void)
void rcc_clock_setup_in_hsi_out_64mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
@@ -727,8 +727,8 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
@@ -747,8 +747,8 @@ void rcc_clock_setup_in_hsi_out_64mhz(void)
void rcc_clock_setup_in_hsi_out_48mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
@@ -781,8 +781,8 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
@@ -801,8 +801,8 @@ void rcc_clock_setup_in_hsi_out_48mhz(void)
void rcc_clock_setup_in_hsi_out_24mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
@@ -834,8 +834,8 @@ void rcc_clock_setup_in_hsi_out_24mhz(void)
rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
@@ -854,15 +854,15 @@ void rcc_clock_setup_in_hsi_out_24mhz(void)
void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
/* Enable external high-speed oscillator 8MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
/*
@@ -898,8 +898,8 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
@@ -918,15 +918,15 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
/* Enable external high-speed oscillator 8MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
/*
@@ -962,8 +962,8 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
@@ -982,15 +982,15 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
/* Enable external high-speed oscillator 16MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
/*
@@ -1026,8 +1026,8 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
@@ -1046,15 +1046,15 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */
rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI);
rcc_osc_on(RCC_HSI);
rcc_wait_for_osc_ready(RCC_HSI);
/* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
/* Enable external high-speed oscillator 16MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
/*
@@ -1090,8 +1090,8 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2);
/* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
@@ -1110,8 +1110,8 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
{
/* Enable external high-speed oscillator 25MHz. */
rcc_osc_on(HSE);
rcc_wait_for_osc_ready(HSE);
rcc_osc_on(RCC_HSE);
rcc_wait_for_osc_ready(RCC_HSE);
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
/*
@@ -1136,8 +1136,8 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
rcc_set_pll2_multiplication_factor(RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8);
/* Enable PLL2 oscillator and wait for it to stabilize */
rcc_osc_on(PLL2);
rcc_wait_for_osc_ready(PLL2);
rcc_osc_on(RCC_PLL2);
rcc_wait_for_osc_ready(RCC_PLL2);
/* Set pll1 prediv/multiplier, prediv1 src, and usb predivider */
rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
@@ -1148,8 +1148,8 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void)
rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3);
/* enable PLL1 and wait for it to stabilize */
rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL);
rcc_osc_on(RCC_PLL);
rcc_wait_for_osc_ready(RCC_PLL);
/* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);