Stile fixes run, 80 char boundry.

lib/stm32/common/dac_common_all.c

@@ -339,8 +339,9 @@ existing output values in the DAC output registers.
 
 @note The DAC trigger must be enabled for this to work.
 
-@param[in] dac_wave_ens uint32_t. Taken from @ref dac_wave1_en or @ref dac_wave2_en
-or a logical OR of one of each of these to set both channels simultaneously.
+@param[in] dac_wave_ens uint32_t. Taken from @ref dac_wave1_en or @ref
+dac_wave2_en or a logical OR of one of each of these to set both channels
+simultaneously.
 */
 
 void dac_set_waveform_generation(uint32_t dac_wave_ens)

lib/stm32/common/dma_common_f13.c

@@ -75,7 +75,8 @@ same channel may be cleared by using the logical OR of the interrupt flags.
 dma_if_offset
 */
 
-void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts)
+void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel,
+			       uint32_t interrupts)
 {
 /* Get offset to interrupt flag location in channel field */
 	uint32_t flags = (interrupts << DMA_FLAG_OFFSET(channel));
@@ -165,7 +166,8 @@ if the peripheral does not support byte or half-word writes.
 dma_ch_perwidth.
 */
 
-void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size)
+void dma_set_peripheral_size(uint32_t dma, uint8_t channel,
+			     uint32_t peripheral_size)
 {
 	DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
 	DMA_CCR(dma, channel) |= peripheral_size;

lib/stm32/common/dma_common_f24.c

@@ -92,7 +92,8 @@ same stream may be cleared by using the bitwise OR of the interrupt flags.
 dma_if_offset
 */
 
-void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts)
+void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream,
+			       uint32_t interrupts)
 {
 	/* Get offset to interrupt flag location in stream field */
 	uint32_t flags = (interrupts << DMA_ISR_OFFSET(stream));
@@ -213,7 +214,8 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
 dma_st_perwidth.
 */
 
-void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size)
+void dma_set_peripheral_size(uint32_t dma, uint8_t stream,
+			     uint32_t peripheral_size)
 {
 	DMA_SCR(dma, stream) &= ~(DMA_SxCR_PSIZE_MASK);
 	DMA_SCR(dma, stream) |= peripheral_size;

lib/stm32/common/gpio_common_f24.c

@@ -86,7 +86,8 @@ gpio_pup
 	     If multiple pins are to be set, use bitwise OR '|' to separate
 	     them.
 */
-void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios)
+void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down,
+		     uint16_t gpios)
 {
 	uint16_t i;
 	uint32_t moder, pupd;
@@ -128,7 +129,8 @@ port.
 	     If multiple pins are to be set, use bitwise OR '|' to separate
 	     them.
 */
-void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios)
+void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed,
+			     uint16_t gpios)
 {
 	uint16_t i;
 	uint32_t ospeedr;

lib/stm32/common/iwdg_common_all.c

@@ -66,8 +66,8 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
 can occasionally occur if the prescale or preload registers are currently busy
 loading a previous value.
 
-@param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog reset
-until a system reset is issued.
+@param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog
+reset until a system reset is issued.
 */
 
 void iwdg_set_period_ms(uint32_t period)

lib/stm32/common/spi_common_all.c

@@ -119,7 +119,8 @@ spi_lsbfirst.
 @returns int. Error code.
 */
 
-int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst)
+int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
+		    uint32_t dff, uint32_t lsbfirst)
 {
 	uint32_t reg32 = SPI_CR1(spi);
 

lib/stm32/common/timer_common_all.c

@@ -1444,7 +1444,8 @@ tim_reg_base
 		timers 1 and 8)
 */
 
-void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id)
+void timer_set_oc_idle_state_set(uint32_t timer_peripheral,
+				 enum tim_oc_id oc_id)
 {
 #if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	/* Acting for TIM1 and TIM8 only. */
@@ -1496,7 +1497,8 @@ tim_reg_base
 		timers 1 and 8)
 */
 
-void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id)
+void timer_set_oc_idle_state_unset(uint32_t timer_peripheral,
+				   enum tim_oc_id oc_id)
 {
 #if (defined(TIM1_BASE) || defined(TIM8_BASE))
 	/* Acting for TIM1 and TIM8 only. */
@@ -1546,7 +1548,8 @@ to the compare register.
 @param[in] value Unsigned int32. Compare value.
 */
 
-void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value)
+void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id,
+			uint32_t value)
 {
 	switch (oc_id) {
 	case TIM_OC1: