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Stile fixes run, 80 char boundry.

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This commit is contained in:
Piotr Esden-Tempski
2013-06-12 21:00:50 -07:00
parent 34de1e776e
commit 39fa9e4c58
45 changed files with 274 additions and 177 deletions
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35
lib/stm32/can.c
View File

@@ -99,8 +99,8 @@ Initialize the selected CAN peripheral block.
@returns int 0 on success, 1 on initialization failure.
*/
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp,
bool loopback, bool silent)
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
uint32_t brp, bool loopback, bool silent)
{
volatile uint32_t wait_ack;
int ret = 0;
@@ -206,8 +206,9 @@ Initialize incoming message filter and assign to FIFO.
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_list_mode,
uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable)
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit,
bool id_list_mode, uint32_t fr1, uint32_t fr2,
uint32_t fifo, bool enable)
{
uint32_t filter_select_bit = 0x00000001 << nr;
@@ -266,8 +267,9 @@ void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_li
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t mask1,
uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable)
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
uint16_t mask1, uint16_t id2,
uint16_t mask2, uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, false, false,
((uint32_t)id1 << 16) | (uint32_t)mask1,
@@ -284,8 +286,8 @@ void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, uint32_t mask,
uint32_t fifo, bool enable)
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id,
uint32_t mask, uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, true, false, id, mask, fifo, enable);
}
@@ -302,8 +304,10 @@ void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, u
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t id2,
uint16_t id3, uint16_t id4, uint32_t fifo, bool enable)
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr,
uint16_t id1, uint16_t id2,
uint16_t id3, uint16_t id4,
uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, false, true,
((uint32_t)id1 << 16) | (uint32_t)id2,
@@ -320,7 +324,8 @@ void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, uint32_t id2,
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr,
uint32_t id1, uint32_t id2,
uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, true, true, id1, id2, fifo, enable);
@@ -360,7 +365,8 @@ void can_disable_irq(uint32_t canport, uint32_t irq)
@returns int 0, 1 or 2 on success and depending on which outgoing mailbox got
selected. -1 if no mailbox was available and no transmission got queued.
*/
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data)
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr,
uint8_t length, uint8_t *data)
{
int ret = 0;
uint32_t mailbox = 0;
@@ -473,8 +479,9 @@ void can_fifo_release(uint32_t canport, uint8_t fifo)
@param[out] length Unsigned int8 pointer. Length of message payload.
@param[out] data Unsigned int8[]. Message payload data.
*/
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext,
bool *rtr, uint32_t *fmi, uint8_t *length, uint8_t *data)
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
bool *ext, bool *rtr, uint32_t *fmi, uint8_t *length,
uint8_t *data)
{
uint32_t fifo_id = 0;
union {

5
lib/stm32/common/dac_common_all.c
View File

@@ -339,8 +339,9 @@ existing output values in the DAC output registers.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_wave_ens uint32_t. Taken from @ref dac_wave1_en or @ref dac_wave2_en
or a logical OR of one of each of these to set both channels simultaneously.
@param[in] dac_wave_ens uint32_t. Taken from @ref dac_wave1_en or @ref
dac_wave2_en or a logical OR of one of each of these to set both channels
simultaneously.
*/
void dac_set_waveform_generation(uint32_t dac_wave_ens)

6
lib/stm32/common/dma_common_f13.c
View File

@@ -75,7 +75,8 @@ same channel may be cleared by using the logical OR of the interrupt flags.
dma_if_offset
*/
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts)
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel,
uint32_t interrupts)
{
/* Get offset to interrupt flag location in channel field */
uint32_t flags = (interrupts << DMA_FLAG_OFFSET(channel));
@@ -165,7 +166,8 @@ if the peripheral does not support byte or half-word writes.
dma_ch_perwidth.
*/
void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size)
void dma_set_peripheral_size(uint32_t dma, uint8_t channel,
uint32_t peripheral_size)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
DMA_CCR(dma, channel) |= peripheral_size;

6
lib/stm32/common/dma_common_f24.c
View File

@@ -92,7 +92,8 @@ same stream may be cleared by using the bitwise OR of the interrupt flags.
dma_if_offset
*/
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts)
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream,
uint32_t interrupts)
{
/* Get offset to interrupt flag location in stream field */
uint32_t flags = (interrupts << DMA_ISR_OFFSET(stream));
@@ -213,7 +214,8 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
dma_st_perwidth.
*/
void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size)
void dma_set_peripheral_size(uint32_t dma, uint8_t stream,
uint32_t peripheral_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_PSIZE_MASK);
DMA_SCR(dma, stream) |= peripheral_size;

6
lib/stm32/common/gpio_common_f24.c
View File

@@ -86,7 +86,8 @@ gpio_pup
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios)
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down,
uint16_t gpios)
{
uint16_t i;
uint32_t moder, pupd;
@@ -128,7 +129,8 @@ port.
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios)
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed,
uint16_t gpios)
{
uint16_t i;
uint32_t ospeedr;

4
lib/stm32/common/iwdg_common_all.c
View File

@@ -66,8 +66,8 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
can occasionally occur if the prescale or preload registers are currently busy
loading a previous value.
@param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog reset
until a system reset is issued.
@param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog
reset until a system reset is issued.
*/
void iwdg_set_period_ms(uint32_t period)

3
lib/stm32/common/spi_common_all.c
View File

@@ -119,7 +119,8 @@ spi_lsbfirst.
@returns int. Error code.
*/
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst)
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
uint32_t dff, uint32_t lsbfirst)
{
uint32_t reg32 = SPI_CR1(spi);

9
lib/stm32/common/timer_common_all.c
View File

@@ -1444,7 +1444,8 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_idle_state_set(uint32_t timer_peripheral,
enum tim_oc_id oc_id)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
/* Acting for TIM1 and TIM8 only. */
@@ -1496,7 +1497,8 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral,
enum tim_oc_id oc_id)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
/* Acting for TIM1 and TIM8 only. */
@@ -1546,7 +1548,8 @@ to the compare register.
@param[in] value Unsigned int32. Compare value.
*/
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value)
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id,
uint32_t value)
{
switch (oc_id) {
case TIM_OC1:

3
lib/stm32/f1/adc.c
View File

@@ -490,7 +490,8 @@ adc_reg_base.
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel.
*/
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
uint8_t channel)
{
uint32_t reg32;

6
lib/stm32/f2/rcc.c
View File

@@ -338,7 +338,8 @@ void rcc_set_rtcpre(uint32_t rtcpre)
RCC_CFGR = (reg32 | (rtcpre << 16));
}
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
@@ -346,7 +347,8 @@ void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |

9
lib/stm32/f4/adc.c
View File

@@ -278,7 +278,8 @@ adc_enable_analog_watchdog_regular.
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
*/
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
uint8_t channel)
{
uint32_t reg32;
@@ -809,7 +810,8 @@ the trigger polarity is zero, triggering is disabled.
adc_trigger_polarity_regular
*/
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity)
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
uint32_t polarity)
{
uint32_t reg32 = ADC_CR2(adc);
@@ -841,7 +843,8 @@ the polarity of the trigger event: rising or falling edge or both.
adc_trigger_polarity_injected
*/
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity)
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
uint32_t polarity)
{
uint32_t reg32 = ADC_CR2(adc);

6
lib/stm32/f4/rcc.c
View File

@@ -455,7 +455,8 @@ void rcc_set_rtcpre(uint32_t rtcpre)
RCC_CFGR = (reg32 | (rtcpre << 16));
}
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
@@ -463,7 +464,8 @@ void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |

3
lib/stm32/l1/rcc.c
View File

@@ -375,7 +375,8 @@ void rcc_set_sysclk_source(uint32_t clk)
RCC_CFGR = (reg32 | clk);
}
void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, uint32_t divisor)
void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier,
uint32_t divisor)
{
uint32_t reg32;