Stile fixes run, 80 char boundry.

This commit is contained in:
Piotr Esden-Tempski
2013-06-12 21:00:50 -07:00
parent 34de1e776e
commit 39fa9e4c58
45 changed files with 274 additions and 177 deletions

View File

@@ -173,7 +173,8 @@
/* Bits [31:30]: reserved - must be kept cleared */
/* TBLOFF[29:9]: Vector table base offset field */
#define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */
/* inconsistent datasheet - LSB could be 11 */
#define SCB_VTOR_TBLOFF_LSB 9
/* --- SCB_AIRCR values ---------------------------------------------------- */

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@@ -21,7 +21,8 @@ LGPL License Terms @ref lgpl_license
/** @defgroup EFM32LG_defines EFM32 Leopard Gecko Defines
@brief Defined Constants and Types for the Energy Micro EFM32 Leopard Gecko series
@brief Defined Constants and Types for the Energy Micro EFM32 Leopard Gecko
series
@version 1.0.0

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@@ -217,8 +217,8 @@ enum gpio_trigger {
BEGIN_DECLS
void gpio_enable_ahb_aperture(void);
void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
uint8_t gpios);
void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode,
enum gpio_pullup pullup, uint8_t gpios);
void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, uint8_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios);
@@ -319,7 +319,8 @@ static inline uint8_t gpio_port_read(uint32_t gpioport)
/**
* \brief Set level of of all pins from a port (atomic)
*
* Set the level of all pins on the given GPIO port. This is an atomic operation.
* Set the level of all pins on the given GPIO port. This is an atomic
* operation.
*
* This is functionally identical to @ref gpio_write (gpioport, GPIO_ALL, data).
*
@@ -335,7 +336,8 @@ static inline void gpio_port_write(uint32_t gpioport, uint8_t data)
}
/** @} */
void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, uint8_t gpios);
void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger,
uint8_t gpios);
void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios);
void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios);

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@@ -646,26 +646,31 @@ BEGIN_DECLS
void can_reset(uint32_t canport);
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp,
bool loopback, bool silent);
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2,
uint32_t brp, bool loopback, bool silent);
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_list_mode,
uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable);
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t mask1,
uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable);
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, uint32_t mask,
uint32_t fifo, bool enable);
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t id2,
uint16_t id3, uint16_t id4, uint32_t fifo, bool enable);
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, uint32_t id2,
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit,
bool id_list_mode, uint32_t fr1, uint32_t fr2,
uint32_t fifo, bool enable);
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
uint16_t mask1, uint16_t id2,
uint16_t mask2, uint32_t fifo, bool enable);
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id,
uint32_t mask, uint32_t fifo, bool enable);
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1,
uint16_t id2, uint16_t id3, uint16_t id4,
uint32_t fifo, bool enable);
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1,
uint32_t id2, uint32_t fifo, bool enable);
void can_enable_irq(uint32_t canport, uint32_t irq);
void can_disable_irq(uint32_t canport, uint32_t irq);
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data);
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext,
bool *rtr, uint32_t *fmi, uint8_t *length, uint8_t *data);
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr,
uint8_t length, uint8_t *data);
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
bool *ext, bool *rtr, uint32_t *fmi, uint8_t *length,
uint8_t *data);
void can_fifo_release(uint32_t canport, uint8_t fifo);
bool can_available_mailbox(uint32_t canport);

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@@ -95,7 +95,8 @@ specific memorymap.h header before including this header file.*/
* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
*/
#define DAC_CR_MAMP2_SHIFT 24
/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude
values
@ingroup dac_defines
Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
@@ -207,7 +208,8 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
*/
#define DAC_CR_MAMP1_SHIFT 8
/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude
values
@ingroup dac_defines
Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
@@ -404,8 +406,10 @@ void dac_set_trigger_source(uint32_t dac_trig_src);
void dac_set_waveform_generation(uint32_t dac_wave_ens);
void dac_disable_waveform_generation(data_channel dac_channel);
void dac_set_waveform_characteristics(uint32_t dac_mamp);
void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format, data_channel dac_channel);
void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2, data_align dac_data_format);
void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format,
data_channel dac_channel);
void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2,
data_align dac_data_format);
void dac_software_trigger(data_channel dac_channel);
END_DECLS

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@@ -386,12 +386,14 @@ group.
BEGIN_DECLS
void dma_channel_reset(uint32_t dma, uint8_t channel);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel,
uint32_t interrupts);
bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts);
void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel);
void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio);
void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t channel,
uint32_t peripheral_size);
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
@@ -407,7 +409,8 @@ void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
void dma_enable_channel(uint32_t dma, uint8_t channel);
void dma_disable_channel(uint32_t dma, uint8_t channel);
void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address);
void dma_set_peripheral_address(uint32_t dma, uint8_t channel,
uint32_t address);
void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address);
void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number);

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@@ -573,12 +573,14 @@ BEGIN_DECLS
*/
void dma_stream_reset(uint32_t dma, uint8_t stream);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts);
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream,
uint32_t interrupts);
bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt);
void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction);
void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio);
void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size);
void dma_set_peripheral_size(uint32_t dma, uint8_t stream,
uint32_t peripheral_size);
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream);
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream);

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@@ -287,8 +287,10 @@ BEGIN_DECLS
* sounding functions that have very different functionality.
*/
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios);
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios);
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down,
uint16_t gpios);
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed,
uint16_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios);
END_DECLS

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@@ -356,7 +356,8 @@ specific memorymap.h header before including this header file.*/
BEGIN_DECLS
void spi_reset(uint32_t spi_peripheral);
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst);
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
uint32_t dff, uint32_t lsbfirst);
void spi_enable(uint32_t spi);
void spi_disable(uint32_t spi);
uint16_t spi_clean_disable(uint32_t spi);

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@@ -1070,16 +1070,20 @@ void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
enum tim_oc_mode oc_mode);
enum tim_oc_mode oc_mode);
void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_polarity_high(uint32_t timer_peripheral,
enum tim_oc_id oc_id);
void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value);
void timer_set_oc_idle_state_set(uint32_t timer_peripheral,
enum tim_oc_id oc_id);
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral,
enum tim_oc_id oc_id);
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id,
uint32_t value);
void timer_enable_break_main_output(uint32_t timer_peripheral);
void timer_disable_break_main_output(uint32_t timer_peripheral);
void timer_enable_break_automatic_output(uint32_t timer_peripheral);
@@ -1098,9 +1102,12 @@ void timer_generate_event(uint32_t timer_peripheral, uint32_t event);
uint32_t timer_get_counter(uint32_t timer_peripheral);
void timer_set_counter(uint32_t timer_peripheral, uint32_t count);
void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic, enum tim_ic_filter flt);
void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic, enum tim_ic_psc psc);
void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic, enum tim_ic_input in);
void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic,
enum tim_ic_filter flt);
void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic,
enum tim_ic_psc psc);
void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic,
enum tim_ic_input in);
void timer_ic_enable(uint32_t timer, enum tim_ic_id ic);
void timer_ic_disable(uint32_t timer, enum tim_ic_id ic);

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@@ -49,7 +49,8 @@ specific memorymap.h header before including this header file.*/
/* ITR1_RMP */
/****************************************************************************/
/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal Trigger 1 Remap
/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal
Trigger 1 Remap
Only available in F2 and F4 series.
@ingroup timer_defines
@@ -99,7 +100,8 @@ enum tim_ic_pol {
BEGIN_DECLS
void timer_set_option(uint32_t timer_peripheral, uint32_t option);
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol);
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic,
enum tim_ic_pol pol);
END_DECLS

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@@ -605,7 +605,8 @@ and ADC2
/* JL[2:0]: Discontinous mode channel count injected channels. */
/****************************************************************************/
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro
injected channels.
@ingroup adc_defines
@{*/
@@ -655,7 +656,8 @@ void adc_disable_discontinuous_mode_injected(uint32_t adc);
void adc_enable_automatic_injected_group_conversion(uint32_t adc);
void adc_disable_automatic_injected_group_conversion(uint32_t adc);
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
uint8_t channel);
void adc_enable_scan_mode(uint32_t adc);
void adc_disable_scan_mode(uint32_t adc);
void adc_enable_eoc_interrupt_injected(uint32_t adc);

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@@ -948,7 +948,8 @@ Line Devices only
BEGIN_DECLS
void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint16_t gpios);
void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf,
uint16_t gpios);
void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin);
void gpio_primary_remap(uint32_t swjenable, uint32_t maps);
void gpio_secondary_remap(uint32_t maps);

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@@ -47,7 +47,9 @@ enum tim_ic_pol {
BEGIN_DECLS
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol);
void timer_ic_set_polarity(uint32_t timer,
enum tim_ic_id ic,
enum tim_ic_pol pol);
END_DECLS

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@@ -34,55 +34,55 @@ struct usb_desc_head {
struct usb_device_desc {
struct usb_desc_head h; /* Size 0x12, ID 0x01 */
uint16_t bcd_usb; /* USB Version */
uint16_t bcd_usb; /* USB Version */
uint8_t class; /* Device class */
uint8_t sub_class; /* Subclass code */
uint8_t protocol; /* Protocol code */
uint8_t max_psize; /* Maximum packet size -> 64bytes */
uint16_t vendor; /* Vendor number */
uint16_t product; /* Device number */
uint16_t bcd_dev; /* Device version */
uint8_t man_desc; /* Index of manufacturer string desc */
uint8_t prod_desc; /* Index of product string desc */
uint8_t sn_desc; /* Index of serial number string desc */
uint8_t num_conf; /* Number of possible configurations */
uint8_t sub_class; /* Subclass code */
uint8_t protocol; /* Protocol code */
uint8_t max_psize; /* Maximum packet size -> 64bytes */
uint16_t vendor; /* Vendor number */
uint16_t product; /* Device number */
uint16_t bcd_dev; /* Device version */
uint8_t man_desc; /* Index of manufacturer string desc */
uint8_t prod_desc; /* Index of product string desc */
uint8_t sn_desc; /* Index of serial number string desc */
uint8_t num_conf; /* Number of possible configurations */
};
struct usb_conf_desc_header {
struct usb_desc_head h; /* Size 0x09, Id 0x02 */
uint16_t tot_leng; /* Total length of data */
uint8_t num_int; /* Number of interfaces */
uint8_t conf_val; /* Configuration selector */
uint8_t conf_desc; /* Index of conf string desc */
uint16_t tot_leng; /* Total length of data */
uint8_t num_int; /* Number of interfaces */
uint8_t conf_val; /* Configuration selector */
uint8_t conf_desc; /* Index of conf string desc */
uint8_t attr; /* Attribute bitmap:
* 7 : Bus powered
* 6 : Self powered
* 5 : Remote wakeup
* 4..0 : Reserved -> 0000
*/
uint8_t max_power; /* Maximum power consumption in 2mA steps */
uint8_t max_power; /* Maximum power consumption in 2mA steps */
};
struct usb_int_desc_header {
struct usb_desc_head h; /* Size 0x09, Id 0x04 */
uint8_t iface_num; /* Interface id number */
uint8_t alt_setting; /* Alternative setting selector */
uint8_t num_endp; /* Endpoints used */
uint8_t iface_num; /* Interface id number */
uint8_t alt_setting; /* Alternative setting selector */
uint8_t num_endp; /* Endpoints used */
uint8_t class; /* Interface class */
uint8_t sub_class; /* Subclass code */
uint8_t protocol; /* Protocol code */
uint8_t iface_desc; /* Index of interface string desc */
uint8_t sub_class; /* Subclass code */
uint8_t protocol; /* Protocol code */
uint8_t iface_desc; /* Index of interface string desc */
};
struct usb_ep_desc {
struct usb_desc_head h; /* Size 0x07, Id 0x05 */
uint8_t ep_addr; /* Endpoint address:
uint8_t ep_addr; /* Endpoint address:
0..3 : Endpoint Number
4..6 : Reserved -> 0
7 : Direction 0=out 1=in */
uint8_t ep_attr; /* Endpoint attributes */
uint16_t max_psize; /* Maximum packet size -> 64bytes */
uint8_t interval; /* Interval for polling endpoint
uint8_t ep_attr; /* Endpoint attributes */
uint16_t max_psize; /* Maximum packet size -> 64bytes */
uint8_t interval; /* Interval for polling endpoint
data. Ignored for bulk & control
endpoints. */
};
@@ -95,7 +95,7 @@ struct usb_conf_desc {
struct usb_string_desc {
struct usb_desc_head h; /* Size > 0x02, Id 0x03 */
uint16_t string[]; /* String UTF16 encoded */
uint16_t string[]; /* String UTF16 encoded */
};
#endif

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@@ -505,8 +505,10 @@ void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_rtcpre(uint32_t rtcpre);
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);

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@@ -804,7 +804,8 @@ void adc_disable_discontinuous_mode_injected(uint32_t adc);
void adc_enable_automatic_injected_group_conversion(uint32_t adc);
void adc_disable_automatic_injected_group_conversion(uint32_t adc);
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
uint8_t channel);
void adc_enable_scan_mode(uint32_t adc);
void adc_disable_scan_mode(uint32_t adc);
void adc_enable_eoc_interrupt_injected(uint32_t adc);
@@ -837,8 +838,10 @@ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
void adc_set_clk_prescale(uint32_t prescaler);
void adc_set_multi_mode(uint32_t mode);
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity);
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity);
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
uint32_t polarity);
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
uint32_t polarity);
void adc_set_resolution(uint32_t adc, uint16_t resolution);
void adc_enable_overrun_interrupt(uint32_t adc);
void adc_disable_overrun_interrupt(uint32_t adc);

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@@ -511,8 +511,10 @@ void rcc_set_ppre2(uint32_t ppre2);
void rcc_set_ppre1(uint32_t ppre1);
void rcc_set_hpre(uint32_t hpre);
void rcc_set_rtcpre(uint32_t rtcpre);
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp,
uint32_t pllq);
uint32_t rcc_system_clock_source(void);
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
void rcc_backupdomain_reset(void);

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@@ -251,8 +251,10 @@ BEGIN_DECLS
* TODO: this should all really be moved to a "common" gpio header
*/
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios);
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios);
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down,
uint16_t gpios);
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed,
uint16_t gpios);
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios);
END_DECLS

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@@ -442,7 +442,8 @@ void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
void rcc_set_sysclk_source(uint32_t clk);
void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, uint32_t divisor);
void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier,
uint32_t divisor);
void rcc_set_pll_source(uint32_t pllsrc);
void rcc_set_adcpre(uint32_t adcpre);
void rcc_set_ppre2(uint32_t ppre2);

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@@ -39,8 +39,8 @@
#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038)
#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C)
#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100)
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + \
4*(x-1))
#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 \
+ 4*(x-1))
/* Host-mode Control and Status Registers */
#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400)
@@ -89,8 +89,9 @@
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
/* Data FIFO */
#define OTG_FS_FIFO(x) ((volatile uint32_t*)(USB_OTG_FS_BASE + \
(((x) + 1) << 12)))
#define OTG_FS_FIFO(x) ((volatile uint32_t*)(USB_OTG_FS_BASE \
+ (((x) + 1) \
<< 12)))
/* Global CSRs */
/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */

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@@ -145,8 +145,8 @@
#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
/* Data FIFO */
#define OTG_HS_FIFO(x) ((volatile uint32_t*)(USB_OTG_HS_BASE + \
OTG_FIFO(x)))
#define OTG_HS_FIFO(x) ((volatile uint32_t*)(USB_OTG_HS_BASE \
+ OTG_FIFO(x)))
/* Global CSRs */
/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */

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@@ -63,7 +63,8 @@ extern usbd_device * usbd_init(const usbd_driver *driver,
const struct usb_device_descriptor *dev,
const struct usb_config_descriptor *conf,
const char **strings, int num_strings,
uint8_t *control_buffer, uint16_t control_buffer_size);
uint8_t *control_buffer,
uint16_t control_buffer_size);
extern void usbd_register_reset_callback(usbd_device *usbd_dev,
void (*callback)(void));
@@ -86,14 +87,15 @@ extern int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type,
/* <usb_standard.c> */
extern void usbd_register_set_config_callback(usbd_device *usbd_dev,
void (*callback)(usbd_device *usbd_dev, uint16_t wValue));
void (*callback)(usbd_device *usbd_dev, uint16_t wValue));
/* Functions to be provided by the hardware abstraction layer */
extern void usbd_poll(usbd_device *usbd_dev);
extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected);
extern void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size,
void (*callback)(usbd_device *usbd_dev, uint8_t ep));
extern void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
uint16_t max_size,
void (*callback)(usbd_device *usbd_dev, uint8_t ep));
extern uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len);
@@ -101,7 +103,8 @@ extern uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
extern uint16_t usbd_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
void *buf, uint16_t len);
extern void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
extern void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr,
uint8_t stall);
extern uint8_t usbd_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
extern void usbd_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);