Add RCC and FLASH support for STM32F2
This commit is contained in:
Stephen Caudle
@@ -28,7 +28,7 @@ CFLAGS = -Os -g -Wall -Wextra -I../../include -fno-common \
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-ffunction-sections -fdata-sections -MD -DSTM32F2
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# ARFLAGS = rcsv
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ARFLAGS = rcs
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OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o
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OBJS = vector.o gpio.o systick.o i2c.o spi.o nvic.o usart.o rcc.o flash.o
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#VPATH += ../usb
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VPATH += ../stm32_common
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250
lib/stm32f2/flash.c
Normal file
250
lib/stm32f2/flash.c
Normal file
@@ -0,0 +1,250 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/f2/flash.h>
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static inline void flash_set_program_size(u32 psize)
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{
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FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
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FLASH_CR |= psize;
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}
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void flash_data_cache_enable(void)
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{
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FLASH_ACR |= FLASH_DCE;
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}
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void flash_dcache_disable(void)
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{
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FLASH_ACR &= ~FLASH_DCE;
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}
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void flash_icache_enable(void)
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{
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FLASH_ACR |= FLASH_ICE;
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}
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void flash_icache_disable(void)
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{
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FLASH_ACR &= ~FLASH_ICE;
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}
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void flash_prefetch_enable(void)
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{
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FLASH_ACR |= FLASH_PRFTEN;
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}
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void flash_prefetch_disable(void)
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{
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FLASH_ACR &= ~FLASH_PRFTEN;
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}
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void flash_dcache_reset(void)
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{
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FLASH_ACR |= FLASH_DCRST;
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}
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void flash_icache_reset(void)
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{
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FLASH_ACR |= FLASH_ICRST;
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}
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void flash_set_ws(u32 ws)
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{
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u32 reg32;
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reg32 = FLASH_ACR;
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reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
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reg32 |= ws;
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FLASH_ACR = reg32;
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}
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void flash_unlock(void)
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{
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/* Authorize the FPEC access. */
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FLASH_KEYR = FLASH_KEY1;
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FLASH_KEYR = FLASH_KEY2;
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}
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void flash_lock(void)
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{
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FLASH_CR |= FLASH_LOCK;
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}
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void flash_clear_pgserr_flag(void)
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{
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FLASH_SR |= FLASH_PGSERR;
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}
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void flash_clear_pgperr_flag(void)
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{
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FLASH_SR |= FLASH_PGPERR;
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}
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void flash_clear_pgaerr_flag(void)
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{
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FLASH_SR |= FLASH_PGAERR;
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}
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void flash_clear_eop_flag(void)
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{
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FLASH_SR |= FLASH_EOP;
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}
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void flash_clear_wrperr_flag(void)
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{
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FLASH_SR |= FLASH_WRPERR;
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}
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void flash_clear_bsy_flag(void)
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{
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FLASH_SR &= ~FLASH_BSY;
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}
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void flash_clear_status_flags(void)
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{
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flash_clear_pgserr_flag();
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flash_clear_pgperr_flag();
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flash_clear_pgaerr_flag();
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flash_clear_eop_flag();
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flash_clear_wrperr_flag();
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flash_clear_bsy_flag();
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}
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void flash_unlock_option_bytes(void)
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{
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FLASH_OPTKEYR = FLASH_OPTKEY1;
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FLASH_OPTKEYR = FLASH_OPTKEY2;
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}
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void flash_lock_option_bytes(void)
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{
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FLASH_OPTCR |= FLASH_OPTLOCK;
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}
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void flash_wait_for_last_operation(void)
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{
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while ((FLASH_SR & FLASH_BSY) == FLASH_BSY)
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;
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}
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void flash_program_double_word(u32 address, u64 data, u32 program_size)
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{
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/* Ensure that all flash operations are complete. */
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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/* Enable writes to flash. */
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FLASH_CR |= FLASH_PG;
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/* Program the first half of the word. */
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MMIO64(address) = data;
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/* Wait for the write to complete. */
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flash_wait_for_last_operation();
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/* Disable writes to flash. */
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FLASH_CR &= ~FLASH_PG;
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}
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void flash_program_word(u32 address, u32 data, u32 program_size)
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{
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/* Ensure that all flash operations are complete. */
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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/* Enable writes to flash. */
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FLASH_CR |= FLASH_PG;
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/* Program the first half of the word. */
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MMIO32(address) = data;
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/* Wait for the write to complete. */
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flash_wait_for_last_operation();
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/* Disable writes to flash. */
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FLASH_CR &= ~FLASH_PG;
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}
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void flash_program_half_word(u32 address, u16 data, u32 program_size)
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{
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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FLASH_CR |= FLASH_PG;
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MMIO16(address) = data;
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
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}
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void flash_program_byte(u32 address, u8 data, u32 program_size)
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{
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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FLASH_CR |= FLASH_PG;
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MMIO8(address) = data;
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_PG; /* Disable the PG bit. */
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}
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void flash_erase_sector(u32 sector, u32 program_size)
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{
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
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FLASH_CR |= sector;
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FLASH_CR |= FLASH_STRT;
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_SER;
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FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
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}
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void flash_erase_all_sectors(u32 program_size)
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{
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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FLASH_CR |= FLASH_MER; /* Enable mass erase. */
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FLASH_CR |= FLASH_STRT; /* Trigger the erase. */
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_MER; /* Disable mass erase. */
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}
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void flash_program_option_bytes(u32 data)
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{
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flash_wait_for_last_operation();
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if (FLASH_OPTCR & FLASH_OPTLOCK)
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flash_unlock_option_bytes();
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FLASH_OPTCR = data & ~0x3;
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FLASH_OPTCR |= FLASH_OPTSTRT; /* Enable option byte programming. */
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flash_wait_for_last_operation();
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}
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412
lib/stm32f2/rcc.c
Normal file
412
lib/stm32f2/rcc.c
Normal file
@@ -0,0 +1,412 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
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* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
|
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/f2/rcc.h>
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#include <libopencm3/stm32/f2/flash.h>
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/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset */
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u32 rcc_ppre1_frequency = 8000000;
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u32 rcc_ppre2_frequency = 8000000;
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/* TODO: Create a table for these values */
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#define RCC_PLL_M 8
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#define RCC_PLL_N 336
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#define RCC_PLL_P 2
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#define RCC_PLL_Q 7
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#define RCC_PLLI2S_N 192
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#define RCC_PLLI2S_R 5
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void rcc_osc_ready_int_clear(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYC;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYC;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYC;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYC;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR |= RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR |= RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR |= RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR |= RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR |= RCC_CIR_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CIR &= ~RCC_CIR_PLLRDYIE;
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break;
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case HSE:
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RCC_CIR &= ~RCC_CIR_HSERDYIE;
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break;
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case HSI:
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RCC_CIR &= ~RCC_CIR_HSIRDYIE;
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break;
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case LSE:
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RCC_CIR &= ~RCC_CIR_LSERDYIE;
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break;
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case LSI:
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RCC_CIR &= ~RCC_CIR_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(osc_t osc)
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{
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switch (osc) {
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case PLL:
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return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
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break;
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case HSE:
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return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
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break;
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case HSI:
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return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
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break;
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case LSE:
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return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
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break;
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case LSI:
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return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
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break;
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}
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/* Shouldn't be reached. */
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return -1;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CIR |= RCC_CIR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIR & RCC_CIR_CSSF) != 0);
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}
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void rcc_wait_for_osc_ready(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CR & RCC_CR_PLLRDY) == 0);
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break;
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case HSE:
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while ((RCC_CR & RCC_CR_HSERDY) == 0);
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break;
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case HSI:
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while ((RCC_CR & RCC_CR_HSIRDY) == 0);
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break;
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case LSE:
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while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
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break;
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case LSI:
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while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
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break;
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}
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}
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void rcc_wait_for_sysclk_status(osc_t osc)
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{
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switch (osc) {
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case PLL:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL);
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break;
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case HSE:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE);
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break;
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case HSI:
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while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR |= RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(osc_t osc)
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{
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switch (osc) {
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case PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case HSI:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
|
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case LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
|
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}
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|
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
|
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|
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
|
||||
}
|
||||
|
||||
void rcc_osc_bypass_enable(osc_t osc)
|
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{
|
||||
switch (osc) {
|
||||
case HSE:
|
||||
RCC_CR |= RCC_CR_HSEBYP;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR |= RCC_BDCR_LSEBYP;
|
||||
break;
|
||||
case PLL:
|
||||
case HSI:
|
||||
case LSI:
|
||||
/* Do nothing, only HSE/LSE allowed here. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_osc_bypass_disable(osc_t osc)
|
||||
{
|
||||
switch (osc) {
|
||||
case HSE:
|
||||
RCC_CR &= ~RCC_CR_HSEBYP;
|
||||
break;
|
||||
case LSE:
|
||||
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
|
||||
break;
|
||||
case PLL:
|
||||
case HSI:
|
||||
case LSI:
|
||||
/* Do nothing, only HSE/LSE allowed here. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
|
||||
{
|
||||
*reg |= en;
|
||||
}
|
||||
|
||||
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
|
||||
{
|
||||
*reg &= ~en;
|
||||
}
|
||||
|
||||
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
|
||||
{
|
||||
*reg |= reset;
|
||||
}
|
||||
|
||||
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
|
||||
{
|
||||
*reg &= ~clear_reset;
|
||||
}
|
||||
|
||||
void rcc_set_sysclk_source(u32 clk)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 1) | (1 << 0));
|
||||
RCC_CFGR = (reg32 | clk);
|
||||
}
|
||||
|
||||
void rcc_set_pll_source(u32 pllsrc)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_PLLCFGR;
|
||||
reg32 &= ~(1 << 22);
|
||||
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
|
||||
}
|
||||
|
||||
void rcc_set_ppre2(u32 ppre2)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13));
|
||||
RCC_CFGR = (reg32 | (ppre2 << 11));
|
||||
}
|
||||
|
||||
void rcc_set_ppre1(u32 ppre1)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10));
|
||||
RCC_CFGR = (reg32 | (ppre1 << 8));
|
||||
}
|
||||
|
||||
void rcc_set_hpre(u32 hpre)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
|
||||
RCC_CFGR = (reg32 | (hpre << 4));
|
||||
}
|
||||
|
||||
void rcc_set_rtcpre(u32 rtcpre)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = RCC_CFGR;
|
||||
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
|
||||
RCC_CFGR = (reg32 | (rtcpre << 16));
|
||||
}
|
||||
|
||||
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
|
||||
{
|
||||
RCC_PLLCFGR = pllm |
|
||||
(plln << 6) |
|
||||
(((pllp >> 1) - 1) << 16) |
|
||||
(pllq << 24);
|
||||
}
|
||||
|
||||
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
|
||||
{
|
||||
RCC_PLLCFGR = pllm |
|
||||
(plln << 6) |
|
||||
(((pllp >> 1) - 1) << 16) |
|
||||
RCC_PLLCFGR_PLLSRC |
|
||||
(pllq << 24);
|
||||
}
|
||||
|
||||
u32 rcc_system_clock_source(void)
|
||||
{
|
||||
/* Return the clock source which is used as system clock. */
|
||||
return ((RCC_CFGR & 0x000c) >> 2);
|
||||
}
|
||||
|
||||
void rcc_clock_setup_in_hse_8mhz_out_120mhz(void)
|
||||
{
|
||||
/* Enable internal high-speed oscillator. */
|
||||
rcc_osc_on(HSI);
|
||||
rcc_wait_for_osc_ready(HSI);
|
||||
|
||||
/* Select HSI as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
|
||||
|
||||
/* Enable external high-speed oscillator 8MHz. */
|
||||
rcc_osc_on(HSE);
|
||||
rcc_wait_for_osc_ready(HSE);
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_HSE);
|
||||
|
||||
/*
|
||||
* Set prescalers for AHB, ADC, ABP1, ABP2.
|
||||
* Do this before touching the PLL (TODO: why?).
|
||||
*/
|
||||
rcc_set_hpre(RCC_CFGR_HPRE_DIV_NONE); /* Set. 120MHz Max. 120MHz */
|
||||
rcc_set_ppre1(RCC_CFGR_PPRE_DIV_4); /* Set. 30MHz Max. 30MHz */
|
||||
rcc_set_ppre2(RCC_CFGR_PPRE_DIV_2); /* Set. 60MHz Max. 60MHz */
|
||||
|
||||
rcc_set_main_pll_hse(RCC_PLL_M, RCC_PLL_N, RCC_PLL_P, RCC_PLL_Q);
|
||||
|
||||
/* Enable PLL oscillator and wait for it to stabilize. */
|
||||
rcc_osc_on(PLL);
|
||||
rcc_wait_for_osc_ready(PLL);
|
||||
|
||||
/*
|
||||
* @3.3V
|
||||
* Sysclk runs with 120MHz -> 3 waitstates.
|
||||
* 0WS from 0-30MHz
|
||||
* 1WS from 30-60MHz
|
||||
* 2WS from 60-90MHz
|
||||
* 3WS from 90-120MHz
|
||||
*/
|
||||
flash_set_ws(FLASH_PRFTEN | FLASH_ICE | FLASH_DCE | FLASH_LATENCY_3WS);
|
||||
|
||||
/* Select PLL as SYSCLK source. */
|
||||
rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
|
||||
|
||||
/* Wait for PLL clock to be selected. */
|
||||
rcc_wait_for_sysclk_status(PLL);
|
||||
|
||||
/* Set the peripheral clock frequencies used */
|
||||
rcc_ppre1_frequency = 30000000;
|
||||
rcc_ppre2_frequency = 60000000;
|
||||
}
|
||||
|
||||
void rcc_backupdomain_reset(void)
|
||||
{
|
||||
/* Set the backup domain software reset. */
|
||||
RCC_BDCR |= RCC_BDCR_BDRST;
|
||||
|
||||
/* Clear the backup domain software reset. */
|
||||
RCC_BDCR &= ~RCC_BDCR_BDRST;
|
||||
}
|
||||
Reference in New Issue
Block a user