Changed to use stdint types.
This commit is contained in:
Piotr Esden-Tempski
@@ -54,9 +54,9 @@ LGPL License Terms @ref lgpl_license
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#include <libopencm3/stm32/f1/flash.h>
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/** Default ppre1 peripheral clock frequency after reset. */
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u32 rcc_ppre1_frequency = 8000000;
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uint32_t rcc_ppre1_frequency = 8000000;
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/** Default ppre2 peripheral clock frequency after reset. */
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u32 rcc_ppre2_frequency = 8000000;
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uint32_t rcc_ppre2_frequency = 8000000;
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/*---------------------------------------------------------------------------*/
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/** @brief RCC Clear the Oscillator Ready Interrupt Flag
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@@ -435,7 +435,7 @@ if they are controlled by the same register</em>.
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@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
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*/
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void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
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void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
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{
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*reg |= en;
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}
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@@ -457,7 +457,7 @@ disabling.
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@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
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*/
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void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
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void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
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{
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*reg &= ~en;
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}
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@@ -478,7 +478,7 @@ they are controlled by the same register</em>.
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@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
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*/
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void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
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void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
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{
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*reg |= reset;
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}
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@@ -499,7 +499,7 @@ simultaneously <em>only if they are controlled by the same register</em>.
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@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
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*/
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void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
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void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
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{
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*reg &= ~clear_reset;
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}
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@@ -510,9 +510,9 @@ void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
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@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs
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*/
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void rcc_set_sysclk_source(u32 clk)
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void rcc_set_sysclk_source(uint32_t clk)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 1) | (1 << 0));
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@@ -527,9 +527,9 @@ void rcc_set_sysclk_source(u32 clk)
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@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll_multiplication_factor(u32 mul)
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void rcc_set_pll_multiplication_factor(uint32_t mul)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18));
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@@ -544,9 +544,9 @@ void rcc_set_pll_multiplication_factor(u32 mul)
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@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll2_multiplication_factor(u32 mul)
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void rcc_set_pll2_multiplication_factor(uint32_t mul)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR2;
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reg32 &= ~((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8));
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@@ -561,9 +561,9 @@ void rcc_set_pll2_multiplication_factor(u32 mul)
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@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
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*/
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void rcc_set_pll3_multiplication_factor(u32 mul)
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void rcc_set_pll3_multiplication_factor(uint32_t mul)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR2;
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reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12));
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@@ -578,9 +578,9 @@ void rcc_set_pll3_multiplication_factor(u32 mul)
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@param[in] pllsrc Unsigned int32. PLL clock source @ref rcc_cfgr_pcs
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*/
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void rcc_set_pll_source(u32 pllsrc)
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 16);
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@@ -595,9 +595,9 @@ void rcc_set_pll_source(u32 pllsrc)
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@param[in] pllxtpre Unsigned int32. HSE division factor @ref rcc_cfgr_hsepre
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*/
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void rcc_set_pllxtpre(u32 pllxtpre)
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void rcc_set_pllxtpre(uint32_t pllxtpre)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 17);
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@@ -609,12 +609,12 @@ void rcc_set_pllxtpre(u32 pllxtpre)
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The ADC's have a common clock prescale setting.
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@param[in] adcpre u32. Prescale divider taken from @ref rcc_cfgr_adcpre
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@param[in] adcpre uint32_t. Prescale divider taken from @ref rcc_cfgr_adcpre
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*/
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void rcc_set_adcpre(u32 adcpre)
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void rcc_set_adcpre(uint32_t adcpre)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 14) | (1 << 15));
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@@ -627,9 +627,9 @@ void rcc_set_adcpre(u32 adcpre)
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@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre
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*/
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void rcc_set_ppre2(u32 ppre2)
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void rcc_set_ppre2(uint32_t ppre2)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13));
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@@ -644,9 +644,9 @@ void rcc_set_ppre2(u32 ppre2)
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@param[in] ppre1 Unsigned int32. APB1 prescale factor @ref rcc_cfgr_apb1pre
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*/
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void rcc_set_ppre1(u32 ppre1)
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void rcc_set_ppre1(uint32_t ppre1)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10));
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@@ -659,9 +659,9 @@ void rcc_set_ppre1(u32 ppre1)
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@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
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*/
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void rcc_set_hpre(u32 hpre)
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void rcc_set_hpre(uint32_t hpre)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
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@@ -679,40 +679,40 @@ The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
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@param[in] usbpre Unsigned int32. USB prescale factor @ref rcc_cfgr_usbpre
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*/
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void rcc_set_usbpre(u32 usbpre)
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void rcc_set_usbpre(uint32_t usbpre)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(1 << 22);
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RCC_CFGR = (reg32 | (usbpre << 22));
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}
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void rcc_set_prediv1(u32 prediv)
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void rcc_set_prediv1(uint32_t prediv)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR2;
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reg32 &= ~(1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
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RCC_CFGR2 |= (reg32 | prediv);
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}
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void rcc_set_prediv2(u32 prediv)
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void rcc_set_prediv2(uint32_t prediv)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR2;
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reg32 &= ~(1 << 7) | (1 << 6) | (1 << 5) | (1 << 4);
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RCC_CFGR2 |= (reg32 | (prediv << 4));
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}
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void rcc_set_prediv1_source(u32 rccsrc)
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void rcc_set_prediv1_source(uint32_t rccsrc)
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{
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RCC_CFGR2 &= ~(1 << 16);
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RCC_CFGR2 |= (rccsrc << 16);
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}
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void rcc_set_mco(u32 mcosrc)
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void rcc_set_mco(uint32_t mcosrc)
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{
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u32 reg32;
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24));
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RCC_CFGR |= (reg32 | (mcosrc << 24));
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@@ -727,7 +727,7 @@ void rcc_set_mco(u32 mcosrc)
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@li 02 indicates PLL
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*/
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u32 rcc_system_clock_source(void)
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uint32_t rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return (RCC_CFGR & 0x000c) >> 2;
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