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Changed to use stdint types.

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This commit is contained in:
Piotr Esden-Tempski
2013-06-12 19:11:22 -07:00
parent 7df63fcae0
commit 34de1e776e
127 changed files with 1886 additions and 1895 deletions
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142
lib/stm32/f1/adc.c
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@@ -122,7 +122,7 @@ If the ADC is already on this function call has no effect.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_power_on(u32 adc)
void adc_power_on(uint32_t adc)
{
if (!(ADC_CR2(adc) & ADC_CR2_ADON)) {
ADC_CR2(adc) |= ADC_CR2_ADON;
@@ -142,7 +142,7 @@ adc_start_conversion_regular.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_start_conversion_direct(u32 adc)
void adc_start_conversion_direct(uint32_t adc)
{
if (ADC_CR2(adc) & ADC_CR2_ADON) {
ADC_CR2(adc) |= ADC_CR2_ADON;
@@ -186,7 +186,7 @@ Dual A/D converter modes possible:
@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod
*/
void adc_set_dual_mode(u32 mode)
void adc_set_dual_mode(uint32_t mode)
{
ADC1_CR1 |= mode;
}
@@ -202,7 +202,7 @@ adc_reg_base.
@returns bool. End of conversion flag.
*/
bool adc_eoc(u32 adc)
bool adc_eoc(uint32_t adc)
{
return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
}
@@ -217,7 +217,7 @@ adc_reg_base.
@returns bool. End of conversion flag.
*/
bool adc_eoc_injected(u32 adc)
bool adc_eoc_injected(uint32_t adc)
{
return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
}
@@ -234,7 +234,7 @@ adc_reg_base.
@returns Unsigned int32 conversion result.
*/
u32 adc_read_regular(u32 adc)
uint32_t adc_read_regular(uint32_t adc)
{
return ADC_DR(adc);
}
@@ -253,7 +253,7 @@ adc_reg_base.
@returns Unsigned int32 conversion result.
*/
u32 adc_read_injected(u32 adc, u8 reg)
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
{
switch (reg) {
case 1:
@@ -281,7 +281,7 @@ adc_reg_base.
@param[in] offset Unsigned int32.
*/
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
{
switch (reg) {
case 1:
@@ -310,7 +310,7 @@ alignment takes place, so the thresholds are left-aligned.
adc_reg_base.
*/
void adc_enable_analog_watchdog_regular(u32 adc)
void adc_enable_analog_watchdog_regular(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDEN;
}
@@ -322,7 +322,7 @@ void adc_enable_analog_watchdog_regular(u32 adc)
adc_reg_base.
*/
void adc_disable_analog_watchdog_regular(u32 adc)
void adc_disable_analog_watchdog_regular(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
}
@@ -338,7 +338,7 @@ alignment takes place, so the thresholds are left-aligned.
adc_reg_base.
*/
void adc_enable_analog_watchdog_injected(u32 adc)
void adc_enable_analog_watchdog_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JAWDEN;
}
@@ -350,7 +350,7 @@ void adc_enable_analog_watchdog_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_analog_watchdog_injected(u32 adc)
void adc_disable_analog_watchdog_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
}
@@ -372,7 +372,7 @@ adc_reg_base.
adc_cr1_discnum.
*/
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
{
if ((length-1) > 7) {
return;
@@ -388,7 +388,7 @@ void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
adc_reg_base.
*/
void adc_disable_discontinuous_mode_regular(u32 adc)
void adc_disable_discontinuous_mode_regular(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
}
@@ -404,7 +404,7 @@ entire group has been converted.
adc_reg_base.
*/
void adc_enable_discontinuous_mode_injected(u32 adc)
void adc_enable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
}
@@ -416,7 +416,7 @@ void adc_enable_discontinuous_mode_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_discontinuous_mode_injected(u32 adc)
void adc_disable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
}
@@ -432,7 +432,7 @@ channels is disabled as required.
adc_reg_base
*/
void adc_enable_automatic_injected_group_conversion(u32 adc)
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
{
adc_disable_external_trigger_injected(adc);
ADC_CR1(adc) |= ADC_CR1_JAUTO;
@@ -445,7 +445,7 @@ void adc_enable_automatic_injected_group_conversion(u32 adc)
adc_reg_base.
*/
void adc_disable_automatic_injected_group_conversion(u32 adc)
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
}
@@ -467,7 +467,7 @@ adc_enable_analog_watchdog_regular.
adc_reg_base.
*/
void adc_enable_analog_watchdog_on_all_channels(u32 adc)
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
}
@@ -490,9 +490,9 @@ adc_reg_base.
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel.
*/
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */
if (channel < 18) {
@@ -513,7 +513,7 @@ previous one. It can use single, continuous or discontinuous mode.
adc_reg_base.
*/
void adc_enable_scan_mode(u32 adc)
void adc_enable_scan_mode(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_SCAN;
}
@@ -524,7 +524,7 @@ void adc_enable_scan_mode(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_scan_mode(u32 adc)
void adc_disable_scan_mode(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_SCAN;
}
@@ -536,7 +536,7 @@ void adc_disable_scan_mode(u32 adc)
adc_reg_base.
*/
void adc_enable_eoc_interrupt_injected(u32 adc)
void adc_enable_eoc_interrupt_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
}
@@ -548,7 +548,7 @@ void adc_enable_eoc_interrupt_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_eoc_interrupt_injected(u32 adc)
void adc_disable_eoc_interrupt_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
}
@@ -560,7 +560,7 @@ void adc_disable_eoc_interrupt_injected(u32 adc)
adc_reg_base.
*/
void adc_enable_awd_interrupt(u32 adc)
void adc_enable_awd_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDIE;
}
@@ -572,7 +572,7 @@ void adc_enable_awd_interrupt(u32 adc)
adc_reg_base.
*/
void adc_disable_awd_interrupt(u32 adc)
void adc_disable_awd_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
}
@@ -584,7 +584,7 @@ void adc_disable_awd_interrupt(u32 adc)
adc_reg_base.
*/
void adc_enable_eoc_interrupt(u32 adc)
void adc_enable_eoc_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_EOCIE;
}
@@ -596,7 +596,7 @@ void adc_enable_eoc_interrupt(u32 adc)
adc_reg_base.
*/
void adc_disable_eoc_interrupt(u32 adc)
void adc_disable_eoc_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
}
@@ -611,7 +611,7 @@ This enables both the sensor and the reference voltage measurements on channels
adc_reg_base.
*/
void adc_enable_temperature_sensor(u32 adc)
void adc_enable_temperature_sensor(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_TSVREFE;
}
@@ -626,7 +626,7 @@ voltage measurements.
adc_reg_base.
*/
void adc_disable_temperature_sensor(u32 adc)
void adc_disable_temperature_sensor(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_TSVREFE;
}
@@ -646,7 +646,7 @@ This is not the same as the ADC start conversion operation.
adc_reg_base.
*/
void adc_start_conversion_regular(u32 adc)
void adc_start_conversion_regular(uint32_t adc)
{
/* Start conversion on regular channels. */
ADC_CR2(adc) |= ADC_CR2_SWSTART;
@@ -670,7 +670,7 @@ This is not the same as the ADC start conversion operation.
adc_reg_base.
*/
void adc_start_conversion_injected(u32 adc)
void adc_start_conversion_injected(uint32_t adc)
{
/* Start conversion on injected channels. */
ADC_CR2(adc) |= ADC_CR2_JSWSTART;
@@ -710,9 +710,9 @@ adc_reg_base.
for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3.
*/
void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK));
reg32 |= (trigger);
@@ -727,7 +727,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
adc_reg_base.
*/
void adc_disable_external_trigger_regular(u32 adc)
void adc_disable_external_trigger_regular(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG;
}
@@ -763,9 +763,9 @@ adc_reg_base.
adc_trigger_injected_12 for ADC1 and ADC2, or @ref adc_trigger_injected_3 for
ADC3.
*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]
*/
@@ -781,7 +781,7 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
adc_reg_base.
*/
void adc_disable_external_trigger_injected(u32 adc)
void adc_disable_external_trigger_injected(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG;
}
@@ -793,7 +793,7 @@ void adc_disable_external_trigger_injected(u32 adc)
adc_reg_base.
*/
void adc_set_left_aligned(u32 adc)
void adc_set_left_aligned(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_ALIGN;
}
@@ -805,7 +805,7 @@ void adc_set_left_aligned(u32 adc)
adc_reg_base.
*/
void adc_set_right_aligned(u32 adc)
void adc_set_right_aligned(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
}
@@ -821,7 +821,7 @@ mode.
adc_reg_base.
*/
void adc_enable_dma(u32 adc)
void adc_enable_dma(uint32_t adc)
{
if ((adc == ADC1) | (adc == ADC3)) {
ADC_CR2(adc) |= ADC_CR2_DMA;
@@ -835,7 +835,7 @@ void adc_enable_dma(u32 adc)
adc_reg_base.
*/
void adc_disable_dma(u32 adc)
void adc_disable_dma(uint32_t adc)
{
if ((adc == ADC1) | (adc == ADC3)) {
ADC_CR2(adc) &= ~ADC_CR2_DMA;
@@ -852,7 +852,7 @@ done before every calibration operation.
adc_reg_base.
*/
void adc_reset_calibration(u32 adc)
void adc_reset_calibration(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_RSTCAL;
while (ADC_CR2(adc) & ADC_CR2_RSTCAL);
@@ -872,7 +872,7 @@ powered on. before calibration starts
adc_reg_base.
*/
void adc_calibration(u32 adc)
void adc_calibration(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_CAL;
while (ADC_CR2(adc) & ADC_CR2_CAL);
@@ -888,7 +888,7 @@ group immediately following completion of the previous channel group conversion.
adc_reg_base.
*/
void adc_set_continuous_conversion_mode(u32 adc)
void adc_set_continuous_conversion_mode(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_CONT;
}
@@ -903,7 +903,7 @@ and stops.
adc_reg_base.
*/
void adc_set_single_conversion_mode(u32 adc)
void adc_set_single_conversion_mode(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_CONT;
}
@@ -921,7 +921,7 @@ If the ADC is already on this function call will initiate a conversion.
adc_reg_base.
*/
void adc_on(u32 adc)
void adc_on(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_ADON;
}
@@ -935,7 +935,7 @@ Turn off the ADC to reduce power consumption to a few microamps.
adc_reg_base.
*/
void adc_off(u32 adc)
void adc_off(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ADON;
}
@@ -952,9 +952,9 @@ adc_channel.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
*/
void adc_set_sample_time(u32 adc, u8 channel, u8 time)
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
{
u32 reg32;
uint32_t reg32;
if (channel < 10) {
reg32 = ADC_SMPR2(adc);
@@ -980,10 +980,10 @@ adc_reg_base.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
*/
void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
{
u8 i;
u32 reg32 = 0;
uint8_t i;
uint32_t reg32 = 0;
for (i = 0; i <= 9; i++) {
reg32 |= (time << (i * 3));
@@ -1004,11 +1004,11 @@ adc_reg_base.
@param[in] threshold Unsigned int8. Upper threshold value.
*/
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
{
u32 reg32 = 0;
uint32_t reg32 = 0;
reg32 = (u32)threshold;
reg32 = (uint32_t)threshold;
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_HTR(adc) = reg32;
}
@@ -1021,11 +1021,11 @@ adc_reg_base.
@param[in] threshold Unsigned int8. Lower threshold value.
*/
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
{
u32 reg32 = 0;
uint32_t reg32 = 0;
reg32 = (u32)threshold;
reg32 = (uint32_t)threshold;
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_LTR(adc) = reg32;
}
@@ -1044,10 +1044,10 @@ adc_reg_base.
0..18.
*/
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
u8 i = 0;
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
uint8_t i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16) {
@@ -1085,10 +1085,10 @@ adc_reg_base.
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
*/
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
u32 reg32 = 0;
u8 i = 0;
uint32_t reg32 = 0;
uint8_t i = 0;
/* Maximum sequence length is 4 channels. */
if (length > 4) {
@@ -1109,15 +1109,15 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
/* Aliases */
#ifdef __GNUC__
void adc_set_continous_conversion_mode(u32 adc)
void adc_set_continous_conversion_mode(uint32_t adc)
__attribute__((alias("adc_set_continuous_conversion_mode")));
void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time)
__attribute__((alias("adc_set_sample_time")));
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time)
__attribute__((alias("adc_set_sample_time_on_all_channels")));
void adc_enable_jeoc_interrupt(u32 adc)
void adc_enable_jeoc_interrupt(uint32_t adc)
__attribute__((alias("adc_enable_eoc_interrupt_injected")));
void adc_disable_jeoc_interrupt(u32 adc)
void adc_disable_jeoc_interrupt(uint32_t adc)
__attribute__((alias("adc_disable_eoc_interrupt_injected")));
#endif