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Changed to use stdint types.

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This commit is contained in:
Piotr Esden-Tempski
2013-06-12 19:11:22 -07:00
parent 7df63fcae0
commit 34de1e776e
127 changed files with 1886 additions and 1895 deletions
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142
lib/stm32/f1/adc.c
View File

@@ -122,7 +122,7 @@ If the ADC is already on this function call has no effect.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_power_on(u32 adc)
void adc_power_on(uint32_t adc)
{
if (!(ADC_CR2(adc) & ADC_CR2_ADON)) {
ADC_CR2(adc) |= ADC_CR2_ADON;
@@ -142,7 +142,7 @@ adc_start_conversion_regular.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_start_conversion_direct(u32 adc)
void adc_start_conversion_direct(uint32_t adc)
{
if (ADC_CR2(adc) & ADC_CR2_ADON) {
ADC_CR2(adc) |= ADC_CR2_ADON;
@@ -186,7 +186,7 @@ Dual A/D converter modes possible:
@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod
*/
void adc_set_dual_mode(u32 mode)
void adc_set_dual_mode(uint32_t mode)
{
ADC1_CR1 |= mode;
}
@@ -202,7 +202,7 @@ adc_reg_base.
@returns bool. End of conversion flag.
*/
bool adc_eoc(u32 adc)
bool adc_eoc(uint32_t adc)
{
return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
}
@@ -217,7 +217,7 @@ adc_reg_base.
@returns bool. End of conversion flag.
*/
bool adc_eoc_injected(u32 adc)
bool adc_eoc_injected(uint32_t adc)
{
return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
}
@@ -234,7 +234,7 @@ adc_reg_base.
@returns Unsigned int32 conversion result.
*/
u32 adc_read_regular(u32 adc)
uint32_t adc_read_regular(uint32_t adc)
{
return ADC_DR(adc);
}
@@ -253,7 +253,7 @@ adc_reg_base.
@returns Unsigned int32 conversion result.
*/
u32 adc_read_injected(u32 adc, u8 reg)
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
{
switch (reg) {
case 1:
@@ -281,7 +281,7 @@ adc_reg_base.
@param[in] offset Unsigned int32.
*/
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
{
switch (reg) {
case 1:
@@ -310,7 +310,7 @@ alignment takes place, so the thresholds are left-aligned.
adc_reg_base.
*/
void adc_enable_analog_watchdog_regular(u32 adc)
void adc_enable_analog_watchdog_regular(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDEN;
}
@@ -322,7 +322,7 @@ void adc_enable_analog_watchdog_regular(u32 adc)
adc_reg_base.
*/
void adc_disable_analog_watchdog_regular(u32 adc)
void adc_disable_analog_watchdog_regular(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
}
@@ -338,7 +338,7 @@ alignment takes place, so the thresholds are left-aligned.
adc_reg_base.
*/
void adc_enable_analog_watchdog_injected(u32 adc)
void adc_enable_analog_watchdog_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JAWDEN;
}
@@ -350,7 +350,7 @@ void adc_enable_analog_watchdog_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_analog_watchdog_injected(u32 adc)
void adc_disable_analog_watchdog_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
}
@@ -372,7 +372,7 @@ adc_reg_base.
adc_cr1_discnum.
*/
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
{
if ((length-1) > 7) {
return;
@@ -388,7 +388,7 @@ void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
adc_reg_base.
*/
void adc_disable_discontinuous_mode_regular(u32 adc)
void adc_disable_discontinuous_mode_regular(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
}
@@ -404,7 +404,7 @@ entire group has been converted.
adc_reg_base.
*/
void adc_enable_discontinuous_mode_injected(u32 adc)
void adc_enable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
}
@@ -416,7 +416,7 @@ void adc_enable_discontinuous_mode_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_discontinuous_mode_injected(u32 adc)
void adc_disable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
}
@@ -432,7 +432,7 @@ channels is disabled as required.
adc_reg_base
*/
void adc_enable_automatic_injected_group_conversion(u32 adc)
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
{
adc_disable_external_trigger_injected(adc);
ADC_CR1(adc) |= ADC_CR1_JAUTO;
@@ -445,7 +445,7 @@ void adc_enable_automatic_injected_group_conversion(u32 adc)
adc_reg_base.
*/
void adc_disable_automatic_injected_group_conversion(u32 adc)
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
}
@@ -467,7 +467,7 @@ adc_enable_analog_watchdog_regular.
adc_reg_base.
*/
void adc_enable_analog_watchdog_on_all_channels(u32 adc)
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
}
@@ -490,9 +490,9 @@ adc_reg_base.
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel.
*/
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */
if (channel < 18) {
@@ -513,7 +513,7 @@ previous one. It can use single, continuous or discontinuous mode.
adc_reg_base.
*/
void adc_enable_scan_mode(u32 adc)
void adc_enable_scan_mode(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_SCAN;
}
@@ -524,7 +524,7 @@ void adc_enable_scan_mode(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_scan_mode(u32 adc)
void adc_disable_scan_mode(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_SCAN;
}
@@ -536,7 +536,7 @@ void adc_disable_scan_mode(u32 adc)
adc_reg_base.
*/
void adc_enable_eoc_interrupt_injected(u32 adc)
void adc_enable_eoc_interrupt_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
}
@@ -548,7 +548,7 @@ void adc_enable_eoc_interrupt_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_eoc_interrupt_injected(u32 adc)
void adc_disable_eoc_interrupt_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
}
@@ -560,7 +560,7 @@ void adc_disable_eoc_interrupt_injected(u32 adc)
adc_reg_base.
*/
void adc_enable_awd_interrupt(u32 adc)
void adc_enable_awd_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDIE;
}
@@ -572,7 +572,7 @@ void adc_enable_awd_interrupt(u32 adc)
adc_reg_base.
*/
void adc_disable_awd_interrupt(u32 adc)
void adc_disable_awd_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
}
@@ -584,7 +584,7 @@ void adc_disable_awd_interrupt(u32 adc)
adc_reg_base.
*/
void adc_enable_eoc_interrupt(u32 adc)
void adc_enable_eoc_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_EOCIE;
}
@@ -596,7 +596,7 @@ void adc_enable_eoc_interrupt(u32 adc)
adc_reg_base.
*/
void adc_disable_eoc_interrupt(u32 adc)
void adc_disable_eoc_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
}
@@ -611,7 +611,7 @@ This enables both the sensor and the reference voltage measurements on channels
adc_reg_base.
*/
void adc_enable_temperature_sensor(u32 adc)
void adc_enable_temperature_sensor(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_TSVREFE;
}
@@ -626,7 +626,7 @@ voltage measurements.
adc_reg_base.
*/
void adc_disable_temperature_sensor(u32 adc)
void adc_disable_temperature_sensor(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_TSVREFE;
}
@@ -646,7 +646,7 @@ This is not the same as the ADC start conversion operation.
adc_reg_base.
*/
void adc_start_conversion_regular(u32 adc)
void adc_start_conversion_regular(uint32_t adc)
{
/* Start conversion on regular channels. */
ADC_CR2(adc) |= ADC_CR2_SWSTART;
@@ -670,7 +670,7 @@ This is not the same as the ADC start conversion operation.
adc_reg_base.
*/
void adc_start_conversion_injected(u32 adc)
void adc_start_conversion_injected(uint32_t adc)
{
/* Start conversion on injected channels. */
ADC_CR2(adc) |= ADC_CR2_JSWSTART;
@@ -710,9 +710,9 @@ adc_reg_base.
for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3.
*/
void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK));
reg32 |= (trigger);
@@ -727,7 +727,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
adc_reg_base.
*/
void adc_disable_external_trigger_regular(u32 adc)
void adc_disable_external_trigger_regular(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG;
}
@@ -763,9 +763,9 @@ adc_reg_base.
adc_trigger_injected_12 for ADC1 and ADC2, or @ref adc_trigger_injected_3 for
ADC3.
*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]
*/
@@ -781,7 +781,7 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
adc_reg_base.
*/
void adc_disable_external_trigger_injected(u32 adc)
void adc_disable_external_trigger_injected(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG;
}
@@ -793,7 +793,7 @@ void adc_disable_external_trigger_injected(u32 adc)
adc_reg_base.
*/
void adc_set_left_aligned(u32 adc)
void adc_set_left_aligned(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_ALIGN;
}
@@ -805,7 +805,7 @@ void adc_set_left_aligned(u32 adc)
adc_reg_base.
*/
void adc_set_right_aligned(u32 adc)
void adc_set_right_aligned(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
}
@@ -821,7 +821,7 @@ mode.
adc_reg_base.
*/
void adc_enable_dma(u32 adc)
void adc_enable_dma(uint32_t adc)
{
if ((adc == ADC1) | (adc == ADC3)) {
ADC_CR2(adc) |= ADC_CR2_DMA;
@@ -835,7 +835,7 @@ void adc_enable_dma(u32 adc)
adc_reg_base.
*/
void adc_disable_dma(u32 adc)
void adc_disable_dma(uint32_t adc)
{
if ((adc == ADC1) | (adc == ADC3)) {
ADC_CR2(adc) &= ~ADC_CR2_DMA;
@@ -852,7 +852,7 @@ done before every calibration operation.
adc_reg_base.
*/
void adc_reset_calibration(u32 adc)
void adc_reset_calibration(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_RSTCAL;
while (ADC_CR2(adc) & ADC_CR2_RSTCAL);
@@ -872,7 +872,7 @@ powered on. before calibration starts
adc_reg_base.
*/
void adc_calibration(u32 adc)
void adc_calibration(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_CAL;
while (ADC_CR2(adc) & ADC_CR2_CAL);
@@ -888,7 +888,7 @@ group immediately following completion of the previous channel group conversion.
adc_reg_base.
*/
void adc_set_continuous_conversion_mode(u32 adc)
void adc_set_continuous_conversion_mode(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_CONT;
}
@@ -903,7 +903,7 @@ and stops.
adc_reg_base.
*/
void adc_set_single_conversion_mode(u32 adc)
void adc_set_single_conversion_mode(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_CONT;
}
@@ -921,7 +921,7 @@ If the ADC is already on this function call will initiate a conversion.
adc_reg_base.
*/
void adc_on(u32 adc)
void adc_on(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_ADON;
}
@@ -935,7 +935,7 @@ Turn off the ADC to reduce power consumption to a few microamps.
adc_reg_base.
*/
void adc_off(u32 adc)
void adc_off(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ADON;
}
@@ -952,9 +952,9 @@ adc_channel.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
*/
void adc_set_sample_time(u32 adc, u8 channel, u8 time)
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
{
u32 reg32;
uint32_t reg32;
if (channel < 10) {
reg32 = ADC_SMPR2(adc);
@@ -980,10 +980,10 @@ adc_reg_base.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
*/
void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
{
u8 i;
u32 reg32 = 0;
uint8_t i;
uint32_t reg32 = 0;
for (i = 0; i <= 9; i++) {
reg32 |= (time << (i * 3));
@@ -1004,11 +1004,11 @@ adc_reg_base.
@param[in] threshold Unsigned int8. Upper threshold value.
*/
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
{
u32 reg32 = 0;
uint32_t reg32 = 0;
reg32 = (u32)threshold;
reg32 = (uint32_t)threshold;
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_HTR(adc) = reg32;
}
@@ -1021,11 +1021,11 @@ adc_reg_base.
@param[in] threshold Unsigned int8. Lower threshold value.
*/
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
{
u32 reg32 = 0;
uint32_t reg32 = 0;
reg32 = (u32)threshold;
reg32 = (uint32_t)threshold;
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_LTR(adc) = reg32;
}
@@ -1044,10 +1044,10 @@ adc_reg_base.
0..18.
*/
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
u8 i = 0;
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
uint8_t i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16) {
@@ -1085,10 +1085,10 @@ adc_reg_base.
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
*/
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
u32 reg32 = 0;
u8 i = 0;
uint32_t reg32 = 0;
uint8_t i = 0;
/* Maximum sequence length is 4 channels. */
if (length > 4) {
@@ -1109,15 +1109,15 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
/* Aliases */
#ifdef __GNUC__
void adc_set_continous_conversion_mode(u32 adc)
void adc_set_continous_conversion_mode(uint32_t adc)
__attribute__((alias("adc_set_continuous_conversion_mode")));
void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time)
__attribute__((alias("adc_set_sample_time")));
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time)
__attribute__((alias("adc_set_sample_time_on_all_channels")));
void adc_enable_jeoc_interrupt(u32 adc)
void adc_enable_jeoc_interrupt(uint32_t adc)
__attribute__((alias("adc_enable_eoc_interrupt_injected")));
void adc_disable_jeoc_interrupt(u32 adc)
void adc_disable_jeoc_interrupt(uint32_t adc)
__attribute__((alias("adc_disable_eoc_interrupt_injected")));
#endif

6
lib/stm32/f1/ethernet.c
View File

@@ -19,7 +19,7 @@
#include <libopencm3/stm32/f1/ethernet.h>
void eth_smi_write(u8 phy, u8 reg, u16 data)
void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data)
{
/* Set PHY and register addresses for write access. */
ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA);
@@ -35,7 +35,7 @@ void eth_smi_write(u8 phy, u8 reg, u16 data)
while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
}
u16 eth_smi_read(u8 phy, u8 reg)
uint16_t eth_smi_read(uint8_t phy, uint8_t reg)
{
/* Set PHY and register addresses for write access. */
ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA | ETH_MACMIIAR_MW);
@@ -48,5 +48,5 @@ u16 eth_smi_read(u8 phy, u8 reg)
while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
/* Set register value. */
return (u16)(ETH_MACMIIDR);
return (uint16_t)(ETH_MACMIIDR);
}

14
lib/stm32/f1/exti.c
View File

@@ -20,7 +20,7 @@
#include <libopencm3/stm32/exti.h>
#include <libopencm3/stm32/f1/gpio.h>
void exti_set_trigger(u32 extis, exti_trigger_type trig)
void exti_set_trigger(uint32_t extis, exti_trigger_type trig)
{
switch (trig) {
case EXTI_TRIGGER_RISING:
@@ -38,7 +38,7 @@ void exti_set_trigger(u32 extis, exti_trigger_type trig)
}
}
void exti_enable_request(u32 extis)
void exti_enable_request(uint32_t extis)
{
/* Enable interrupts. */
EXTI_IMR |= extis;
@@ -47,7 +47,7 @@ void exti_enable_request(u32 extis)
EXTI_EMR |= extis;
}
void exti_disable_request(u32 extis)
void exti_disable_request(uint32_t extis)
{
/* Disable interrupts. */
EXTI_IMR &= ~extis;
@@ -60,7 +60,7 @@ void exti_disable_request(u32 extis)
* Reset the interrupt request by writing a 1 to the corresponding
* pending bit register.
*/
void exti_reset_request(u32 extis)
void exti_reset_request(uint32_t extis)
{
EXTI_PR |= extis;
}
@@ -68,7 +68,7 @@ void exti_reset_request(u32 extis)
/*
* Check the flag of a given EXTI interrupt.
* */
u32 exti_get_flag_status(u32 exti)
uint32_t exti_get_flag_status(uint32_t exti)
{
return EXTI_PR & exti;
}
@@ -79,9 +79,9 @@ u32 exti_get_flag_status(u32 exti)
*
* TODO: This could be rewritten in fewer lines of code.
*/
void exti_select_source(u32 exti, u32 gpioport)
void exti_select_source(uint32_t exti, uint32_t gpioport)
{
u8 shift, bits;
uint8_t shift, bits;
shift = bits = 0;

22
lib/stm32/f1/flash.c
View File

@@ -40,9 +40,9 @@ void flash_halfcycle_disable(void)
FLASH_ACR &= ~FLASH_ACR_HLFCYA;
}
void flash_set_ws(u32 ws)
void flash_set_ws(uint32_t ws)
{
u32 reg32;
uint32_t reg32;
reg32 = FLASH_ACR;
reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
@@ -93,7 +93,7 @@ void flash_clear_status_flags(void)
flash_clear_bsy_flag();
}
u32 flash_get_status_flags(void)
uint32_t flash_get_status_flags(void)
{
return FLASH_SR &= (FLASH_SR_PGERR |
FLASH_SR_EOP |
@@ -113,7 +113,7 @@ void flash_wait_for_last_operation(void)
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
void flash_program_word(u32 address, u32 data)
void flash_program_word(uint32_t address, uint32_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
@@ -122,13 +122,13 @@ void flash_program_word(u32 address, u32 data)
FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
(*(volatile u16 *)address) = (u16)data;
(*(volatile uint16_t *)address) = (uint16_t)data;
/* Wait for the write to complete. */
flash_wait_for_last_operation();
/* Program the second half of the word. */
(*(volatile u16 *)(address + 2)) = data >> 16;
(*(volatile uint16_t *)(address + 2)) = data >> 16;
/* Wait for the write to complete. */
flash_wait_for_last_operation();
@@ -137,20 +137,20 @@ void flash_program_word(u32 address, u32 data)
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data)
void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_PG;
(*(volatile u16 *)address) = data;
(*(volatile uint16_t *)address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_page(u32 page_address)
void flash_erase_page(uint32_t page_address)
{
flash_wait_for_last_operation();
@@ -187,7 +187,7 @@ void flash_erase_option_bytes(void)
FLASH_CR &= ~FLASH_CR_OPTER; /* Disable option byte erase. */
}
void flash_program_option_bytes(u32 address, u16 data)
void flash_program_option_bytes(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
@@ -196,7 +196,7 @@ void flash_program_option_bytes(u32 address, u16 data)
}
FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */
(*(volatile u16 *)address) = data;
(*(volatile uint16_t *)address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_OPTPG; /* Disable option byte programming. */
}

12
lib/stm32/f1/gpio.c
View File

@@ -92,10 +92,10 @@ open drain/push pull), for a set of GPIO pins on a given GPIO port.
them.
*/
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint16_t gpios)
{
u16 i, offset = 0;
u32 crl = 0, crh = 0, tmp32 = 0;
uint16_t i, offset = 0;
uint32_t crl = 0, crh = 0, tmp32 = 0;
/*
* We want to set the config only for the pins mentioned in gpios,
@@ -138,7 +138,7 @@ Enable the EVENTOUT signal and select the port and pin to be used.
@param[in] evoutport Unsigned int8. Port for EVENTOUT signal @ref afio_evcr_port
@param[in] evoutpin Unsigned int8. Pin for EVENTOUT signal @ref afio_evcr_pin
*/
void gpio_set_eventout(u8 evoutport, u8 evoutpin)
void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin)
{
AFIO_EVCR = AFIO_EVCR_EVOE | evoutport | evoutpin;
}
@@ -166,7 +166,7 @@ afio_remap, @ref afio_remap_can1, @ref afio_remap_tim3, @ref afio_remap_tim2,
@ref afio_remap_tim1, @ref afio_remap_usart3. For connectivity line devices
only @ref afio_remap_cld are also available.
*/
void gpio_primary_remap(u32 swjdisable, u32 maps)
void gpio_primary_remap(uint32_t swjdisable, uint32_t maps)
{
AFIO_MAPR |= (swjdisable & AFIO_MAPR_SWJ_MASK) | (maps & 0x1FFFFF);
}
@@ -185,7 +185,7 @@ The AFIO remapping feature is used only with the STM32F10x series.
@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref
afio_remap2
*/
void gpio_secondary_remap(u32 maps)
void gpio_secondary_remap(uint32_t maps)
{
AFIO_MAPR2 |= maps;
}

74
lib/stm32/f1/rcc.c
View File

@@ -54,9 +54,9 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/f1/flash.h>
/** Default ppre1 peripheral clock frequency after reset. */
u32 rcc_ppre1_frequency = 8000000;
uint32_t rcc_ppre1_frequency = 8000000;
/** Default ppre2 peripheral clock frequency after reset. */
u32 rcc_ppre2_frequency = 8000000;
uint32_t rcc_ppre2_frequency = 8000000;
/*---------------------------------------------------------------------------*/
/** @brief RCC Clear the Oscillator Ready Interrupt Flag
@@ -435,7 +435,7 @@ if they are controlled by the same register</em>.
@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
*/
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg |= en;
}
@@ -457,7 +457,7 @@ disabling.
@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
*/
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg &= ~en;
}
@@ -478,7 +478,7 @@ they are controlled by the same register</em>.
@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
*/
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
{
*reg |= reset;
}
@@ -499,7 +499,7 @@ simultaneously <em>only if they are controlled by the same register</em>.
@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
*/
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
{
*reg &= ~clear_reset;
}
@@ -510,9 +510,9 @@ void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs
*/
void rcc_set_sysclk_source(u32 clk)
void rcc_set_sysclk_source(uint32_t clk)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
@@ -527,9 +527,9 @@ void rcc_set_sysclk_source(u32 clk)
@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
*/
void rcc_set_pll_multiplication_factor(u32 mul)
void rcc_set_pll_multiplication_factor(uint32_t mul)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18));
@@ -544,9 +544,9 @@ void rcc_set_pll_multiplication_factor(u32 mul)
@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
*/
void rcc_set_pll2_multiplication_factor(u32 mul)
void rcc_set_pll2_multiplication_factor(uint32_t mul)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR2;
reg32 &= ~((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8));
@@ -561,9 +561,9 @@ void rcc_set_pll2_multiplication_factor(u32 mul)
@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
*/
void rcc_set_pll3_multiplication_factor(u32 mul)
void rcc_set_pll3_multiplication_factor(uint32_t mul)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR2;
reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12));
@@ -578,9 +578,9 @@ void rcc_set_pll3_multiplication_factor(u32 mul)
@param[in] pllsrc Unsigned int32. PLL clock source @ref rcc_cfgr_pcs
*/
void rcc_set_pll_source(u32 pllsrc)
void rcc_set_pll_source(uint32_t pllsrc)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(1 << 16);
@@ -595,9 +595,9 @@ void rcc_set_pll_source(u32 pllsrc)
@param[in] pllxtpre Unsigned int32. HSE division factor @ref rcc_cfgr_hsepre
*/
void rcc_set_pllxtpre(u32 pllxtpre)
void rcc_set_pllxtpre(uint32_t pllxtpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(1 << 17);
@@ -609,12 +609,12 @@ void rcc_set_pllxtpre(u32 pllxtpre)
The ADC's have a common clock prescale setting.
@param[in] adcpre u32. Prescale divider taken from @ref rcc_cfgr_adcpre
@param[in] adcpre uint32_t. Prescale divider taken from @ref rcc_cfgr_adcpre
*/
void rcc_set_adcpre(u32 adcpre)
void rcc_set_adcpre(uint32_t adcpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 14) | (1 << 15));
@@ -627,9 +627,9 @@ void rcc_set_adcpre(u32 adcpre)
@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre
*/
void rcc_set_ppre2(u32 ppre2)
void rcc_set_ppre2(uint32_t ppre2)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13));
@@ -644,9 +644,9 @@ void rcc_set_ppre2(u32 ppre2)
@param[in] ppre1 Unsigned int32. APB1 prescale factor @ref rcc_cfgr_apb1pre
*/
void rcc_set_ppre1(u32 ppre1)
void rcc_set_ppre1(uint32_t ppre1)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10));
@@ -659,9 +659,9 @@ void rcc_set_ppre1(u32 ppre1)
@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
*/
void rcc_set_hpre(u32 hpre)
void rcc_set_hpre(uint32_t hpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
@@ -679,40 +679,40 @@ The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
@param[in] usbpre Unsigned int32. USB prescale factor @ref rcc_cfgr_usbpre
*/
void rcc_set_usbpre(u32 usbpre)
void rcc_set_usbpre(uint32_t usbpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(1 << 22);
RCC_CFGR = (reg32 | (usbpre << 22));
}
void rcc_set_prediv1(u32 prediv)
void rcc_set_prediv1(uint32_t prediv)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR2;
reg32 &= ~(1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
RCC_CFGR2 |= (reg32 | prediv);
}
void rcc_set_prediv2(u32 prediv)
void rcc_set_prediv2(uint32_t prediv)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR2;
reg32 &= ~(1 << 7) | (1 << 6) | (1 << 5) | (1 << 4);
RCC_CFGR2 |= (reg32 | (prediv << 4));
}
void rcc_set_prediv1_source(u32 rccsrc)
void rcc_set_prediv1_source(uint32_t rccsrc)
{
RCC_CFGR2 &= ~(1 << 16);
RCC_CFGR2 |= (rccsrc << 16);
}
void rcc_set_mco(u32 mcosrc)
void rcc_set_mco(uint32_t mcosrc)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24));
RCC_CFGR |= (reg32 | (mcosrc << 24));
@@ -727,7 +727,7 @@ void rcc_set_mco(u32 mcosrc)
@li 02 indicates PLL
*/
u32 rcc_system_clock_source(void)
uint32_t rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return (RCC_CFGR & 0x000c) >> 2;

28
lib/stm32/f1/rtc.c
View File

@@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
void rtc_awake_from_off(osc_t clock_source)
{
u32 reg32;
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);
@@ -106,7 +106,7 @@ void rtc_awake_from_off(osc_t clock_source)
void rtc_enter_config_mode(void)
{
u32 reg32;
uint32_t reg32;
/* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */
while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
@@ -117,7 +117,7 @@ void rtc_enter_config_mode(void)
void rtc_exit_config_mode(void)
{
u32 reg32;
uint32_t reg32;
/* Exit configuration mode. */
RTC_CRL &= ~RTC_CRL_CNF;
@@ -126,7 +126,7 @@ void rtc_exit_config_mode(void)
while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
}
void rtc_set_alarm_time(u32 alarm_time)
void rtc_set_alarm_time(uint32_t alarm_time)
{
rtc_enter_config_mode();
RTC_ALRL = (alarm_time & 0x0000ffff);
@@ -148,7 +148,7 @@ void rtc_disable_alarm(void)
rtc_exit_config_mode();
}
void rtc_set_prescale_val(u32 prescale_val)
void rtc_set_prescale_val(uint32_t prescale_val)
{
rtc_enter_config_mode();
RTC_PRLL = prescale_val & 0x0000ffff; /* PRL[15:0] */
@@ -156,22 +156,22 @@ void rtc_set_prescale_val(u32 prescale_val)
rtc_exit_config_mode();
}
u32 rtc_get_counter_val(void)
uint32_t rtc_get_counter_val(void)
{
return (RTC_CNTH << 16) | RTC_CNTL;
}
u32 rtc_get_prescale_div_val(void)
uint32_t rtc_get_prescale_div_val(void)
{
return (RTC_DIVH << 16) | RTC_DIVL;
}
u32 rtc_get_alarm_val(void)
uint32_t rtc_get_alarm_val(void)
{
return (RTC_ALRH << 16) | RTC_ALRL;
}
void rtc_set_counter_val(u32 counter_val)
void rtc_set_counter_val(uint32_t counter_val)
{
rtc_enter_config_mode();
RTC_CNTH = (counter_val & 0xffff0000) >> 16; /* CNT[31:16] */
@@ -237,9 +237,9 @@ void rtc_clear_flag(rtcflag_t flag_val)
}
}
u32 rtc_check_flag(rtcflag_t flag_val)
uint32_t rtc_check_flag(rtcflag_t flag_val)
{
u32 reg32;
uint32_t reg32;
/* Read correct flag. */
switch (flag_val) {
@@ -262,7 +262,7 @@ u32 rtc_check_flag(rtcflag_t flag_val)
void rtc_awake_from_standby(void)
{
u32 reg32;
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);
@@ -279,9 +279,9 @@ void rtc_awake_from_standby(void)
while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
}
void rtc_auto_awake(osc_t clock_source, u32 prescale_val)
void rtc_auto_awake(osc_t clock_source, uint32_t prescale_val)
{
u32 reg32;
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);

2
lib/stm32/f1/timer.c
View File

@@ -46,7 +46,7 @@ in which case this file must be added to the compile list. */
@param[in] pol ::tim_ic_pol. Input Capture polarity.
*/
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_pol pol)
{
if (pol) {