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Changed to use stdint types.

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This commit is contained in:
Piotr Esden-Tempski
2013-06-12 19:11:22 -07:00
parent 7df63fcae0
commit 34de1e776e
127 changed files with 1886 additions and 1895 deletions
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4
lib/stm32/common/crc_common_all.c
View File

@@ -49,7 +49,7 @@ computation is complete.
@returns int32 Computed CRC result
*/
u32 crc_calculate(u32 data)
uint32_t crc_calculate(uint32_t data)
{
CRC_DR = data;
/* Data sheet says this blocks until it's ready.... */
@@ -67,7 +67,7 @@ until the computation of each word is complete.
@returns int32 Final computed CRC result
*/
u32 crc_calculate_block(u32 *datap, int size)
uint32_t crc_calculate_block(uint32_t *datap, int size)
{
int i;

24
lib/stm32/common/dac_common_all.c
View File

@@ -82,7 +82,7 @@ Both DAC channels are enabled, and both triggers are set to the same timer
dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT);
dma_set_read_from_memory(DMA2,DMA_CHANNEL3);
dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(u32) &DAC_DHR8RD);
dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(uint32_t) &DAC_DHR8RD);
dma_enable_channel(DMA2,DMA_CHANNEL3);
...
dac_trigger_enable(CHANNEL_D);
@@ -320,12 +320,12 @@ void dac_trigger_disable(data_channel dac_channel)
Sets the digital to analog converter trigger source, which can be taken from
various timers, an external trigger or a software trigger.
@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref
@param[in] dac_trig_src uint32_t. Taken from @ref dac_trig2_sel or @ref
dac_trig1_sel or a logical OR of one of each of these to set both channels
simultaneously.
*/
void dac_set_trigger_source(u32 dac_trig_src)
void dac_set_trigger_source(uint32_t dac_trig_src)
{
DAC_CR |= dac_trig_src;
}
@@ -339,11 +339,11 @@ existing output values in the DAC output registers.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en
@param[in] dac_wave_ens uint32_t. Taken from @ref dac_wave1_en or @ref dac_wave2_en
or a logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_generation(u32 dac_wave_ens)
void dac_set_waveform_generation(uint32_t dac_wave_ens)
{
DAC_CR |= dac_wave_ens;
}
@@ -387,11 +387,11 @@ the signal output.
become read-only.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a
@param[in] dac_mamp uint32_t. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a
logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_characteristics(u32 dac_mamp)
void dac_set_waveform_characteristics(uint32_t dac_mamp)
{
DAC_CR |= dac_mamp;
}
@@ -405,12 +405,12 @@ data to be converted on a channel. The data can be aligned as follows:
@li right-aligned 12 bit data in bits 0-11
@li left aligned 12 bit data in bits 4-15
@param[in] dac_data u16 with appropriate alignment.
@param[in] dac_data uint16_t with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Alignment and size.
@param[in] dac_channel enum ::data_channel.
*/
void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format,
void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format,
data_channel dac_channel)
{
if (dac_channel == CHANNEL_1) {
@@ -448,13 +448,13 @@ Loads the appropriate digital to analog converter dual data register with 12 or
simultaneous or independent analog output. The data in both channels are aligned
identically.
@param[in] dac_data1 u16 for channel 1 with appropriate alignment.
@param[in] dac_data2 u16 for channel 2 with appropriate alignment.
@param[in] dac_data1 uint16_t for channel 1 with appropriate alignment.
@param[in] dac_data2 uint16_t for channel 2 with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or
12 bit.
*/
void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2,
void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2,
data_align dac_data_format)
{
switch (dac_data_format) {

58
lib/stm32/common/dma_common_f13.c
View File

@@ -49,7 +49,7 @@ The channel is disabled and configuration registers are cleared.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_channel_reset(u32 dma, u8 channel)
void dma_channel_reset(uint32_t dma, uint8_t channel)
{
/* Disable channel and reset config bits. */
DMA_CCR(dma, channel) = 0;
@@ -75,10 +75,10 @@ same channel may be cleared by using the logical OR of the interrupt flags.
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts)
{
/* Get offset to interrupt flag location in channel field */
u32 flags = (interrupts << DMA_FLAG_OFFSET(channel));
uint32_t flags = (interrupts << DMA_FLAG_OFFSET(channel));
DMA_IFCR(dma) = flags;
}
@@ -93,10 +93,10 @@ The interrupt flag for the channel is returned.
@returns bool interrupt flag is set.
*/
bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt)
bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupt)
{
/* get offset to interrupt flag location in channel field. */
u32 flag = (interrupt << DMA_FLAG_OFFSET(channel));
uint32_t flag = (interrupt << DMA_FLAG_OFFSET(channel));
return ((DMA_ISR(dma) & flag) > 0);
}
@@ -111,7 +111,7 @@ intervention.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_mem2mem_mode(u32 dma, u8 channel)
void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
@@ -128,7 +128,7 @@ hardware priority.
@param[in] prio unsigned int32. Priority level @ref dma_ch_pri.
*/
void dma_set_priority(u32 dma, u8 channel, u32 prio)
void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
DMA_CCR(dma, channel) |= prio;
@@ -145,7 +145,7 @@ alignment information if the source and destination widths do not match.
@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth.
*/
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK);
@@ -165,7 +165,7 @@ if the peripheral does not support byte or half-word writes.
dma_ch_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
DMA_CCR(dma, channel) |= peripheral_size;
@@ -182,7 +182,7 @@ value held by the base memory address register is unchanged.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_memory_increment_mode(u32 dma, u8 channel)
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_MINC;
}
@@ -194,7 +194,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_memory_increment_mode(u32 dma, u8 channel)
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_MINC;
}
@@ -210,7 +210,7 @@ value held by the base peripheral address register is unchanged.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_PINC;
}
@@ -222,7 +222,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_peripheral_increment_mode(u32 dma, u8 channel)
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_PINC;
}
@@ -241,7 +241,7 @@ disabled here.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_circular_mode(u32 dma, u8 channel)
void dma_enable_circular_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
@@ -256,7 +256,7 @@ The data direction is set to read from a peripheral.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_set_read_from_peripheral(u32 dma, u8 channel)
void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
}
@@ -270,7 +270,7 @@ The data direction is set to read from memory.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_set_read_from_memory(u32 dma, u8 channel)
void dma_set_read_from_memory(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_DIR;
}
@@ -282,7 +282,7 @@ void dma_set_read_from_memory(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
}
@@ -294,7 +294,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
}
@@ -306,7 +306,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
}
@@ -318,7 +318,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
}
@@ -330,7 +330,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
}
@@ -342,7 +342,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
}
@@ -354,7 +354,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_channel(u32 dma, u8 channel)
void dma_enable_channel(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_EN;
}
@@ -369,7 +369,7 @@ disabled.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_channel(u32 dma, u8 channel)
void dma_disable_channel(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
}
@@ -388,10 +388,10 @@ function has no effect if the channel is enabled.
@param[in] address unsigned int32. Peripheral Address.
*/
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CPAR(dma, channel) = (u32) address;
DMA_CPAR(dma, channel) = (uint32_t) address;
}
}
@@ -406,10 +406,10 @@ function has no effect if the channel is enabled.
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CMAR(dma, channel) = (u32) address;
DMA_CMAR(dma, channel) = (uint32_t) address;
}
}
@@ -425,7 +425,7 @@ count is not changed if the channel is enabled.
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number)
{
DMA_CNDTR(dma, channel) = number;
}

114
lib/stm32/common/dma_common_f24.c
View File

@@ -57,7 +57,7 @@ The specified stream is disabled and configuration registers are cleared.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_stream_reset(u32 dma, u8 stream)
void dma_stream_reset(uint32_t dma, uint8_t stream)
{
/* Disable stream (must be done before register is otherwise changed). */
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
@@ -72,7 +72,7 @@ void dma_stream_reset(u32 dma, u8 stream)
/* This is the default setting */
DMA_SFCR(dma, stream) = 0x21;
/* Reset all stream interrupt flags using the interrupt flag clear register. */
u32 mask = DMA_ISR_MASK(stream);
uint32_t mask = DMA_ISR_MASK(stream);
if (stream < 4) {
DMA_LIFCR(dma) |= mask;
} else {
@@ -92,10 +92,10 @@ same stream may be cleared by using the bitwise OR of the interrupt flags.
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts)
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts)
{
/* Get offset to interrupt flag location in stream field */
u32 flags = (interrupts << DMA_ISR_OFFSET(stream));
uint32_t flags = (interrupts << DMA_ISR_OFFSET(stream));
/* First four streams are in low register. Flag clear must be set then
* reset.
*/
@@ -117,12 +117,12 @@ The interrupt flag for the stream is returned.
@returns bool interrupt flag is set.
*/
bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt)
bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt)
{
/* get offset to interrupt flag location in stream field. Assumes
* stream and interrupt parameters are integers.
*/
u32 flag = (interrupt << DMA_ISR_OFFSET(stream));
uint32_t flag = (interrupt << DMA_ISR_OFFSET(stream));
/* First four streams are in low register */
if (stream < 4) {
return ((DMA_LISR(dma) & flag) > 0);
@@ -145,9 +145,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] direction unsigned int32. Data transfer direction @ref dma_st_dir
*/
void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction)
void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
/* Disable circular and double buffer modes if memory to memory
* transfers are in effect. (Direct Mode is automatically disabled by
* hardware)
@@ -173,7 +173,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] prio unsigned int32. Priority level @ref dma_st_pri.
*/
void dma_set_priority(u32 dma, u8 stream, u32 prio)
void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_PL_MASK);
DMA_SCR(dma, stream) |= prio;
@@ -192,7 +192,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] mem_size unsigned int32. Memory word width @ref dma_st_memwidth.
*/
void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size)
void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK);
DMA_SCR(dma, stream) |= mem_size;
@@ -213,7 +213,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
dma_st_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_PSIZE_MASK);
DMA_SCR(dma, stream) |= peripheral_size;
@@ -232,7 +232,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_memory_increment_mode(u32 dma, u8 stream)
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_MINC;
}
@@ -246,7 +246,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_memory_increment_mode(u32 dma, u8 stream)
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC;
}
@@ -264,9 +264,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_peripheral_increment_mode(u32 dma, u8 stream)
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
u32 reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC);
uint32_t reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC);
DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS);
}
@@ -279,7 +279,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_peripheral_increment_mode(u32 dma, u8 stream)
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC;
}
@@ -297,7 +297,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream)
void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS);
}
@@ -319,7 +319,7 @@ It is enabled automatically if double buffered mode is selected.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_circular_mode(u32 dma, u8 stream)
void dma_enable_circular_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_CIRC;
}
@@ -338,7 +338,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] channel unsigned int8. Channel selection @ref dma_ch_sel
*/
void dma_channel_select(u32 dma, u8 stream, u32 channel)
void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel)
{
DMA_SCR(dma, stream) |= channel;
}
@@ -356,9 +356,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] burst unsigned int8. Memory Burst selection @ref dma_mburst
*/
void dma_set_memory_burst(u32 dma, u8 stream, u32 burst)
void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK);
DMA_SCR(dma, stream) = (reg32 | burst);
}
@@ -375,9 +375,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] burst unsigned int8. Peripheral Burst selection @ref dma_pburst
*/
void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst)
void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK);
DMA_SCR(dma, stream) = (reg32 | burst);
}
@@ -394,9 +394,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] memory unsigned int8. Initial memory pointer to use: 0 or 1
*/
void dma_set_initial_target(u32 dma, u8 stream, u8 memory)
void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
if (memory == 1) {
reg32 |= DMA_SxCR_CT;
}
@@ -417,7 +417,7 @@ the stream to be disabled and the transfer error flag to be set.
@returns unsigned int8. Memory buffer in use: 0 or 1
*/
u8 dma_get_target(u32 dma, u8 stream)
uint8_t dma_get_target(uint32_t dma, uint8_t stream)
{
if (DMA_SCR(dma, stream) & DMA_SxCR_CT) {
return 1;
@@ -441,7 +441,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_double_buffer_mode(u32 dma, u8 stream)
void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_DBM;
}
@@ -453,7 +453,7 @@ void dma_enable_double_buffer_mode(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_double_buffer_mode(u32 dma, u8 stream)
void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM;
}
@@ -470,7 +470,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_set_peripheral_flow_control(u32 dma, u8 stream)
void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL;
}
@@ -486,7 +486,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_set_dma_flow_control(u32 dma, u8 stream)
void dma_set_dma_flow_control(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL;
}
@@ -498,7 +498,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_TEIF);
DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
@@ -511,7 +511,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE;
}
@@ -523,7 +523,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_HTIF);
DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
@@ -536,7 +536,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
}
@@ -548,7 +548,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_TCIF);
DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
@@ -561,7 +561,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
}
@@ -573,7 +573,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_DMEIF);
DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
@@ -586,7 +586,7 @@ void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE;
}
@@ -598,7 +598,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_FEIF);
DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
@@ -611,7 +611,7 @@ void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_fifo_error_interrupt(u32 dma, u8 stream)
void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE;
}
@@ -624,10 +624,10 @@ meaning if direct mode is enabled (as the FIFO is not used).
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@returns u32 FIFO Status @ref dma_fifo_status
@returns uint32_t FIFO Status @ref dma_fifo_status
*/
u32 dma_fifo_status(u32 dma, u8 stream)
uint32_t dma_fifo_status(uint32_t dma, uint8_t stream)
{
return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK;
}
@@ -643,7 +643,7 @@ mode is selected.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_direct_mode(u32 dma, u8 stream)
void dma_enable_direct_mode(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS;
}
@@ -657,7 +657,7 @@ Data is transferred via a FIFO.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fifo_mode(u32 dma, u8 stream)
void dma_enable_fifo_mode(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS;
}
@@ -673,9 +673,9 @@ destination.
@param[in] threshold unsigned int8. Threshold setting @ref dma_fifo_thresh
*/
void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold)
{
u32 reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK);
uint32_t reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK);
DMA_SFCR(dma, stream) = (reg32 | threshold);
}
@@ -686,7 +686,7 @@ void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_stream(u32 dma, u8 stream)
void dma_enable_stream(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_EN;
}
@@ -700,7 +700,7 @@ void dma_enable_stream(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_stream(u32 dma, u8 stream)
void dma_disable_stream(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
}
@@ -719,10 +719,10 @@ has no effect if the stream is enabled.
@param[in] address unsigned int32. Peripheral Address.
*/
void dma_set_peripheral_address(u32 dma, u8 stream, u32 address)
void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address)
{
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) {
DMA_SPAR(dma, stream) = (u32 *) address;
DMA_SPAR(dma, stream) = (uint32_t *) address;
}
}
@@ -741,12 +741,12 @@ This is the default base memory address used in direct mode.
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address(u32 dma, u8 stream, u32 address)
void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address)
{
u32 reg32 = DMA_SCR(dma, stream);
uint32_t reg32 = DMA_SCR(dma, stream);
if (!(reg32 & DMA_SxCR_EN) ||
((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM0AR(dma, stream) = (u32 *) address;
DMA_SM0AR(dma, stream) = (uint32_t *) address;
}
}
@@ -763,12 +763,12 @@ to change this in double buffer mode when the current target is memory area 0
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address_1(u32 dma, u8 stream, u32 address)
void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address)
{
u32 reg32 = DMA_SCR(dma, stream);
uint32_t reg32 = DMA_SCR(dma, stream);
if (!(reg32 & DMA_SxCR_EN) ||
(!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM1AR(dma, stream) = (u32 *) address;
DMA_SM1AR(dma, stream) = (uint32_t *) address;
}
}
@@ -784,7 +784,7 @@ is not changed if the stream is enabled.
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 stream, u16 number)
void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number)
{
DMA_SNDTR(dma, stream) = number;
}

24
lib/stm32/common/flash_common_f24.c
View File

@@ -20,7 +20,7 @@
#include <libopencm3/stm32/flash.h>
static inline void flash_set_program_size(u32 psize)
static inline void flash_set_program_size(uint32_t psize)
{
FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
FLASH_CR |= psize;
@@ -66,9 +66,9 @@ void flash_icache_reset(void)
FLASH_ACR |= FLASH_ACR_ICRST;
}
void flash_set_ws(u32 ws)
void flash_set_ws(uint32_t ws)
{
u32 reg32;
uint32_t reg32;
reg32 = FLASH_ACR;
reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
@@ -151,7 +151,7 @@ void flash_wait_for_last_operation(void)
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
void flash_program_double_word(u32 address, u64 data)
void flash_program_double_word(uint32_t address, uint64_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
@@ -170,7 +170,7 @@ void flash_program_double_word(u32 address, u64 data)
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_word(u32 address, u32 data)
void flash_program_word(uint32_t address, uint32_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
@@ -189,7 +189,7 @@ void flash_program_word(u32 address, u32 data)
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data)
void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
flash_set_program_size(FLASH_CR_PROGRAM_X16);
@@ -203,7 +203,7 @@ void flash_program_half_word(u32 address, u16 data)
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program_byte(u32 address, u8 data)
void flash_program_byte(uint32_t address, uint8_t data)
{
flash_wait_for_last_operation();
flash_set_program_size(FLASH_CR_PROGRAM_X8);
@@ -217,18 +217,18 @@ void flash_program_byte(u32 address, u8 data)
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program(u32 address, u8 *data, u32 len)
void flash_program(uint32_t address, uint8_t *data, uint32_t len)
{
/* TODO: Use dword and word size program operations where possible for
* turbo speed.
*/
u32 i;
uint32_t i;
for (i = 0; i < len; i++) {
flash_program_byte(address+i, data[i]);
}
}
void flash_erase_sector(u8 sector, u32 program_size)
void flash_erase_sector(uint8_t sector, uint32_t program_size)
{
flash_wait_for_last_operation();
flash_set_program_size(program_size);
@@ -243,7 +243,7 @@ void flash_erase_sector(u8 sector, u32 program_size)
FLASH_CR &= ~(0xF << 3);
}
void flash_erase_all_sectors(u32 program_size)
void flash_erase_all_sectors(uint32_t program_size)
{
flash_wait_for_last_operation();
flash_set_program_size(program_size);
@@ -255,7 +255,7 @@ void flash_erase_all_sectors(u32 program_size)
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_program_option_bytes(u32 data)
void flash_program_option_bytes(uint32_t data)
{
flash_wait_for_last_operation();

18
lib/stm32/common/gpio_common_all.c
View File

@@ -39,7 +39,7 @@ Set one or more pins of the given GPIO port to 1 in an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_set(u32 gpioport, u16 gpios)
void gpio_set(uint32_t gpioport, uint16_t gpios)
{
GPIO_BSRR(gpioport) = gpios;
}
@@ -54,7 +54,7 @@ Clear one or more pins of the given GPIO port to 0 in an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_clear(u32 gpioport, u16 gpios)
void gpio_clear(uint32_t gpioport, uint16_t gpios)
{
GPIO_BSRR(gpioport) = (gpios << 16);
}
@@ -69,7 +69,7 @@ void gpio_clear(u32 gpioport, u16 gpios)
@return Unsigned int16 value of the pin values. The bit position of the pin
value returned corresponds to the pin number.
*/
u16 gpio_get(u32 gpioport, u16 gpios)
uint16_t gpio_get(uint32_t gpioport, uint16_t gpios)
{
return gpio_port_read(gpioport) & gpios;
}
@@ -84,7 +84,7 @@ Toggle one or more pins of the given GPIO port. This is not an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_toggle(u32 gpioport, u16 gpios)
void gpio_toggle(uint32_t gpioport, uint16_t gpios)
{
GPIO_ODR(gpioport) ^= gpios;
}
@@ -98,9 +98,9 @@ valid pin data.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@return Unsigned int16. The value held in the specified GPIO port.
*/
u16 gpio_port_read(u32 gpioport)
uint16_t gpio_port_read(uint32_t gpioport)
{
return (u16)GPIO_IDR(gpioport);
return (uint16_t)GPIO_IDR(gpioport);
}
/*---------------------------------------------------------------------------*/
@@ -111,7 +111,7 @@ Write a value to the given GPIO port.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] data Unsigned int16. The value to be written to the GPIO port.
*/
void gpio_port_write(u32 gpioport, u16 data)
void gpio_port_write(uint32_t gpioport, uint16_t data)
{
GPIO_ODR(gpioport) = data;
}
@@ -128,9 +128,9 @@ reset.
If multiple pins are to be locked, use logical OR '|' to separate
them.
*/
void gpio_port_config_lock(u32 gpioport, u16 gpios)
void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios)
{
u32 reg32;
uint32_t reg32;
/* Special "Lock Key Writing Sequence", see datasheet. */
GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */

18
lib/stm32/common/gpio_common_f24.c
View File

@@ -86,10 +86,10 @@ gpio_pup
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios)
{
u16 i;
u32 moder, pupd;
uint16_t i;
uint32_t moder, pupd;
/*
* We want to set the config only for the pins mentioned in gpios,
@@ -128,10 +128,10 @@ port.
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios)
{
u16 i;
u32 ospeedr;
uint16_t i;
uint32_t ospeedr;
if (otype == 0x1) {
GPIO_OTYPER(gpioport) |= gpios;
@@ -173,10 +173,10 @@ gpio_af_num
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios)
{
u16 i;
u32 afrl, afrh;
uint16_t i;
uint32_t afrl, afrh;
afrl = GPIO_AFRL(gpioport);
afrh = GPIO_AFRH(gpioport);

14
lib/stm32/common/hash_common_f24.c
View File

@@ -40,7 +40,7 @@ Sets up the specified mode - either HASH or HMAC.
@param[in] mode unsigned int8. Hash processor mode: @ref hash_mode
*/
void hash_set_mode(u8 mode)
void hash_set_mode(uint8_t mode)
{
HASH_CR &= ~HASH_CR_MODE;
HASH_CR |= mode;
@@ -54,7 +54,7 @@ Sets up the specified algorithm - either MD5 or SHA1.
@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm
*/
void hash_set_algorithm(u8 algorithm)
void hash_set_algorithm(uint8_t algorithm)
{
HASH_CR &= ~HASH_CR_ALGO;
HASH_CR |= algorithm;
@@ -68,7 +68,7 @@ Sets up the specified data type: 32Bit, 16Bit, 8Bit, Bitstring.
@param[in] datatype unsigned int8. Hash data type: @ref hash_data_type
*/
void hash_set_data_type(u8 datatype)
void hash_set_data_type(uint8_t datatype)
{
HASH_CR &= ~HASH_CR_DATATYPE;
HASH_CR |= datatype;
@@ -82,7 +82,7 @@ Sets up the specified key length: Long, Short.
@param[in] keylength unsigned int8. Hash data type: @ref hash_key_length
*/
void hash_set_key_length(u8 keylength)
void hash_set_key_length(uint8_t keylength)
{
HASH_CR &= ~HASH_CR_LKEY;
HASH_CR |= keylength;
@@ -96,7 +96,7 @@ Specifies the number of valid bits in the last word.
@param[in] validbits unsigned int8. Number of valid bits.
*/
void hash_set_last_word_valid_bits(u8 validbits)
void hash_set_last_word_valid_bits(uint8_t validbits)
{
HASH_STR &= ~(HASH_STR_NBW);
HASH_STR |= 32 - validbits;
@@ -122,7 +122,7 @@ Puts data into the HASH processor's queue.
@param[in] data unsigned int32. Hash input data.
*/
void hash_add_data(u32 data)
void hash_add_data(uint32_t data)
{
HASH_DIN = data;
}
@@ -148,7 +148,7 @@ Makes a copy of the resulting hash.
@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm
*/
void hash_get_result(u32 *data)
void hash_get_result(uint32_t *data)
{
data[0] = HASH_HR[0];
data[1] = HASH_HR[1];

64
lib/stm32/common/i2c_common_all.c
View File

@@ -49,7 +49,7 @@ the reset condition. The reset is effected via the RCC peripheral reset system.
@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
*/
void i2c_reset(u32 i2c)
void i2c_reset(uint32_t i2c)
{
switch (i2c) {
case I2C1:
@@ -69,7 +69,7 @@ void i2c_reset(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_peripheral_enable(u32 i2c)
void i2c_peripheral_enable(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_PE;
}
@@ -83,7 +83,7 @@ In Slave mode, the peripheral is disabled only after communication has ended.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_peripheral_disable(u32 i2c)
void i2c_peripheral_disable(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_PE;
}
@@ -98,7 +98,7 @@ when the current bus activity is completed.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_send_start(u32 i2c)
void i2c_send_start(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_START;
}
@@ -112,7 +112,7 @@ mode, or simply release the bus if in Slave mode.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_send_stop(u32 i2c)
void i2c_send_stop(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_STOP;
}
@@ -124,7 +124,7 @@ Clear the "Send Stop" flag in the I2C config register
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_clear_stop(u32 i2c)
void i2c_clear_stop(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_STOP;
}
@@ -138,9 +138,9 @@ This sets an address for Slave mode operation, in 7 bit form.
@param[in] slave Unsigned int8. Slave address 0...127.
*/
void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave)
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
{
I2C_OAR1(i2c) = (u16)(slave << 1);
I2C_OAR1(i2c) = (uint16_t)(slave << 1);
I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE;
I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
}
@@ -156,9 +156,9 @@ This sets an address for Slave mode operation, in 10 bit form.
@param[in] slave Unsigned int16. Slave address 0...1023.
*/
void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave)
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
{
I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave);
I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_ADDMODE | slave);
}
/*---------------------------------------------------------------------------*/
@@ -170,7 +170,7 @@ clock frequency must be set with @ref i2c_set_clock_frequency
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_fast_mode(u32 i2c)
void i2c_set_fast_mode(uint32_t i2c)
{
I2C_CCR(i2c) |= I2C_CCR_FS;
}
@@ -184,7 +184,7 @@ actual clock frequency must be set with @ref i2c_set_clock_frequency
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_standard_mode(u32 i2c)
void i2c_set_standard_mode(uint32_t i2c)
{
I2C_CCR(i2c) &= ~I2C_CCR_FS;
}
@@ -201,9 +201,9 @@ i2c_set_ccr
@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock.
*/
void i2c_set_clock_frequency(u32 i2c, u8 freq)
void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq)
{
u16 reg16;
uint16_t reg16;
reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */
reg16 |= freq;
I2C_CR2(i2c) = reg16;
@@ -224,9 +224,9 @@ of the CCR field. It is a divisor of the peripheral clock frequency
@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095.
*/
void i2c_set_ccr(u32 i2c, u16 freq)
void i2c_set_ccr(uint32_t i2c, uint16_t freq)
{
u16 reg16;
uint16_t reg16;
reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */
reg16 |= freq;
I2C_CCR(i2c) = reg16;
@@ -245,7 +245,7 @@ number.
@param[in] trise Unsigned int16. Rise Time Setting 0...63.
*/
void i2c_set_trise(u32 i2c, u16 trise)
void i2c_set_trise(uint32_t i2c, uint16_t trise)
{
I2C_TRISE(i2c) = trise;
}
@@ -259,9 +259,9 @@ void i2c_set_trise(u32 i2c, u16 trise)
send @ref i2c_rw.
*/
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite)
{
I2C_DR(i2c) = (u8)((slave << 1) | readwrite);
I2C_DR(i2c) = (uint8_t)((slave << 1) | readwrite);
}
/*---------------------------------------------------------------------------*/
@@ -271,7 +271,7 @@ void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
@param[in] data Unsigned int8. Byte to send.
*/
void i2c_send_data(u32 i2c, u8 data)
void i2c_send_data(uint32_t i2c, uint8_t data)
{
I2C_DR(i2c) = data;
}
@@ -281,7 +281,7 @@ void i2c_send_data(u32 i2c, u8 data)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
uint8_t i2c_get_data(u32 i2c)
uint8_t i2c_get_data(uint32_t i2c)
{
return I2C_DR(i2c) & 0xff;
}
@@ -292,7 +292,7 @@ uint8_t i2c_get_data(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] interrupt Unsigned int32. Interrupt to enable.
*/
void i2c_enable_interrupt(u32 i2c, u32 interrupt)
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
{
I2C_CR2(i2c) |= interrupt;
}
@@ -303,7 +303,7 @@ void i2c_enable_interrupt(u32 i2c, u32 interrupt)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] interrupt Unsigned int32. Interrupt to disable.
*/
void i2c_disable_interrupt(u32 i2c, u32 interrupt)
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
{
I2C_CR2(i2c) &= ~interrupt;
}
@@ -314,7 +314,7 @@ void i2c_disable_interrupt(u32 i2c, u32 interrupt)
Enables acking of own 7/10 bit address
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_enable_ack(u32 i2c)
void i2c_enable_ack(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_ACK;
}
@@ -325,7 +325,7 @@ void i2c_enable_ack(u32 i2c)
Disables acking of own 7/10 bit address
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_disable_ack(u32 i2c)
void i2c_disable_ack(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_ACK;
}
@@ -336,7 +336,7 @@ void i2c_disable_ack(u32 i2c)
Causes the I2C controller to NACK the reception of the next byte
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_nack_next(u32 i2c)
void i2c_nack_next(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_POS;
}
@@ -348,7 +348,7 @@ Causes the I2C controller to NACK the reception of the current byte
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_nack_current(u32 i2c)
void i2c_nack_current(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_POS;
}
@@ -359,7 +359,7 @@ void i2c_nack_current(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle.
*/
void i2c_set_dutycycle(u32 i2c, u32 dutycycle)
void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle)
{
if (dutycycle == I2C_CCR_DUTY_DIV2) {
I2C_CCR(i2c) &= ~I2C_CCR_DUTY;
@@ -373,7 +373,7 @@ void i2c_set_dutycycle(u32 i2c, u32 dutycycle)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_enable_dma(u32 i2c)
void i2c_enable_dma(uint32_t i2c)
{
I2C_CR2(i2c) |= I2C_CR2_DMAEN;
}
@@ -383,7 +383,7 @@ void i2c_enable_dma(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_disable_dma(u32 i2c)
void i2c_disable_dma(uint32_t i2c)
{
I2C_CR2(i2c) &= ~I2C_CR2_DMAEN;
}
@@ -393,7 +393,7 @@ void i2c_disable_dma(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_dma_last_transfer(u32 i2c)
void i2c_set_dma_last_transfer(uint32_t i2c)
{
I2C_CR2(i2c) |= I2C_CR2_LAST;
}
@@ -403,7 +403,7 @@ void i2c_set_dma_last_transfer(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_clear_dma_last_transfer(u32 i2c)
void i2c_clear_dma_last_transfer(uint32_t i2c)
{
I2C_CR2(i2c) &= ~I2C_CR2_LAST;
}

6
lib/stm32/common/iwdg_common_all.c
View File

@@ -66,13 +66,13 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
can occasionally occur if the prescale or preload registers are currently busy
loading a previous value.
@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset
@param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog reset
until a system reset is issued.
*/
void iwdg_set_period_ms(u32 period)
void iwdg_set_period_ms(uint32_t period)
{
u32 count, prescale, reload, exponent;
uint32_t count, prescale, reload, exponent;
/* Set the count to represent ticks of the 32kHz LSI clock */
count = (period << 5);

4
lib/stm32/common/pwr_common_all.c
View File

@@ -57,10 +57,10 @@ This provides voltage level threshold detection. The result of detection is
provided in the power voltage detector output flag (see @ref pwr_voltage_high)
or by setting the EXTI16 interrupt (see datasheet for configuration details).
@param[in] pvd_level u32. Taken from @ref pwr_pls.
@param[in] pvd_level uint32_t. Taken from @ref pwr_pls.
*/
void pwr_enable_power_voltage_detect(u32 pvd_level)
void pwr_enable_power_voltage_detect(uint32_t pvd_level)
{
PWR_CR &= ~PWR_CR_PLS_MASK;
PWR_CR |= (PWR_CR_PVDE | pvd_level);

4
lib/stm32/common/rtc_common_bcd.c
View File

@@ -33,7 +33,7 @@
This sets the RTC synchronous and asynchronous prescalars.
*/
void rtc_set_prescaler(u32 sync, u32 async)
void rtc_set_prescaler(uint32_t sync, uint32_t async)
{
/*
* Even if only one of the two fields needs to be changed,
@@ -86,7 +86,7 @@ void rtc_lock(void)
/** @brief Sets the wakeup time auto-reload value
*/
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel)
void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel)
{
/* FTFM:
* The following sequence is required to configure or change the wakeup

100
lib/stm32/common/spi_common_all.c
View File

@@ -79,7 +79,7 @@ the reset condition. The reset is effected via the RCC peripheral reset system.
spi_reg_base.
*/
void spi_reset(u32 spi_peripheral)
void spi_reset(uint32_t spi_peripheral)
{
switch (spi_peripheral) {
case SPI1:
@@ -119,9 +119,9 @@ spi_lsbfirst.
@returns int. Error code.
*/
int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst)
{
u32 reg32 = SPI_CR1(spi);
uint32_t reg32 = SPI_CR1(spi);
/* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */
reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT;
@@ -152,7 +152,7 @@ The SPI peripheral is enabled.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable(u32 spi)
void spi_enable(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */
}
@@ -166,9 +166,9 @@ The SPI peripheral is disabled.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable(u32 spi)
void spi_disable(uint32_t spi)
{
u32 reg32;
uint32_t reg32;
reg32 = SPI_CR1(spi);
reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */
@@ -186,12 +186,12 @@ prevents the BSY flag from becoming unreliable.
@returns data Unsigned int16. 8 or 16 bit data from final read.
*/
u16 spi_clean_disable(u32 spi)
uint16_t spi_clean_disable(uint32_t spi)
{
/* Wait to receive last data */
while (!(SPI_SR(spi) & SPI_SR_RXNE));
u16 data = SPI_DR(spi);
uint16_t data = SPI_DR(spi);
/* Wait to transmit last data */
while (!(SPI_SR(spi) & SPI_SR_TXE));
@@ -213,7 +213,7 @@ Data is written to the SPI interface.
@param[in] data Unsigned int16. 8 or 16 bit data to be written.
*/
void spi_write(u32 spi, u16 data)
void spi_write(uint32_t spi, uint16_t data)
{
/* Write data (8 or 16 bits, depending on DFF) into DR. */
SPI_DR(spi) = data;
@@ -229,7 +229,7 @@ finished.
@param[in] data Unsigned int16. 8 or 16 bit data to be written.
*/
void spi_send(u32 spi, u16 data)
void spi_send(uint32_t spi, uint16_t data)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_TXE));
@@ -247,7 +247,7 @@ Data is read from the SPI interface after the incoming transfer has finished.
@returns data Unsigned int16. 8 or 16 bit data.
*/
u16 spi_read(u32 spi)
uint16_t spi_read(uint32_t spi)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_RXNE));
@@ -267,7 +267,7 @@ transfer has finished.
@returns data Unsigned int16. 8 or 16 bit data.
*/
u16 spi_xfer(u32 spi, u16 data)
uint16_t spi_xfer(uint32_t spi, uint16_t data)
{
spi_write(spi, data);
@@ -287,7 +287,7 @@ The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_mode(u32 spi)
void spi_set_bidirectional_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
}
@@ -302,7 +302,7 @@ clock wire and a unidirectional data wire.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_unidirectional_mode(u32 spi)
void spi_set_unidirectional_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
}
@@ -317,7 +317,7 @@ state.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_receive_only_mode(u32 spi)
void spi_set_bidirectional_receive_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
@@ -333,7 +333,7 @@ state.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_transmit_only_mode(u32 spi)
void spi_set_bidirectional_transmit_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
SPI_CR1(spi) |= SPI_CR1_BIDIOE;
@@ -347,7 +347,7 @@ The SPI peripheral is set to use a CRC field for transmit and receive.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_crc(u32 spi)
void spi_enable_crc(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CRCEN;
}
@@ -358,7 +358,7 @@ void spi_enable_crc(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_crc(u32 spi)
void spi_disable_crc(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
}
@@ -373,7 +373,7 @@ of a data or CRC word.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_next_tx_from_buffer(u32 spi)
void spi_set_next_tx_from_buffer(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
}
@@ -388,7 +388,7 @@ of a data or CRC word.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_next_tx_from_crc(u32 spi)
void spi_set_next_tx_from_crc(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
}
@@ -399,7 +399,7 @@ void spi_set_next_tx_from_crc(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_dff_8bit(u32 spi)
void spi_set_dff_8bit(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_DFF;
}
@@ -410,7 +410,7 @@ void spi_set_dff_8bit(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_dff_16bit(u32 spi)
void spi_set_dff_16bit(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_DFF;
}
@@ -421,7 +421,7 @@ void spi_set_dff_16bit(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_full_duplex_mode(u32 spi)
void spi_set_full_duplex_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
}
@@ -433,7 +433,7 @@ Transfers
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_receive_only_mode(u32 spi)
void spi_set_receive_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_RXONLY;
}
@@ -446,7 +446,7 @@ In slave mode the NSS hardware input is used as a select enable for the slave.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_software_slave_management(u32 spi)
void spi_disable_software_slave_management(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_SSM;
}
@@ -460,7 +460,7 @@ enable/disable of the slave (@ref spi_set_nss_high).
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_software_slave_management(u32 spi)
void spi_enable_software_slave_management(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SSM;
}
@@ -477,7 +477,7 @@ otherwise
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_nss_high(u32 spi)
void spi_set_nss_high(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SSI;
}
@@ -491,7 +491,7 @@ the NSS signal with a slave select disable signal.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_nss_low(u32 spi)
void spi_set_nss_low(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_SSI;
}
@@ -502,7 +502,7 @@ void spi_set_nss_low(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_send_lsb_first(u32 spi)
void spi_send_lsb_first(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_LSBFIRST;
}
@@ -513,7 +513,7 @@ void spi_send_lsb_first(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_send_msb_first(u32 spi)
void spi_send_msb_first(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
}
@@ -528,9 +528,9 @@ values?
@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
*/
void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate)
{
u32 reg32;
uint32_t reg32;
if (baudrate > 7) {
return;
@@ -547,7 +547,7 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_master_mode(u32 spi)
void spi_set_master_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_MSTR;
}
@@ -558,7 +558,7 @@ void spi_set_master_mode(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_slave_mode(u32 spi)
void spi_set_slave_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_MSTR;
}
@@ -569,7 +569,7 @@ void spi_set_slave_mode(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_polarity_1(u32 spi)
void spi_set_clock_polarity_1(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CPOL;
}
@@ -580,7 +580,7 @@ void spi_set_clock_polarity_1(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_polarity_0(u32 spi)
void spi_set_clock_polarity_0(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CPOL;
}
@@ -591,7 +591,7 @@ void spi_set_clock_polarity_0(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_phase_1(u32 spi)
void spi_set_clock_phase_1(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CPHA;
}
@@ -602,7 +602,7 @@ void spi_set_clock_phase_1(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_phase_0(u32 spi)
void spi_set_clock_phase_0(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CPHA;
}
@@ -613,7 +613,7 @@ void spi_set_clock_phase_0(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_tx_buffer_empty_interrupt(u32 spi)
void spi_enable_tx_buffer_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_TXEIE;
}
@@ -624,7 +624,7 @@ void spi_enable_tx_buffer_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_tx_buffer_empty_interrupt(u32 spi)
void spi_disable_tx_buffer_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
}
@@ -635,7 +635,7 @@ void spi_disable_tx_buffer_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_RXNEIE;
}
@@ -646,7 +646,7 @@ void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
}
@@ -657,7 +657,7 @@ void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_error_interrupt(u32 spi)
void spi_enable_error_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_ERRIE;
}
@@ -668,7 +668,7 @@ void spi_enable_error_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_error_interrupt(u32 spi)
void spi_disable_error_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
}
@@ -682,7 +682,7 @@ SPI bus into slave mode. Multimaster mode is not possible.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_ss_output(u32 spi)
void spi_enable_ss_output(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_SSOE;
}
@@ -697,7 +697,7 @@ becomes a slave enable.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_ss_output(u32 spi)
void spi_disable_ss_output(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_SSOE;
}
@@ -712,7 +712,7 @@ SPI peripheral are given in the Technical Manual DMA section.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_tx_dma(u32 spi)
void spi_enable_tx_dma(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
}
@@ -723,7 +723,7 @@ void spi_enable_tx_dma(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_tx_dma(u32 spi)
void spi_disable_tx_dma(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
}
@@ -738,7 +738,7 @@ for each SPI peripheral are given in the Technical Manual DMA section.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_rx_dma(u32 spi)
void spi_enable_rx_dma(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
}
@@ -749,7 +749,7 @@ void spi_enable_rx_dma(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_rx_dma(u32 spi)
void spi_disable_rx_dma(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN;
}

156
lib/stm32/common/timer_common_all.c
View File

@@ -113,7 +113,7 @@ reset condition. The reset is effected via the RCC peripheral reset system.
tim_reg_base (TIM9 .. TIM14 not yet supported here).
*/
void timer_reset(u32 timer_peripheral)
void timer_reset(uint32_t timer_peripheral)
{
switch (timer_peripheral) {
#if defined(TIM1_BASE)
@@ -198,7 +198,7 @@ tim_reg_base
enable bits to be set
*/
void timer_enable_irq(u32 timer_peripheral, u32 irq)
void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq)
{
TIM_DIER(timer_peripheral) |= irq;
}
@@ -212,7 +212,7 @@ tim_reg_base
enable bits to be cleared
*/
void timer_disable_irq(u32 timer_peripheral, u32 irq)
void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq)
{
TIM_DIER(timer_peripheral) &= ~irq;
}
@@ -233,7 +233,7 @@ tim_reg_base
@returns boolean: flag set.
*/
bool timer_interrupt_source(u32 timer_peripheral, u32 flag)
bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag)
{
/* flag not set or interrupt disabled or not an interrupt source */
if (((TIM_SR(timer_peripheral) &
@@ -259,7 +259,7 @@ tim_reg_base
@returns boolean: flag set.
*/
bool timer_get_flag(u32 timer_peripheral, u32 flag)
bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag)
{
if ((TIM_SR(timer_peripheral) & flag) != 0) {
return true;
@@ -276,7 +276,7 @@ tim_reg_base
@param[in] flag Unsigned int32. @ref tim_sr_values. Status register flag.
*/
void timer_clear_flag(u32 timer_peripheral, u32 flag)
void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag)
{
TIM_SR(timer_peripheral) &= ~flag;
}
@@ -309,10 +309,10 @@ tim_x_cr1_cdr
tim_x_cr1_dir
*/
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
u32 alignment, u32 direction)
void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div,
uint32_t alignment, uint32_t direction)
{
u32 cr1;
uint32_t cr1;
cr1 = TIM_CR1(timer_peripheral);
@@ -335,7 +335,7 @@ tim_reg_base
tim_x_cr1_cdr
*/
void timer_set_clock_division(u32 timer_peripheral, u32 clock_div)
void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div)
{
clock_div &= TIM_CR1_CKD_CK_INT_MASK;
TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK;
@@ -352,7 +352,7 @@ auto-reload register only at the next update event.
tim_reg_base
*/
void timer_enable_preload(u32 timer_peripheral)
void timer_enable_preload(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE;
}
@@ -368,7 +368,7 @@ current count cycle rather than for the cycle following an update event.
tim_reg_base
*/
void timer_disable_preload(u32 timer_peripheral)
void timer_disable_preload(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE;
}
@@ -383,7 +383,7 @@ tim_reg_base
@param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms
*/
void timer_set_alignment(u32 timer_peripheral, u32 alignment)
void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment)
{
alignment &= TIM_CR1_CMS_MASK;
TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK;
@@ -399,7 +399,7 @@ This has no effect if the timer is set to center aligned.
tim_reg_base
*/
void timer_direction_up(u32 timer_peripheral)
void timer_direction_up(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN;
}
@@ -413,7 +413,7 @@ This has no effect if the timer is set to center aligned.
tim_reg_base
*/
void timer_direction_down(u32 timer_peripheral)
void timer_direction_down(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN;
}
@@ -425,7 +425,7 @@ void timer_direction_down(u32 timer_peripheral)
tim_reg_base
*/
void timer_one_shot_mode(u32 timer_peripheral)
void timer_one_shot_mode(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_OPM;
}
@@ -437,7 +437,7 @@ void timer_one_shot_mode(u32 timer_peripheral)
tim_reg_base
*/
void timer_continuous_mode(u32 timer_peripheral)
void timer_continuous_mode(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM;
}
@@ -454,7 +454,7 @@ The events which will generate an interrupt or DMA request can be
tim_reg_base
*/
void timer_update_on_any(u32 timer_peripheral)
void timer_update_on_any(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS;
}
@@ -467,7 +467,7 @@ Events.
tim_reg_base
*/
void timer_update_on_overflow(u32 timer_peripheral)
void timer_update_on_overflow(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_URS;
}
@@ -479,7 +479,7 @@ void timer_update_on_overflow(u32 timer_peripheral)
tim_reg_base
*/
void timer_enable_update_event(u32 timer_peripheral)
void timer_enable_update_event(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS;
}
@@ -493,7 +493,7 @@ Update events are not generated and the shadow registers keep their values.
tim_reg_base
*/
void timer_disable_update_event(u32 timer_peripheral)
void timer_disable_update_event(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS;
}
@@ -507,7 +507,7 @@ This should be called after the timer initial configuration has been completed.
tim_reg_base
*/
void timer_enable_counter(u32 timer_peripheral)
void timer_enable_counter(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_CEN;
}
@@ -519,7 +519,7 @@ void timer_enable_counter(u32 timer_peripheral)
tim_reg_base
*/
void timer_disable_counter(u32 timer_peripheral)
void timer_disable_counter(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN;
}
@@ -540,7 +540,7 @@ tim_x_cr2_ois. If several settings are to be made, use the logical OR of the
output control values.
*/
void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs)
void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -567,7 +567,7 @@ tim_reg_base
tim_x_cr2_ois
*/
void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs)
void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -589,7 +589,7 @@ input channels 1, 2, 3.
tim_reg_base
*/
void timer_set_ti1_ch123_xor(u32 timer_peripheral)
void timer_set_ti1_ch123_xor(uint32_t timer_peripheral)
{
TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S;
}
@@ -603,7 +603,7 @@ The first timer capture input is taken from the timer input channel 1 only.
tim_reg_base
*/
void timer_set_ti1_ch1(u32 timer_peripheral)
void timer_set_ti1_ch1(uint32_t timer_peripheral)
{
TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S;
}
@@ -619,7 +619,7 @@ tim_reg_base
@param[in] mode Unsigned int32. Master Mode @ref tim_mastermode
*/
void timer_set_master_mode(u32 timer_peripheral, u32 mode)
void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode)
{
TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK;
TIM_CR2(timer_peripheral) |= mode;
@@ -634,7 +634,7 @@ Capture/compare events will cause DMA requests to be generated.
tim_reg_base
*/
void timer_set_dma_on_compare_event(u32 timer_peripheral)
void timer_set_dma_on_compare_event(uint32_t timer_peripheral)
{
TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS;
}
@@ -648,7 +648,7 @@ Update events will cause DMA requests to be generated.
tim_reg_base
*/
void timer_set_dma_on_update_event(u32 timer_peripheral)
void timer_set_dma_on_update_event(uint32_t timer_peripheral)
{
TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS;
}
@@ -667,7 +667,7 @@ complementary outputs.
tim_reg_base
*/
void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral)
void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -692,7 +692,7 @@ complementary outputs.
tim_reg_base
*/
void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral)
void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -716,7 +716,7 @@ complementary outputs.
tim_reg_base
*/
void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral)
void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -739,7 +739,7 @@ complementary outputs.
tim_reg_base
*/
void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral)
void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -760,7 +760,7 @@ tim_reg_base
@param[in] value Unsigned int32. Prescaler values 0...0xFFFF.
*/
void timer_set_prescaler(u32 timer_peripheral, u32 value)
void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value)
{
TIM_PSC(timer_peripheral) = value;
}
@@ -778,7 +778,7 @@ tim_reg_base
@param[in] value Unsigned int32. Repetition values 0...0xFF.
*/
void timer_set_repetition_counter(u32 timer_peripheral, u32 value)
void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -800,7 +800,7 @@ tim_reg_base
@param[in] period Unsigned int32. Period in counter clock ticks.
*/
void timer_set_period(u32 timer_peripheral, u32 period)
void timer_set_period(uint32_t timer_peripheral, uint32_t period)
{
TIM_ARR(timer_peripheral) = period;
}
@@ -819,7 +819,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -853,7 +853,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -892,7 +892,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -927,7 +927,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -977,7 +977,7 @@ tim_reg_base
TIM_OCM_PWM1, TIM_OCM_PWM2
*/
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
enum tim_oc_mode oc_mode)
{
switch (oc_id) {
@@ -1126,7 +1126,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1158,7 +1158,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action)
*/
void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1193,7 +1193,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1255,7 +1255,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1317,7 +1317,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1379,7 +1379,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1444,7 +1444,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
/* Acting for TIM1 and TIM8 only. */
@@ -1496,7 +1496,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
/* Acting for TIM1 and TIM8 only. */
@@ -1546,7 +1546,7 @@ to the compare register.
@param[in] value Unsigned int32. Compare value.
*/
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value)
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value)
{
switch (oc_id) {
case TIM_OC1:
@@ -1585,7 +1585,7 @@ timer <b>even if break or deadtime features are not being used</b>.
TIM8
*/
void timer_enable_break_main_output(u32 timer_peripheral)
void timer_enable_break_main_output(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1608,7 +1608,7 @@ the Master Output Enable in the Break and Deadtime Register.
TIM8
*/
void timer_disable_break_main_output(u32 timer_peripheral)
void timer_disable_break_main_output(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1632,7 +1632,7 @@ break event.
TIM8
*/
void timer_enable_break_automatic_output(u32 timer_peripheral)
void timer_enable_break_automatic_output(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1656,7 +1656,7 @@ break event.
TIM8
*/
void timer_disable_break_automatic_output(u32 timer_peripheral)
void timer_disable_break_automatic_output(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1678,7 +1678,7 @@ Sets the break function to activate when the break input becomes high.
TIM8
*/
void timer_set_break_polarity_high(u32 timer_peripheral)
void timer_set_break_polarity_high(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1700,7 +1700,7 @@ Sets the break function to activate when the break input becomes low.
TIM8
*/
void timer_set_break_polarity_low(u32 timer_peripheral)
void timer_set_break_polarity_low(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1722,7 +1722,7 @@ Enables the break function of an advanced timer.
TIM8
*/
void timer_enable_break(u32 timer_peripheral)
void timer_enable_break(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1744,7 +1744,7 @@ Disables the break function of an advanced timer.
TIM8
*/
void timer_disable_break(u32 timer_peripheral)
void timer_disable_break(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1770,7 +1770,7 @@ inactive level as defined by the output polarity.
TIM8
*/
void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral)
void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1795,7 +1795,7 @@ disabled, the output is also disabled.
TIM8
*/
void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral)
void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1819,7 +1819,7 @@ inactive level as defined by the output polarity.
TIM8
*/
void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral)
void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1842,7 +1842,7 @@ timer. When the master output is disabled the output is also disabled.
TIM8
*/
void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral)
void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1867,7 +1867,7 @@ TIM8
@param[in] lock Unsigned int32. Lock specification @ref tim_lock
*/
void timer_set_break_lock(u32 timer_peripheral, u32 lock)
void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1899,7 +1899,7 @@ TIM8
above.
*/
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime)
void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1924,7 +1924,7 @@ generated.
@param[in] event Unsigned int32. Event specification @ref tim_event_gen
*/
void timer_generate_event(u32 timer_peripheral, u32 event)
void timer_generate_event(uint32_t timer_peripheral, uint32_t event)
{
TIM_EGR(timer_peripheral) |= event;
}
@@ -1938,7 +1938,7 @@ Read back the value of a timer's counter register contents
@returns Unsigned int32. Counter value.
*/
u32 timer_get_counter(u32 timer_peripheral)
uint32_t timer_get_counter(uint32_t timer_peripheral)
{
return TIM_CNT(timer_peripheral);
}
@@ -1952,7 +1952,7 @@ Set the value of a timer's counter register contents.
@param[in] count Unsigned int32. Counter value.
*/
void timer_set_counter(u32 timer_peripheral, u32 count)
void timer_set_counter(uint32_t timer_peripheral, uint32_t count)
{
TIM_CNT(timer_peripheral) = count;
}
@@ -1971,7 +1971,7 @@ valid.
@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
*/
void timer_ic_set_filter(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_filter(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_filter flt)
{
switch (ic) {
@@ -2004,7 +2004,7 @@ Set the number of events between each capture.
@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
*/
void timer_ic_set_prescaler(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_prescaler(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_psc psc)
{
switch (ic) {
@@ -2048,7 +2048,7 @@ internal trigger input selected through TS bit
@param[in] in ::tim_ic_input. Input Capture channel direction and source input.
*/
void timer_ic_set_input(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_input(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_input in)
{
in &= 3;
@@ -2086,7 +2086,7 @@ void timer_ic_set_input(u32 timer_peripheral, enum tim_ic_id ic,
@param[in] ic ::tim_ic_id. Input Capture channel designator.
*/
void timer_ic_enable(u32 timer_peripheral, enum tim_ic_id ic)
void timer_ic_enable(uint32_t timer_peripheral, enum tim_ic_id ic)
{
TIM_CCER(timer_peripheral) |= (0x1 << (ic * 4));
}
@@ -2098,7 +2098,7 @@ void timer_ic_enable(u32 timer_peripheral, enum tim_ic_id ic)
@param[in] ic ::tim_ic_id. Input Capture channel designator.
*/
void timer_ic_disable(u32 timer_peripheral, enum tim_ic_id ic)
void timer_ic_disable(uint32_t timer_peripheral, enum tim_ic_id ic)
{
TIM_CCER(timer_peripheral) &= ~(0x1 << (ic * 4));
}
@@ -2116,7 +2116,7 @@ valid.
@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
*/
void timer_slave_set_filter(u32 timer_peripheral, enum tim_ic_filter flt)
void timer_slave_set_filter(uint32_t timer_peripheral, enum tim_ic_filter flt)
{
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETF_MASK;
TIM_SMCR(timer_peripheral) |= flt << 8;
@@ -2131,7 +2131,7 @@ Set the external trigger frequency division ratio.
@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
*/
void timer_slave_set_prescaler(u32 timer_peripheral, enum tim_ic_psc psc)
void timer_slave_set_prescaler(uint32_t timer_peripheral, enum tim_ic_psc psc)
{
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETPS_MASK;
TIM_SMCR(timer_peripheral) |= psc << 12;
@@ -2144,7 +2144,7 @@ void timer_slave_set_prescaler(u32 timer_peripheral, enum tim_ic_psc psc)
@param[in] pol ::tim_et_pol. Slave External Trigger polarity.
*/
void timer_slave_set_polarity(u32 timer_peripheral, enum tim_et_pol pol)
void timer_slave_set_polarity(uint32_t timer_peripheral, enum tim_et_pol pol)
{
if (pol) {
TIM_SMCR(timer_peripheral) |= TIM_SMCR_ETP;
@@ -2160,7 +2160,7 @@ void timer_slave_set_polarity(u32 timer_peripheral, enum tim_et_pol pol)
@param[in] mode Unsigned int8. Slave mode @ref tim_sms
*/
void timer_slave_set_mode(u32 timer_peripheral, u8 mode)
void timer_slave_set_mode(uint32_t timer_peripheral, uint8_t mode)
{
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_SMS_MASK;
TIM_SMCR(timer_peripheral) |= mode;
@@ -2173,7 +2173,7 @@ void timer_slave_set_mode(u32 timer_peripheral, u8 mode)
@param[in] trigger Unsigned int8. Slave trigger source @ref tim_ts
*/
void timer_slave_set_trigger(u32 timer_peripheral, u8 trigger)
void timer_slave_set_trigger(uint32_t timer_peripheral, uint8_t trigger)
{
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_TS_MASK;
TIM_SMCR(timer_peripheral) |= trigger;

4
lib/stm32/common/timer_common_f24.c
View File

@@ -37,7 +37,7 @@ and similarly for TIM5 for oscillator calibration purposes.
@ref tim5_opt_trigger_remap.
*/
void timer_set_option(u32 timer_peripheral, u32 option)
void timer_set_option(uint32_t timer_peripheral, uint32_t option)
{
if (timer_peripheral == TIM2) {
TIM_OR(timer_peripheral) &= ~TIM2_OR_ITR1_RMP_MASK;
@@ -58,7 +58,7 @@ The timer channel must be set to input capture mode.
@param[in] pol ::tim_ic_pol. Input Capture polarity control.
*/
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_pol pol)
{
/* Clear CCxP and CCxNP to zero. For both edge trigger both fields are

64
lib/stm32/common/usart_common_all.c
View File

@@ -46,9 +46,9 @@ usart_reg_base
@param[in] baud unsigned 32 bit. Baud rate specified in Hz.
*/
void usart_set_baudrate(u32 usart, u32 baud)
void usart_set_baudrate(uint32_t usart, uint32_t baud)
{
u32 clock = rcc_ppre1_frequency;
uint32_t clock = rcc_ppre1_frequency;
#if defined STM32F2 || defined STM32F4
if ((usart == USART1) ||
@@ -85,7 +85,7 @@ usart_reg_base
@param[in] bits unsigned 32 bit. Word length in bits 8 or 9.
*/
void usart_set_databits(u32 usart, u32 bits)
void usart_set_databits(uint32_t usart, uint32_t bits)
{
if (bits == 8) {
USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */
@@ -104,9 +104,9 @@ usart_reg_base
@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits.
*/
void usart_set_stopbits(u32 usart, u32 stopbits)
void usart_set_stopbits(uint32_t usart, uint32_t stopbits)
{
u32 reg32;
uint32_t reg32;
reg32 = USART_CR2(usart);
reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits;
@@ -123,9 +123,9 @@ usart_reg_base
@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity.
*/
void usart_set_parity(u32 usart, u32 parity)
void usart_set_parity(uint32_t usart, uint32_t parity)
{
u32 reg32;
uint32_t reg32;
reg32 = USART_CR1(usart);
reg32 = (reg32 & ~USART_PARITY_MASK) | parity;
@@ -142,9 +142,9 @@ usart_reg_base
@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode.
*/
void usart_set_mode(u32 usart, u32 mode)
void usart_set_mode(uint32_t usart, uint32_t mode)
{
u32 reg32;
uint32_t reg32;
reg32 = USART_CR1(usart);
reg32 = (reg32 & ~USART_MODE_MASK) | mode;
@@ -161,9 +161,9 @@ usart_reg_base
@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol.
*/
void usart_set_flow_control(u32 usart, u32 flowcontrol)
void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol)
{
u32 reg32;
uint32_t reg32;
reg32 = USART_CR3(usart);
reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol;
@@ -177,7 +177,7 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol)
usart_reg_base
*/
void usart_enable(u32 usart)
void usart_enable(uint32_t usart)
{
USART_CR1(usart) |= USART_CR1_UE;
}
@@ -191,7 +191,7 @@ At the end of the current frame, the USART is disabled to reduce power.
usart_reg_base
*/
void usart_disable(u32 usart)
void usart_disable(uint32_t usart)
{
USART_CR1(usart) &= ~USART_CR1_UE;
}
@@ -204,7 +204,7 @@ usart_reg_base
@param[in] data unsigned 16 bit.
*/
void usart_send(u32 usart, u16 data)
void usart_send(uint32_t usart, uint16_t data)
{
/* Send data. */
USART_DR(usart) = (data & USART_DR_MASK);
@@ -221,7 +221,7 @@ usart_reg_base
@returns unsigned 16 bit data word.
*/
u16 usart_recv(u32 usart)
uint16_t usart_recv(uint32_t usart)
{
/* Receive data. */
return USART_DR(usart) & USART_DR_MASK;
@@ -237,7 +237,7 @@ next data word.
usart_reg_base
*/
void usart_wait_send_ready(u32 usart)
void usart_wait_send_ready(uint32_t usart)
{
/* Wait until the data has been transferred into the shift register. */
while ((USART_SR(usart) & USART_SR_TXE) == 0);
@@ -252,7 +252,7 @@ Blocks until the receive data buffer holds a valid received data word.
usart_reg_base
*/
void usart_wait_recv_ready(u32 usart)
void usart_wait_recv_ready(uint32_t usart)
{
/* Wait until the data is ready to be received. */
while ((USART_SR(usart) & USART_SR_RXNE) == 0);
@@ -269,7 +269,7 @@ usart_reg_base
@param[in] data unsigned 16 bit.
*/
void usart_send_blocking(u32 usart, u16 data)
void usart_send_blocking(uint32_t usart, uint16_t data)
{
usart_wait_send_ready(usart);
usart_send(usart, data);
@@ -285,7 +285,7 @@ usart_reg_base
@returns unsigned 16 bit data word.
*/
u16 usart_recv_blocking(u32 usart)
uint16_t usart_recv_blocking(uint32_t usart)
{
usart_wait_recv_ready(usart);
@@ -305,7 +305,7 @@ DMA is available on:
usart_reg_base
*/
void usart_enable_rx_dma(u32 usart)
void usart_enable_rx_dma(uint32_t usart)
{
USART_CR3(usart) |= USART_CR3_DMAR;
}
@@ -317,7 +317,7 @@ void usart_enable_rx_dma(u32 usart)
usart_reg_base
*/
void usart_disable_rx_dma(u32 usart)
void usart_disable_rx_dma(uint32_t usart)
{
USART_CR3(usart) &= ~USART_CR3_DMAR;
}
@@ -335,7 +335,7 @@ DMA is available on:
usart_reg_base
*/
void usart_enable_tx_dma(u32 usart)
void usart_enable_tx_dma(uint32_t usart)
{
USART_CR3(usart) |= USART_CR3_DMAT;
}
@@ -347,7 +347,7 @@ void usart_enable_tx_dma(u32 usart)
usart_reg_base
*/
void usart_disable_tx_dma(u32 usart)
void usart_disable_tx_dma(uint32_t usart)
{
USART_CR3(usart) &= ~USART_CR3_DMAT;
}
@@ -359,7 +359,7 @@ void usart_disable_tx_dma(u32 usart)
usart_reg_base
*/
void usart_enable_rx_interrupt(u32 usart)
void usart_enable_rx_interrupt(uint32_t usart)
{
USART_CR1(usart) |= USART_CR1_RXNEIE;
}
@@ -372,7 +372,7 @@ void usart_enable_rx_interrupt(u32 usart)
usart_reg_base
*/
void usart_disable_rx_interrupt(u32 usart)
void usart_disable_rx_interrupt(uint32_t usart)
{
USART_CR1(usart) &= ~USART_CR1_RXNEIE;
}
@@ -384,7 +384,7 @@ void usart_disable_rx_interrupt(u32 usart)
usart_reg_base
*/
void usart_enable_tx_interrupt(u32 usart)
void usart_enable_tx_interrupt(uint32_t usart)
{
USART_CR1(usart) |= USART_CR1_TXEIE;
}
@@ -396,7 +396,7 @@ void usart_enable_tx_interrupt(u32 usart)
usart_reg_base
*/
void usart_disable_tx_interrupt(u32 usart)
void usart_disable_tx_interrupt(uint32_t usart)
{
USART_CR1(usart) &= ~USART_CR1_TXEIE;
}
@@ -408,7 +408,7 @@ void usart_disable_tx_interrupt(u32 usart)
usart_reg_base
*/
void usart_enable_error_interrupt(u32 usart)
void usart_enable_error_interrupt(uint32_t usart)
{
USART_CR3(usart) |= USART_CR3_EIE;
}
@@ -420,7 +420,7 @@ void usart_enable_error_interrupt(u32 usart)
usart_reg_base
*/
void usart_disable_error_interrupt(u32 usart)
void usart_disable_error_interrupt(uint32_t usart)
{
USART_CR3(usart) &= ~USART_CR3_EIE;
}
@@ -434,7 +434,7 @@ usart_reg_base
@returns boolean: flag set.
*/
bool usart_get_flag(u32 usart, u32 flag)
bool usart_get_flag(uint32_t usart, uint32_t flag)
{
return ((USART_SR(usart) & flag) != 0);
}
@@ -456,9 +456,9 @@ usart_reg_base
@returns boolean: flag and interrupt enable both set.
*/
bool usart_get_interrupt_source(u32 usart, u32 flag)
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag)
{
u32 flag_set = (USART_SR(usart) & flag);
uint32_t flag_set = (USART_SR(usart) & flag);
/* IDLE, RXNE, TC, TXE interrupts */
if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) {
return ((flag_set & USART_CR1(usart)) != 0);