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Changed to use stdint types.

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This commit is contained in:
Piotr Esden-Tempski
2013-06-12 19:11:22 -07:00
parent 7df63fcae0
commit 34de1e776e
127 changed files with 1886 additions and 1895 deletions
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18
lib/cm3/nvic.c
View File

@@ -53,7 +53,7 @@ Enables a user interrupt.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
*/
void nvic_enable_irq(u8 irqn)
void nvic_enable_irq(uint8_t irqn)
{
NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
}
@@ -66,7 +66,7 @@ Disables a user interrupt.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
*/
void nvic_disable_irq(u8 irqn)
void nvic_disable_irq(uint8_t irqn)
{
NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
}
@@ -80,7 +80,7 @@ True if the interrupt has occurred and is waiting for service.
@return Boolean. Interrupt pending.
*/
u8 nvic_get_pending_irq(u8 irqn)
uint8_t nvic_get_pending_irq(uint8_t irqn)
{
return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
@@ -94,7 +94,7 @@ is already pending.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
*/
void nvic_set_pending_irq(u8 irqn)
void nvic_set_pending_irq(uint8_t irqn)
{
NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
}
@@ -108,7 +108,7 @@ interrupt is actively being serviced.
@param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
*/
void nvic_clear_pending_irq(u8 irqn)
void nvic_clear_pending_irq(uint8_t irqn)
{
NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
}
@@ -122,7 +122,7 @@ Interrupt has occurred and is currently being serviced.
@return Boolean. Interrupt active.
*/
u8 nvic_get_active_irq(u8 irqn)
uint8_t nvic_get_active_irq(uint8_t irqn)
{
return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
@@ -134,7 +134,7 @@ u8 nvic_get_active_irq(u8 irqn)
@return Boolean. Interrupt enabled.
*/
u8 nvic_get_irq_enabled(u8 irqn)
uint8_t nvic_get_irq_enabled(uint8_t irqn)
{
return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
}
@@ -152,7 +152,7 @@ scb_set_priority_grouping.
@param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16)
*/
void nvic_set_priority(u8 irqn, u8 priority)
void nvic_set_priority(uint8_t irqn, uint8_t priority)
{
/* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
* negative interrupt numbers assigned to the system interrupts. better
@@ -176,7 +176,7 @@ Registers.
@param[in] irqn Unsigned int16. Interrupt number (0 ... 239)
*/
void nvic_generate_software_interrupt(u16 irqn)
void nvic_generate_software_interrupt(uint16_t irqn)
{
if (irqn <= 239) {
NVIC_STIR |= irqn;

2
lib/cm3/scb.c
View File

@@ -35,7 +35,7 @@ void scb_reset_system(void)
while (1);
}
void scb_set_priority_grouping(u32 prigroup)
void scb_set_priority_grouping(uint32_t prigroup)
{
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
}

10
lib/cm3/sync.c
View File

@@ -19,16 +19,16 @@
#include <libopencm3/cm3/sync.h>
u32 __ldrex(volatile u32 *addr)
uint32_t __ldrex(volatile uint32_t *addr)
{
u32 res;
uint32_t res;
__asm__ volatile ("ldrex %0, [%1]" : "=r" (res) : "r" (addr));
return res;
}
u32 __strex(u32 val, volatile u32 *addr)
uint32_t __strex(uint32_t val, volatile uint32_t *addr)
{
u32 res;
uint32_t res;
__asm__ volatile ("strex %0, %2, [%1]"
: "=&r" (res) : "r" (addr), "r" (val));
return res;
@@ -41,7 +41,7 @@ void __dmb()
void mutex_lock(mutex_t *m)
{
u32 status = 0;
uint32_t status = 0;
do {
/* Wait until the mutex is unlocked. */

20
lib/cm3/systick.c
View File

@@ -46,10 +46,10 @@ LGPL License Terms @ref lgpl_license
The counter is set to the reload value when the counter starts and after it
reaches zero.
@param[in] value u32. 24 bit reload value.
@param[in] value uint32_t. 24 bit reload value.
*/
void systick_set_reload(u32 value)
void systick_set_reload(uint32_t value)
{
STK_LOAD = (value & 0x00FFFFFF);
}
@@ -57,10 +57,10 @@ void systick_set_reload(u32 value)
/*---------------------------------------------------------------------------*/
/** @brief SysTick Read the Automatic Reload Value.
@returns 24 bit reload value as u32.
@returns 24 bit reload value as uint32_t.
*/
u32 systick_get_reload(void)
uint32_t systick_get_reload(void)
{
return STK_LOAD & 0x00FFFFFF;
}
@@ -68,10 +68,10 @@ u32 systick_get_reload(void)
/*---------------------------------------------------------------------------*/
/** @brief Get the current SysTick counter value.
@returns 24 bit current value as u32.
@returns 24 bit current value as uint32_t.
*/
u32 systick_get_value(void)
uint32_t systick_get_value(void)
{
return STK_VAL & 0x00FFFFFF;
}
@@ -81,10 +81,10 @@ u32 systick_get_value(void)
The clock source can be either the AHB clock or the same clock divided by 8.
@param[in] clocksource u8. Clock source from @ref systick_clksource.
@param[in] clocksource uint8_t. Clock source from @ref systick_clksource.
*/
void systick_set_clocksource(u8 clocksource)
void systick_set_clocksource(uint8_t clocksource)
{
if (clocksource < 2) {
STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB);
@@ -140,7 +140,7 @@ the flag is read.
@returns Boolean if flag set.
*/
u8 systick_get_countflag(void)
uint8_t systick_get_countflag(void)
{
if (STK_CTRL & STK_CTRL_COUNTFLAG) {
return 1;
@@ -154,7 +154,7 @@ u8 systick_get_countflag(void)
@returns Current calibration value
*/
u32 systick_get_calib(void)
uint32_t systick_get_calib(void)
{
return STK_CALIB & 0x00FFFFFF;
}

4
lib/lm3s/gpio.c
View File

@@ -37,13 +37,13 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lm3s/gpio.h>
void gpio_set(u32 gpioport, u8 gpios)
void gpio_set(uint32_t gpioport, uint8_t gpios)
{
/* ipaddr[9:2] mask the bits to be set, hence the array index */
GPIO_DATA(gpioport)[gpios] = 0xff;
}
void gpio_clear(u32 gpioport, u8 gpios)
void gpio_clear(uint32_t gpioport, uint8_t gpios)
{
GPIO_DATA(gpioport)[gpios] = 0;
}

26
lib/lm4f/gpio.c
View File

@@ -206,8 +206,8 @@ void gpio_enable_ahb_aperture(void)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
u8 gpios)
void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
uint8_t gpios)
{
switch (mode) {
case GPIO_MODE_OUTPUT:
@@ -267,8 +267,8 @@ void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, u8 gpios)
void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype,
enum gpio_drive_strength drive, uint8_t gpios)
{
if (otype == GPIO_OTYPE_OD) {
GPIO_ODR(gpioport) |= gpios;
@@ -318,10 +318,10 @@ void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios)
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios)
{
u32 pctl32;
u8 pin_mask;
uint32_t pctl32;
uint8_t pin_mask;
int i;
/* Did we mean to disable the alternate function? */
@@ -362,7 +362,7 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together.
*/
void gpio_unlock_commit(u32 gpioport, u8 gpios)
void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios)
{
/* Unlock the GPIO_CR register */
GPIO_LOCK(gpioport) = GPIO_LOCK_UNLOCK_CODE;
@@ -438,7 +438,7 @@ void gpio_unlock_commit(u32 gpioport, u8 gpios)
* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
* @param[in] gpios Pin identifiers. @ref gpio_pin_id
*/
void gpio_toggle(u32 gpioport, u8 gpios)
void gpio_toggle(uint32_t gpioport, uint8_t gpios)
{
/* The mask makes sure we only toggle the GPIOs we want to */
GPIO_DATA(gpioport)[gpios] ^= GPIO_ALL;
@@ -490,7 +490,7 @@ void gpio_toggle(u32 gpioport, u8 gpios)
* @code{.c}
* void gpiof_isr(void)
* {
* u8 serviced_irqs = 0;
* uint8_t serviced_irqs = 0;
*
* // Process individual IRQs
* if (gpio_is_interrupt_source(GPIOF, GPIO0)) {
@@ -524,7 +524,7 @@ void gpio_toggle(u32 gpioport, u8 gpios)
* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
* by OR'ing then together
*/
void gpio_configure_trigger(u32 gpioport, enum gpio_trigger trigger, u8 gpios)
void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, uint8_t gpios)
{
switch (trigger) {
case GPIO_TRIG_LVL_LOW:
@@ -568,7 +568,7 @@ void gpio_configure_trigger(u32 gpioport, enum gpio_trigger trigger, u8 gpios)
* combination of pins may be specified by OR'ing them
* together.
*/
void gpio_enable_interrupts(u32 gpioport, u8 gpios)
void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios)
{
GPIO_IM(gpioport) |= gpios;
}
@@ -586,7 +586,7 @@ void gpio_enable_interrupts(u32 gpioport, u8 gpios)
* combination of pins may be specified by OR'ing them
* together.
*/
void gpio_disable_interrupts(u32 gpioport, u8 gpios)
void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios)
{
GPIO_IM(gpioport) |= gpios;
}

26
lib/lm4f/rcc.c
View File

@@ -100,10 +100,10 @@ Alexandru Gagniuc <mr.nuke.me@gmail.com>
* If write access is desired (i.e. when changing the system clock via the
* fine-grained mechanisms), then include the following line in your code:
* @code
* extern u32 lm4f_rcc_sysclk_freq;
* extern uint32_t lm4f_rcc_sysclk_freq;
* @endcode
*/
u32 lm4f_rcc_sysclk_freq = 16000000;
uint32_t lm4f_rcc_sysclk_freq = 16000000;
/**
@@ -118,7 +118,7 @@ u32 lm4f_rcc_sysclk_freq = 16000000;
*/
void rcc_configure_xtal(xtal_t xtal)
{
u32 reg32;
uint32_t reg32;
reg32 = SYSCTL_RCC;
reg32 &= ~SYSCTL_RCC_XTAL_MASK;
@@ -215,7 +215,7 @@ void rcc_pll_on(void)
*/
void rcc_set_osc_source(osc_src_t src)
{
u32 reg32;
uint32_t reg32;
reg32 = SYSCTL_RCC2;
reg32 &= ~SYSCTL_RCC2_OSCSRC2_MASK;
@@ -270,9 +270,9 @@ void rcc_pll_bypass_enable(void)
* caller's responsibility to ensure that the divisor will not create
* a system clock that is out of spec.
*/
void rcc_set_pll_divisor(u8 div400)
void rcc_set_pll_divisor(uint8_t div400)
{
u32 reg32;
uint32_t reg32;
SYSCTL_RCC |= SYSCTL_RCC_USESYSDIV;
@@ -293,7 +293,7 @@ void rcc_set_pll_divisor(u8 div400)
*/
void rcc_set_pwm_divisor(pwm_clkdiv_t div)
{
u32 reg32;
uint32_t reg32;
reg32 = SYSCTL_RCC;
reg32 &= ~SYSCTL_RCC_PWMDIV_MASK;
@@ -361,7 +361,7 @@ void rcc_wait_for_pll_ready(void)
*
* @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock.
*/
void rcc_change_pll_divisor(u8 pll_div400)
void rcc_change_pll_divisor(uint8_t pll_div400)
{
/* Bypass the PLL while its settings are modified */
rcc_pll_bypass_enable();
@@ -372,7 +372,7 @@ void rcc_change_pll_divisor(u8 pll_div400)
/* Disable PLL bypass to derive the system clock from the PLL clock */
rcc_pll_bypass_disable();
/* Update the system clock frequency for housekeeping */
lm4f_rcc_sysclk_freq = (u32)400E6 / pll_div400;
lm4f_rcc_sysclk_freq = (uint32_t)400E6 / pll_div400;
}
/**
@@ -380,15 +380,15 @@ void rcc_change_pll_divisor(u8 pll_div400)
*
* @return System clock frequency in Hz
*/
u32 rcc_get_system_clock_frequency(void)
uint32_t rcc_get_system_clock_frequency(void)
{
return lm4f_rcc_sysclk_freq;
}
/* Get the clock frequency corresponging to a given XTAL value */
static u32 xtal_to_freq(xtal_t xtal)
static uint32_t xtal_to_freq(xtal_t xtal)
{
const u32 freqs[] = {
const uint32_t freqs[] = {
4000000, /* XTAL_4M */
4096000, /* XTAL_4M_096 */
4915200, /* XTAL_4M_9152 */
@@ -440,7 +440,7 @@ static u32 xtal_to_freq(xtal_t xtal)
*
* @return System clock frequency in Hz
*/
void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, u8 pll_div400)
void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400)
{
/*
* We could be using the PLL at this point, or we could be running of a

74
lib/lm4f/uart.c
View File

@@ -90,7 +90,7 @@
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable(u32 uart)
void uart_enable(uint32_t uart)
{
UART_CTL(uart) |= (UART_CTL_UARTEN | UART_CTL_RXE | UART_CTL_TXE);
}
@@ -100,7 +100,7 @@ void uart_enable(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable(u32 uart)
void uart_disable(uint32_t uart)
{
UART_CTL(uart) &= ~UART_CTL_UARTEN;
}
@@ -111,9 +111,9 @@ void uart_disable(u32 uart)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] baud Baud rate in bits per second (bps).*
*/
void uart_set_baudrate(u32 uart, u32 baud)
void uart_set_baudrate(uint32_t uart, uint32_t baud)
{
u32 clock;
uint32_t clock;
/* Are we running off the internal clock or system clock? */
if (UART_CC(uart) == UART_CC_CS_PIOSC) {
@@ -123,7 +123,7 @@ void uart_set_baudrate(u32 uart, u32 baud)
}
/* Find the baudrate divisor */
u32 div = (((clock * 8) / baud) + 1) / 2;
uint32_t div = (((clock * 8) / baud) + 1) / 2;
/* Set the baudrate divisors */
UART_IBRD(uart) = div / 64;
@@ -136,18 +136,18 @@ void uart_set_baudrate(u32 uart, u32 baud)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] databits number of data bits per transmission.
*/
void uart_set_databits(u32 uart, u8 databits)
void uart_set_databits(uint32_t uart, uint8_t databits)
{
u32 reg32, bits32;
uint32_t reg32, bitint32_t;
/* This has the same effect as using UART_LCRH_WLEN_5/6/7/8 directly */
bits32 = (databits - 5) << 5;
bitint32_t = (databits - 5) << 5;
/* TODO: What about 9 data bits? */
reg32 = UART_LCRH(uart);
reg32 &= ~UART_LCRH_WLEN_MASK;
reg32 |= bits32;
reg32 |= bitint32_t;
UART_LCRH(uart) = reg32;
}
@@ -157,7 +157,7 @@ void uart_set_databits(u32 uart, u8 databits)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] bits the requested number of stopbits, either 1 or 2.
*/
void uart_set_stopbits(u32 uart, u8 stopbits)
void uart_set_stopbits(uint32_t uart, uint8_t stopbits)
{
if (stopbits == 2) {
UART_LCRH(uart) |= UART_LCRH_STP2;
@@ -172,9 +172,9 @@ void uart_set_stopbits(u32 uart, u8 stopbits)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] bits the requested parity scheme.
*/
void uart_set_parity(u32 uart, enum uart_parity parity)
void uart_set_parity(uint32_t uart, enum uart_parity parity)
{
u32 reg32;
uint32_t reg32;
reg32 = UART_LCRH(uart);
reg32 |= UART_LCRH_PEN;
@@ -213,9 +213,9 @@ void uart_set_parity(u32 uart, enum uart_parity parity)
* UART_FLOWCTL_CTS -- enable the CTS line \n
* UART_FLOWCTL_RTS_CTS -- enable both RTS and CTS lines
*/
void uart_set_flow_control(u32 uart, enum uart_flowctl flow)
void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow)
{
u32 reg32 = UART_CTL(uart);
uint32_t reg32 = UART_CTL(uart);
reg32 &= ~(UART_CTL_RTSEN | UART_CTL_CTSEN);
@@ -235,7 +235,7 @@ void uart_set_flow_control(u32 uart, enum uart_flowctl flow)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_clock_from_piosc(u32 uart)
void uart_clock_from_piosc(uint32_t uart)
{
UART_CC(uart) = UART_CC_CS_PIOSC;
}
@@ -245,7 +245,7 @@ void uart_clock_from_piosc(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_clock_from_sysclk(u32 uart)
void uart_clock_from_sysclk(uint32_t uart)
{
UART_CC(uart) = UART_CC_CS_SYSCLK;
}
@@ -272,7 +272,7 @@ void uart_clock_from_sysclk(u32 uart)
* @param[in] uart UART block register address base @ref uart_reg_base
* @param[in] data data to send.
*/
void uart_send(u32 uart, u16 data)
void uart_send(uint32_t uart, uint16_t data)
{
data &= 0xFF;
UART_DR(uart) = data;
@@ -284,7 +284,7 @@ void uart_send(u32 uart, u16 data)
* @param[in] uart UART block register address base @ref uart_reg_base
* @return data from the Rx FIFO.
*/
u16 uart_recv(u32 uart)
uint16_t uart_recv(uint32_t uart)
{
return UART_DR(uart) & UART_DR_DATA_MASK;
}
@@ -300,7 +300,7 @@ u16 uart_recv(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_wait_send_ready(u32 uart)
void uart_wait_send_ready(uint32_t uart)
{
/* Wait until the Tx FIFO is no longer full */
while (UART_FR(uart) & UART_FR_TXFF);
@@ -313,7 +313,7 @@ void uart_wait_send_ready(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_wait_recv_ready(u32 uart)
void uart_wait_recv_ready(uint32_t uart)
{
/* Wait until the Tx FIFO is no longer empty */
while (UART_FR(uart) & UART_FR_RXFE);
@@ -327,7 +327,7 @@ void uart_wait_recv_ready(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_send_blocking(u32 uart, u16 data)
void uart_send_blocking(uint32_t uart, uint16_t data)
{
uart_wait_send_ready(uart);
uart_send(uart, data);
@@ -341,7 +341,7 @@ void uart_send_blocking(u32 uart, u16 data)
* @param[in] uart UART block register address base @ref uart_reg_base
* @return data from the Rx FIFO.
*/
u16 uart_recv_blocking(u32 uart)
uint16_t uart_recv_blocking(uint32_t uart)
{
uart_wait_recv_ready(uart);
return uart_recv(uart);
@@ -395,7 +395,7 @@ u16 uart_recv_blocking(u32 uart)
* @code{.c}
* void uart0_isr(void)
* {
* u32 serviced_irqs = 0;
* uint32_t serviced_irqs = 0;
*
* // Process individual IRQs
* if (uart_is_interrupt_source(UART0, UART_INT_RX)) {
@@ -427,7 +427,7 @@ u16 uart_recv_blocking(u32 uart)
* @param[in] ints Interrupts which to enable. Any combination of interrupts may
* be specified by OR'ing then together
*/
void uart_enable_interrupts(u32 uart, enum uart_interrupt_flag ints)
void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints)
{
UART_IM(uart) |= ints;
}
@@ -443,7 +443,7 @@ void uart_enable_interrupts(u32 uart, enum uart_interrupt_flag ints)
* @param[in] ints Interrupts which to disable. Any combination of interrupts
* may be specified by OR'ing then together
*/
void uart_disable_interrupts(u32 uart, enum uart_interrupt_flag ints)
void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints)
{
UART_IM(uart) &= ~ints;
}
@@ -456,7 +456,7 @@ void uart_disable_interrupts(u32 uart, enum uart_interrupt_flag ints)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_rx_interrupt(u32 uart)
void uart_enable_rx_interrupt(uint32_t uart)
{
uart_enable_interrupts(uart, UART_INT_RX);
}
@@ -466,7 +466,7 @@ void uart_enable_rx_interrupt(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_rx_interrupt(u32 uart)
void uart_disable_rx_interrupt(uint32_t uart)
{
uart_disable_interrupts(uart, UART_INT_RX);
}
@@ -479,7 +479,7 @@ void uart_disable_rx_interrupt(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_tx_interrupt(u32 uart)
void uart_enable_tx_interrupt(uint32_t uart)
{
uart_enable_interrupts(uart, UART_INT_TX);
}
@@ -489,7 +489,7 @@ void uart_enable_tx_interrupt(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_tx_interrupt(u32 uart)
void uart_disable_tx_interrupt(uint32_t uart)
{
uart_disable_interrupts(uart, UART_INT_TX);
}
@@ -505,7 +505,7 @@ void uart_disable_tx_interrupt(u32 uart)
* @param[in] ints Interrupts which to clear. Any combination of interrupts may
* be specified by OR'ing then together
*/
void uart_clear_interrupt_flag(u32 uart, enum uart_interrupt_flag ints)
void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints)
{
UART_ICR(uart) |= ints;
}
@@ -524,7 +524,7 @@ void uart_clear_interrupt_flag(u32 uart, enum uart_interrupt_flag ints)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_rx_dma(u32 uart)
void uart_enable_rx_dma(uint32_t uart)
{
UART_DMACTL(uart) |= UART_DMACTL_RXDMAE;
}
@@ -534,7 +534,7 @@ void uart_enable_rx_dma(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_rx_dma(u32 uart)
void uart_disable_rx_dma(uint32_t uart)
{
UART_DMACTL(uart) &= ~UART_DMACTL_RXDMAE;
}
@@ -544,7 +544,7 @@ void uart_disable_rx_dma(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_tx_dma(u32 uart)
void uart_enable_tx_dma(uint32_t uart)
{
UART_DMACTL(uart) |= UART_DMACTL_TXDMAE;
}
@@ -554,7 +554,7 @@ void uart_enable_tx_dma(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_tx_dma(u32 uart)
void uart_disable_tx_dma(uint32_t uart)
{
UART_DMACTL(uart) &= ~UART_DMACTL_TXDMAE;
}
@@ -591,7 +591,7 @@ void uart_disable_tx_dma(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_enable_fifo(u32 uart)
void uart_enable_fifo(uint32_t uart)
{
UART_LCRH(uart) |= UART_LCRH_FEN;
}
@@ -601,7 +601,7 @@ void uart_enable_fifo(u32 uart)
*
* @param[in] uart UART block register address base @ref uart_reg_base
*/
void uart_disable_fifo(u32 uart)
void uart_disable_fifo(uint32_t uart)
{
UART_LCRH(uart) &= ~UART_LCRH_FEN;
}
@@ -613,7 +613,7 @@ void uart_disable_fifo(u32 uart)
* @param[in] rx_level Trigger level for RX FIFO
* @param[in] tx_level Trigger level for TX FIFO
*/
void uart_set_fifo_trigger_levels(u32 uart,
void uart_set_fifo_trigger_levels(uint32_t uart,
enum uart_fifo_rx_trigger_level rx_level,
enum uart_fifo_tx_trigger_level tx_level)
{

64
lib/lm4f/usb_lm4f.c
View File

@@ -176,24 +176,24 @@ static inline void lm4f_usb_soft_connect(void)
USB_POWER |= USB_POWER_SOFTCONN;
}
static void lm4f_set_address(usbd_device *usbd_dev, u8 addr)
static void lm4f_set_address(usbd_device *usbd_dev, uint8_t addr)
{
(void)usbd_dev;
USB_FADDR = addr & USB_FADDR_FUNCADDR_MASK;
}
static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
void (*callback) (usbd_device *usbd_dev, u8 ep))
static void lm4f_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size,
void (*callback) (usbd_device *usbd_dev, uint8_t ep))
{
(void)usbd_dev;
(void)type;
u8 reg8;
u16 fifo_size;
uint8_t reg8;
uint16_t fifo_size;
const bool dir_tx = addr & 0x80;
const u8 ep = addr & 0x0f;
const uint8_t ep = addr & 0x0f;
/*
* We do not mess with the maximum packet size, but we can only allocate
@@ -296,11 +296,11 @@ static void lm4f_endpoints_reset(usbd_device *usbd_dev)
usbd_dev->fifo_mem_top = 64;
}
static void lm4f_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
static void lm4f_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
{
(void)usbd_dev;
const u8 ep = addr & 0x0f;
const uint8_t ep = addr & 0x0f;
const bool dir_tx = addr & 0x80;
if (ep == 0) {
@@ -328,11 +328,11 @@ static void lm4f_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
}
}
static u8 lm4f_ep_stall_get(usbd_device *usbd_dev, u8 addr)
static uint8_t lm4f_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
{
(void)usbd_dev;
const u8 ep = addr & 0x0f;
const uint8_t ep = addr & 0x0f;
const bool dir_tx = addr & 0x80;
if (ep == 0) {
@@ -346,7 +346,7 @@ static u8 lm4f_ep_stall_get(usbd_device *usbd_dev, u8 addr)
}
}
static void lm4f_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
static void lm4f_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
{
(void)usbd_dev;
(void)addr;
@@ -355,11 +355,11 @@ static void lm4f_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
/* NAK's are handled automatically by hardware. Move along. */
}
static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
const void *buf, u16 len)
static uint16_t lm4f_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len)
{
const u8 ep = addr & 0xf;
u16 i;
const uint8_t ep = addr & 0xf;
uint16_t i;
(void)usbd_dev;
@@ -376,14 +376,14 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
* performance, but we don't crash.
*/
for (i = 0; i < (len & ~0x3); i += 4) {
USB_FIFO32(ep) = *((u32 *)(buf + i));
USB_FIFO32(ep) = *((uint32_t *)(buf + i));
}
if (len & 0x2) {
USB_FIFO16(ep) = *((u16 *)(buf + i));
USB_FIFO16(ep) = *((uint16_t *)(buf + i));
i += 2;
}
if (len & 0x1) {
USB_FIFO8(ep) = *((u8 *)(buf + i));
USB_FIFO8(ep) = *((uint8_t *)(buf + i));
}
if (ep == 0) {
@@ -405,15 +405,15 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr,
return i;
}
static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
u16 len)
static uint16_t lm4f_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf,
uint16_t len)
{
(void)usbd_dev;
u16 rlen;
u8 ep = addr & 0xf;
uint16_t rlen;
uint8_t ep = addr & 0xf;
u16 fifoin = USB_RXCOUNT(ep);
uint16_t fifoin = USB_RXCOUNT(ep);
rlen = (fifoin > len) ? len : fifoin;
@@ -423,14 +423,14 @@ static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
* performance, but we don't crash.
*/
for (len = 0; len < (rlen & ~0x3); len += 4) {
*((u32 *)(buf + len)) = USB_FIFO32(ep);
*((uint32_t *)(buf + len)) = USB_FIFO32(ep);
}
if (rlen & 0x2) {
*((u16 *)(buf + len)) = USB_FIFO16(ep);
*((uint16_t *)(buf + len)) = USB_FIFO16(ep);
len += 2;
}
if (rlen & 0x1) {
*((u8 *)(buf + len)) = USB_FIFO8(ep);
*((uint8_t *)(buf + len)) = USB_FIFO8(ep);
}
if (ep == 0) {
@@ -454,8 +454,8 @@ static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
static void lm4f_poll(usbd_device *usbd_dev)
{
void (*tx_cb)(usbd_device *usbd_dev, u8 ea);
void (*rx_cb)(usbd_device *usbd_dev, u8 ea);
void (*tx_cb)(usbd_device *usbd_dev, uint8_t ea);
void (*rx_cb)(usbd_device *usbd_dev, uint8_t ea);
int i;
/*
@@ -463,10 +463,10 @@ static void lm4f_poll(usbd_device *usbd_dev)
* interrupt, but we need the initial state in order to decide how to
* handle events.
*/
const u8 usb_is = USB_IS;
const u8 usb_rxis = USB_RXIS;
const u8 usb_txis = USB_TXIS;
const u8 usb_csrl0 = USB_CSRL0;
const uint8_t usb_is = USB_IS;
const uint8_t usb_rxis = USB_RXIS;
const uint8_t usb_txis = USB_TXIS;
const uint8_t usb_csrl0 = USB_CSRL0;
if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend)) {
usbd_dev->user_callback_suspend();

2
lib/lpc13xx/gpio.c
View File

@@ -33,7 +33,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc13xx/gpio.h>
void gpio_set(u32 gpioport, u16 gpios)
void gpio_set(uint32_t gpioport, uint16_t gpios)
{
GPIO_DATA(gpioport) = gpios;
}

4
lib/lpc17xx/gpio.c
View File

@@ -34,12 +34,12 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc17xx/gpio.h>
void gpio_set(u32 gpioport, u32 gpios)
void gpio_set(uint32_t gpioport, uint32_t gpios)
{
GPIO_SET(gpioport) = gpios;
}
void gpio_clear(u32 gpioport, u32 gpios)
void gpio_clear(uint32_t gpioport, uint32_t gpios)
{
GPIO_CLR(gpioport) = gpios;
}

6
lib/lpc43xx/gpio.c
View File

@@ -34,17 +34,17 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/lpc43xx/gpio.h>
void gpio_set(u32 gpioport, u32 gpios)
void gpio_set(uint32_t gpioport, uint32_t gpios)
{
GPIO_SET(gpioport) = gpios;
}
void gpio_clear(u32 gpioport, u32 gpios)
void gpio_clear(uint32_t gpioport, uint32_t gpios)
{
GPIO_CLR(gpioport) = gpios;
}
void gpio_toggle(u32 gpioport, u32 gpios)
void gpio_toggle(uint32_t gpioport, uint32_t gpios)
{
GPIO_NOT(gpioport) = gpios;
}

4
lib/lpc43xx/i2c.c
View File

@@ -79,7 +79,7 @@ void i2c0_tx_start(void)
}
/* transmit data byte */
void i2c0_tx_byte(u8 byte)
void i2c0_tx_byte(uint8_t byte)
{
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;
@@ -90,7 +90,7 @@ void i2c0_tx_byte(u8 byte)
}
/* receive data byte */
u8 i2c0_rx_byte(void)
uint8_t i2c0_rx_byte(void)
{
if (I2C0_CONSET & I2C_CONSET_STA) {
I2C0_CONCLR = I2C_CONCLR_STAC;

2
lib/lpc43xx/scu.c
View File

@@ -37,7 +37,7 @@ LGPL License Terms @ref lgpl_license
/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for
* different I/O pins types
*/
void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf)
void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf)
{
MMIO32(group_pin) = scu_conf;
}

20
lib/lpc43xx/ssp.c
View File

@@ -59,7 +59,7 @@ void ssp_wait_until_not_busy(ssp_num_t ssp_num);
/* Disable SSP */
void ssp_disable(ssp_num_t ssp_num)
{
u32 ssp_port;
uint32_t ssp_port;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
@@ -77,14 +77,14 @@ void ssp_init(ssp_num_t ssp_num,
ssp_datasize_t data_size,
ssp_frame_format_t frame_format,
ssp_cpol_cpha_t cpol_cpha_format,
u8 serial_clock_rate,
u8 clk_prescale,
uint8_t serial_clock_rate,
uint8_t clk_prescale,
ssp_mode_t mode,
ssp_master_slave_t master_slave,
ssp_slave_option_t slave_option)
{
u32 ssp_port;
u32 clock;
uint32_t ssp_port;
uint32_t clock;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
@@ -112,9 +112,9 @@ void ssp_init(ssp_num_t ssp_num,
/*
* This Function Wait until Data RX Ready, and return Data Read from SSP.
*/
u16 ssp_read(ssp_num_t ssp_num)
uint16_t ssp_read(ssp_num_t ssp_num)
{
u32 ssp_port;
uint32_t ssp_port;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
@@ -130,7 +130,7 @@ u16 ssp_read(ssp_num_t ssp_num)
void ssp_wait_until_not_busy(ssp_num_t ssp_num)
{
u32 ssp_port;
uint32_t ssp_port;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;
@@ -142,9 +142,9 @@ void ssp_wait_until_not_busy(ssp_num_t ssp_num)
}
/* This Function Wait Data TX Ready, and Write Data to SSP */
void ssp_write(ssp_num_t ssp_num, u16 data)
void ssp_write(ssp_num_t ssp_num, uint16_t data)
{
u32 ssp_port;
uint32_t ssp_port;
if (ssp_num == SSP0_NUM) {
ssp_port = SSP0;

6
lib/sam/common/gpio.c
View File

@@ -19,7 +19,7 @@
#include <libopencm3/sam/gpio.h>
void gpio_init(u32 port, u32 pins, enum gpio_flags flags)
void gpio_init(uint32_t port, uint32_t pins, enum gpio_flags flags)
{
switch (flags & 3) {
case GPIO_FLAG_GPINPUT:
@@ -55,9 +55,9 @@ void gpio_init(u32 port, u32 pins, enum gpio_flags flags)
}
}
void gpio_toggle(u32 gpioport, u32 gpios)
void gpio_toggle(uint32_t gpioport, uint32_t gpios)
{
u32 odsr = PIO_ODSR(gpioport);
uint32_t odsr = PIO_ODSR(gpioport);
PIO_CODR(gpioport) = odsr & gpios;
PIO_SODR(gpioport) = ~odsr & gpios;
}

10
lib/sam/common/pmc.c
View File

@@ -21,9 +21,9 @@
#include <libopencm3/sam/eefc.h>
/** Default peripheral clock frequency after reset. */
u32 pmc_mck_frequency = 4000000;
uint32_t pmc_mck_frequency = 4000000;
void pmc_xtal_enable(bool en, u8 startup_time)
void pmc_xtal_enable(bool en, uint8_t startup_time)
{
if (en) {
CKGR_MOR = (CKGR_MOR & ~CKGR_MOR_MOSCXTST_MASK) |
@@ -35,14 +35,14 @@ void pmc_xtal_enable(bool en, u8 startup_time)
}
}
void pmc_plla_config(u8 mul, u8 div)
void pmc_plla_config(uint8_t mul, uint8_t div)
{
CKGR_PLLAR = CKGR_PLLAR_ONE | ((mul - 1) << 16) |
CKGR_PLLAR_PLLACOUNT_MASK | div;
while (!(PMC_SR & PMC_SR_LOCKA));
}
void pmc_peripheral_clock_enable(u8 pid)
void pmc_peripheral_clock_enable(uint8_t pid)
{
if (pid < 32) {
PMC_PCER0 = 1 << pid;
@@ -51,7 +51,7 @@ void pmc_peripheral_clock_enable(u8 pid)
}
}
void pmc_peripheral_clock_disable(u8 pid)
void pmc_peripheral_clock_disable(uint8_t pid)
{
if (pid < 32) {
PMC_PCDR0 = 1 << pid;

32
lib/sam/common/usart.c
View File

@@ -20,29 +20,29 @@
#include <libopencm3/sam/usart.h>
#include <libopencm3/sam/pmc.h>
void usart_set_baudrate(u32 usart, u32 baud)
void usart_set_baudrate(uint32_t usart, uint32_t baud)
{
USART_BRGR(usart) = pmc_mck_frequency / (16 * baud);
}
void usart_set_databits(u32 usart, int bits)
void usart_set_databits(uint32_t usart, int bits)
{
USART_MR(usart) = (USART_MR(usart) & ~USART_MR_CHRL_MASK) |
((bits - 5) << 6);
}
void usart_set_stopbits(u32 usart, enum usart_stopbits sb)
void usart_set_stopbits(uint32_t usart, enum usart_stopbits sb)
{
USART_MR(usart) = (USART_MR(usart) & ~USART_MR_NBSTOP_MASK) |
(sb << 12);
}
void usart_set_parity(u32 usart, enum usart_parity par)
void usart_set_parity(uint32_t usart, enum usart_parity par)
{
USART_MR(usart) = (USART_MR(usart) & ~USART_MR_PAR_MASK) | (par << 9);
}
void usart_set_mode(u32 usart, enum usart_mode mode)
void usart_set_mode(uint32_t usart, enum usart_mode mode)
{
USART_CR(usart) =
(mode & USART_MODE_RX) ? USART_CR_RXEN : USART_CR_RXDIS;
@@ -50,59 +50,59 @@ void usart_set_mode(u32 usart, enum usart_mode mode)
: USART_CR_TXDIS;
}
void usart_set_flow_control(u32 usart, enum usart_flowcontrol fc)
void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol fc)
{
USART_MR(usart) = (USART_MR(usart) & ~USART_MR_MODE_MASK) |
(fc ? USART_MR_MODE_HW_HANDSHAKING : 0);
}
void usart_enable(u32 usart)
void usart_enable(uint32_t usart)
{
}
void usart_disable(u32 usart)
void usart_disable(uint32_t usart)
{
}
void usart_send(u32 usart, u16 data)
void usart_send(uint32_t usart, uint16_t data)
{
USART_THR(usart) = data;
}
u16 usart_recv(u32 usart)
uint16_t usart_recv(uint32_t usart)
{
return USART_RHR(usart) & 0x1f;
}
void usart_wait_send_ready(u32 usart)
void usart_wait_send_ready(uint32_t usart)
{
while ((USART_CSR(usart) & USART_CSR_TXRDY) == 0);
}
void usart_wait_recv_ready(u32 usart)
void usart_wait_recv_ready(uint32_t usart)
{
while ((USART_CSR(usart) & USART_CSR_RXRDY) == 0);
}
void usart_send_blocking(u32 usart, u16 data)
void usart_send_blocking(uint32_t usart, uint16_t data)
{
usart_wait_send_ready(usart);
usart_send(usart, data);
}
u16 usart_recv_blocking(u32 usart)
uint16_t usart_recv_blocking(uint32_t usart)
{
usart_wait_recv_ready(usart);
return usart_recv(usart);
}
void usart_enable_rx_interrupt(u32 usart)
void usart_enable_rx_interrupt(uint32_t usart)
{
USART_IER(usart) = USART_CSR_RXRDY;
}
void usart_disable_rx_interrupt(u32 usart)
void usart_disable_rx_interrupt(uint32_t usart)
{
USART_IDR(usart) = USART_CSR_RXRDY;
}

66
lib/stm32/can.c
View File

@@ -69,7 +69,7 @@ system.
@param[in] canport Unsigned int32. CAN block register address base @ref
can_reg_base.
*/
void can_reset(u32 canport)
void can_reset(uint32_t canport)
{
if (canport == CAN1) {
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
@@ -98,11 +98,11 @@ Initialize the selected CAN peripheral block.
@param[in] brp Unsigned int32. Baud rate prescaler.
@returns int 0 on success, 1 on initialization failure.
*/
int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp,
int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp,
bool loopback, bool silent)
{
volatile u32 wait_ack;
volatile uint32_t wait_ack;
int ret = 0;
/* Exit from sleep mode. */
@@ -206,10 +206,10 @@ Initialize incoming message filter and assign to FIFO.
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
u32 fr1, u32 fr2, u32 fifo, bool enable)
void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_list_mode,
uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable)
{
u32 filter_select_bit = 0x00000001 << nr;
uint32_t filter_select_bit = 0x00000001 << nr;
/* Request initialization "enter". */
CAN_FMR(canport) |= CAN_FMR_FINIT;
@@ -266,12 +266,12 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
u16 id2, u16 mask2, u32 fifo, bool enable)
void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t mask1,
uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, false, false,
((u32)id1 << 16) | (u32)mask1,
((u32)id2 << 16) | (u32)mask2, fifo, enable);
((uint32_t)id1 << 16) | (uint32_t)mask1,
((uint32_t)id2 << 16) | (uint32_t)mask2, fifo, enable);
}
/*---------------------------------------------------------------------------*/
@@ -284,8 +284,8 @@ void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
u32 fifo, bool enable)
void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, uint32_t mask,
uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, true, false, id, mask, fifo, enable);
}
@@ -302,12 +302,12 @@ void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
u16 id3, u16 id4, u32 fifo, bool enable)
void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t id2,
uint16_t id3, uint16_t id4, uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, false, true,
((u32)id1 << 16) | (u32)id2,
((u32)id3 << 16) | (u32)id4, fifo, enable);
((uint32_t)id1 << 16) | (uint32_t)id2,
((uint32_t)id3 << 16) | (uint32_t)id4, fifo, enable);
}
/*---------------------------------------------------------------------------*/
@@ -320,8 +320,8 @@ void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
@param[in] fifo Unsigned int32. FIFO id.
@param[in] enable bool. Enable filter?
*/
void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
u32 fifo, bool enable)
void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, uint32_t id2,
uint32_t fifo, bool enable)
{
can_filter_init(canport, nr, true, true, id1, id2, fifo, enable);
}
@@ -332,7 +332,7 @@ void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@param[in] irq Unsigned int32. IRQ bit(s).
*/
void can_enable_irq(u32 canport, u32 irq)
void can_enable_irq(uint32_t canport, uint32_t irq)
{
CAN_IER(canport) |= irq;
}
@@ -343,7 +343,7 @@ void can_enable_irq(u32 canport, u32 irq)
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@param[in] irq Unsigned int32. IRQ bit(s).
*/
void can_disable_irq(u32 canport, u32 irq)
void can_disable_irq(uint32_t canport, uint32_t irq)
{
CAN_IER(canport) &= ~irq;
}
@@ -360,13 +360,13 @@ void can_disable_irq(u32 canport, u32 irq)
@returns int 0, 1 or 2 on success and depending on which outgoing mailbox got
selected. -1 if no mailbox was available and no transmission got queued.
*/
int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data)
{
int ret = 0;
u32 mailbox = 0;
uint32_t mailbox = 0;
union {
u8 data8[4];
u32 data32;
uint8_t data8[4];
uint32_t data32;
} tdlxr, tdhxr;
/* Check which transmit mailbox is empty if any. */
@@ -451,7 +451,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
@param[in] canport Unsigned int32. CAN block register base @ref can_reg_base.
@param[in] fifo Unsigned int8. FIFO id.
*/
void can_fifo_release(u32 canport, u8 fifo)
void can_fifo_release(uint32_t canport, uint8_t fifo)
{
if (fifo == 0) {
CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
@@ -473,15 +473,15 @@ void can_fifo_release(u32 canport, u8 fifo)
@param[out] length Unsigned int8 pointer. Length of message payload.
@param[out] data Unsigned int8[]. Message payload data.
*/
void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
bool *rtr, u32 *fmi, u8 *length, u8 *data)
void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext,
bool *rtr, uint32_t *fmi, uint8_t *length, uint8_t *data)
{
u32 fifo_id = 0;
uint32_t fifo_id = 0;
union {
u8 data8[4];
u32 data32;
uint8_t data8[4];
uint32_t data32;
} rdlxr, rdhxr;
const u32 fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
const uint32_t fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1};
fifo_id = fifoid_array[fifo];
@@ -544,7 +544,7 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
}
}
bool can_available_mailbox(u32 canport)
bool can_available_mailbox(uint32_t canport)
{
return CAN_TSR(canport) & (CAN_TSR_TME0 | CAN_TSR_TME1 | CAN_TSR_TME2);
}

4
lib/stm32/common/crc_common_all.c
View File

@@ -49,7 +49,7 @@ computation is complete.
@returns int32 Computed CRC result
*/
u32 crc_calculate(u32 data)
uint32_t crc_calculate(uint32_t data)
{
CRC_DR = data;
/* Data sheet says this blocks until it's ready.... */
@@ -67,7 +67,7 @@ until the computation of each word is complete.
@returns int32 Final computed CRC result
*/
u32 crc_calculate_block(u32 *datap, int size)
uint32_t crc_calculate_block(uint32_t *datap, int size)
{
int i;

24
lib/stm32/common/dac_common_all.c
View File

@@ -82,7 +82,7 @@ Both DAC channels are enabled, and both triggers are set to the same timer
dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT);
dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT);
dma_set_read_from_memory(DMA2,DMA_CHANNEL3);
dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(u32) &DAC_DHR8RD);
dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(uint32_t) &DAC_DHR8RD);
dma_enable_channel(DMA2,DMA_CHANNEL3);
...
dac_trigger_enable(CHANNEL_D);
@@ -320,12 +320,12 @@ void dac_trigger_disable(data_channel dac_channel)
Sets the digital to analog converter trigger source, which can be taken from
various timers, an external trigger or a software trigger.
@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref
@param[in] dac_trig_src uint32_t. Taken from @ref dac_trig2_sel or @ref
dac_trig1_sel or a logical OR of one of each of these to set both channels
simultaneously.
*/
void dac_set_trigger_source(u32 dac_trig_src)
void dac_set_trigger_source(uint32_t dac_trig_src)
{
DAC_CR |= dac_trig_src;
}
@@ -339,11 +339,11 @@ existing output values in the DAC output registers.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en
@param[in] dac_wave_ens uint32_t. Taken from @ref dac_wave1_en or @ref dac_wave2_en
or a logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_generation(u32 dac_wave_ens)
void dac_set_waveform_generation(uint32_t dac_wave_ens)
{
DAC_CR |= dac_wave_ens;
}
@@ -387,11 +387,11 @@ the signal output.
become read-only.
@note The DAC trigger must be enabled for this to work.
@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a
@param[in] dac_mamp uint32_t. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a
logical OR of one of each of these to set both channels simultaneously.
*/
void dac_set_waveform_characteristics(u32 dac_mamp)
void dac_set_waveform_characteristics(uint32_t dac_mamp)
{
DAC_CR |= dac_mamp;
}
@@ -405,12 +405,12 @@ data to be converted on a channel. The data can be aligned as follows:
@li right-aligned 12 bit data in bits 0-11
@li left aligned 12 bit data in bits 4-15
@param[in] dac_data u16 with appropriate alignment.
@param[in] dac_data uint16_t with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Alignment and size.
@param[in] dac_channel enum ::data_channel.
*/
void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format,
void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format,
data_channel dac_channel)
{
if (dac_channel == CHANNEL_1) {
@@ -448,13 +448,13 @@ Loads the appropriate digital to analog converter dual data register with 12 or
simultaneous or independent analog output. The data in both channels are aligned
identically.
@param[in] dac_data1 u16 for channel 1 with appropriate alignment.
@param[in] dac_data2 u16 for channel 2 with appropriate alignment.
@param[in] dac_data1 uint16_t for channel 1 with appropriate alignment.
@param[in] dac_data2 uint16_t for channel 2 with appropriate alignment.
@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or
12 bit.
*/
void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2,
void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2,
data_align dac_data_format)
{
switch (dac_data_format) {

58
lib/stm32/common/dma_common_f13.c
View File

@@ -49,7 +49,7 @@ The channel is disabled and configuration registers are cleared.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_channel_reset(u32 dma, u8 channel)
void dma_channel_reset(uint32_t dma, uint8_t channel)
{
/* Disable channel and reset config bits. */
DMA_CCR(dma, channel) = 0;
@@ -75,10 +75,10 @@ same channel may be cleared by using the logical OR of the interrupt flags.
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts)
{
/* Get offset to interrupt flag location in channel field */
u32 flags = (interrupts << DMA_FLAG_OFFSET(channel));
uint32_t flags = (interrupts << DMA_FLAG_OFFSET(channel));
DMA_IFCR(dma) = flags;
}
@@ -93,10 +93,10 @@ The interrupt flag for the channel is returned.
@returns bool interrupt flag is set.
*/
bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt)
bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupt)
{
/* get offset to interrupt flag location in channel field. */
u32 flag = (interrupt << DMA_FLAG_OFFSET(channel));
uint32_t flag = (interrupt << DMA_FLAG_OFFSET(channel));
return ((DMA_ISR(dma) & flag) > 0);
}
@@ -111,7 +111,7 @@ intervention.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_mem2mem_mode(u32 dma, u8 channel)
void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_MEM2MEM;
DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC;
@@ -128,7 +128,7 @@ hardware priority.
@param[in] prio unsigned int32. Priority level @ref dma_ch_pri.
*/
void dma_set_priority(u32 dma, u8 channel, u32 prio)
void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PL_MASK);
DMA_CCR(dma, channel) |= prio;
@@ -145,7 +145,7 @@ alignment information if the source and destination widths do not match.
@param[in] mem_size unsigned int32. Memory word width @ref dma_ch_memwidth.
*/
void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size)
void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_MSIZE_MASK);
@@ -165,7 +165,7 @@ if the peripheral does not support byte or half-word writes.
dma_ch_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size)
void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size)
{
DMA_CCR(dma, channel) &= ~(DMA_CCR_PSIZE_MASK);
DMA_CCR(dma, channel) |= peripheral_size;
@@ -182,7 +182,7 @@ value held by the base memory address register is unchanged.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_memory_increment_mode(u32 dma, u8 channel)
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_MINC;
}
@@ -194,7 +194,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_memory_increment_mode(u32 dma, u8 channel)
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_MINC;
}
@@ -210,7 +210,7 @@ value held by the base peripheral address register is unchanged.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_PINC;
}
@@ -222,7 +222,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_peripheral_increment_mode(u32 dma, u8 channel)
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_PINC;
}
@@ -241,7 +241,7 @@ disabled here.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_circular_mode(u32 dma, u8 channel)
void dma_enable_circular_mode(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_CIRC;
DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM;
@@ -256,7 +256,7 @@ The data direction is set to read from a peripheral.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_set_read_from_peripheral(u32 dma, u8 channel)
void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_DIR;
}
@@ -270,7 +270,7 @@ The data direction is set to read from memory.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_set_read_from_memory(u32 dma, u8 channel)
void dma_set_read_from_memory(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_DIR;
}
@@ -282,7 +282,7 @@ void dma_set_read_from_memory(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_TEIE;
}
@@ -294,7 +294,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE;
}
@@ -306,7 +306,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_HTIE;
}
@@ -318,7 +318,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE;
}
@@ -330,7 +330,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_TCIE;
}
@@ -342,7 +342,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE;
}
@@ -354,7 +354,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_enable_channel(u32 dma, u8 channel)
void dma_enable_channel(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) |= DMA_CCR_EN;
}
@@ -369,7 +369,7 @@ disabled.
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
*/
void dma_disable_channel(u32 dma, u8 channel)
void dma_disable_channel(uint32_t dma, uint8_t channel)
{
DMA_CCR(dma, channel) &= ~DMA_CCR_EN;
}
@@ -388,10 +388,10 @@ function has no effect if the channel is enabled.
@param[in] address unsigned int32. Peripheral Address.
*/
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CPAR(dma, channel) = (u32) address;
DMA_CPAR(dma, channel) = (uint32_t) address;
}
}
@@ -406,10 +406,10 @@ function has no effect if the channel is enabled.
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address)
{
if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) {
DMA_CMAR(dma, channel) = (u32) address;
DMA_CMAR(dma, channel) = (uint32_t) address;
}
}
@@ -425,7 +425,7 @@ count is not changed if the channel is enabled.
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number)
{
DMA_CNDTR(dma, channel) = number;
}

114
lib/stm32/common/dma_common_f24.c
View File

@@ -57,7 +57,7 @@ The specified stream is disabled and configuration registers are cleared.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_stream_reset(u32 dma, u8 stream)
void dma_stream_reset(uint32_t dma, uint8_t stream)
{
/* Disable stream (must be done before register is otherwise changed). */
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
@@ -72,7 +72,7 @@ void dma_stream_reset(u32 dma, u8 stream)
/* This is the default setting */
DMA_SFCR(dma, stream) = 0x21;
/* Reset all stream interrupt flags using the interrupt flag clear register. */
u32 mask = DMA_ISR_MASK(stream);
uint32_t mask = DMA_ISR_MASK(stream);
if (stream < 4) {
DMA_LIFCR(dma) |= mask;
} else {
@@ -92,10 +92,10 @@ same stream may be cleared by using the bitwise OR of the interrupt flags.
dma_if_offset
*/
void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts)
void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts)
{
/* Get offset to interrupt flag location in stream field */
u32 flags = (interrupts << DMA_ISR_OFFSET(stream));
uint32_t flags = (interrupts << DMA_ISR_OFFSET(stream));
/* First four streams are in low register. Flag clear must be set then
* reset.
*/
@@ -117,12 +117,12 @@ The interrupt flag for the stream is returned.
@returns bool interrupt flag is set.
*/
bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt)
bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt)
{
/* get offset to interrupt flag location in stream field. Assumes
* stream and interrupt parameters are integers.
*/
u32 flag = (interrupt << DMA_ISR_OFFSET(stream));
uint32_t flag = (interrupt << DMA_ISR_OFFSET(stream));
/* First four streams are in low register */
if (stream < 4) {
return ((DMA_LISR(dma) & flag) > 0);
@@ -145,9 +145,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] direction unsigned int32. Data transfer direction @ref dma_st_dir
*/
void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction)
void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK);
/* Disable circular and double buffer modes if memory to memory
* transfers are in effect. (Direct Mode is automatically disabled by
* hardware)
@@ -173,7 +173,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] prio unsigned int32. Priority level @ref dma_st_pri.
*/
void dma_set_priority(u32 dma, u8 stream, u32 prio)
void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_PL_MASK);
DMA_SCR(dma, stream) |= prio;
@@ -192,7 +192,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] mem_size unsigned int32. Memory word width @ref dma_st_memwidth.
*/
void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size)
void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK);
DMA_SCR(dma, stream) |= mem_size;
@@ -213,7 +213,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
dma_st_perwidth.
*/
void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size)
void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size)
{
DMA_SCR(dma, stream) &= ~(DMA_SxCR_PSIZE_MASK);
DMA_SCR(dma, stream) |= peripheral_size;
@@ -232,7 +232,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_memory_increment_mode(u32 dma, u8 stream)
void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_MINC;
}
@@ -246,7 +246,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_memory_increment_mode(u32 dma, u8 stream)
void dma_disable_memory_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC;
}
@@ -264,9 +264,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_peripheral_increment_mode(u32 dma, u8 stream)
void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
u32 reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC);
uint32_t reg32 = (DMA_SCR(dma, stream) | DMA_SxCR_PINC);
DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS);
}
@@ -279,7 +279,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_peripheral_increment_mode(u32 dma, u8 stream)
void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC;
}
@@ -297,7 +297,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream)
void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS);
}
@@ -319,7 +319,7 @@ It is enabled automatically if double buffered mode is selected.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_circular_mode(u32 dma, u8 stream)
void dma_enable_circular_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_CIRC;
}
@@ -338,7 +338,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] channel unsigned int8. Channel selection @ref dma_ch_sel
*/
void dma_channel_select(u32 dma, u8 stream, u32 channel)
void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel)
{
DMA_SCR(dma, stream) |= channel;
}
@@ -356,9 +356,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] burst unsigned int8. Memory Burst selection @ref dma_mburst
*/
void dma_set_memory_burst(u32 dma, u8 stream, u32 burst)
void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_MBURST_MASK);
DMA_SCR(dma, stream) = (reg32 | burst);
}
@@ -375,9 +375,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] burst unsigned int8. Peripheral Burst selection @ref dma_pburst
*/
void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst)
void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_PBURST_MASK);
DMA_SCR(dma, stream) = (reg32 | burst);
}
@@ -394,9 +394,9 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] memory unsigned int8. Initial memory pointer to use: 0 or 1
*/
void dma_set_initial_target(u32 dma, u8 stream, u8 memory)
void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory)
{
u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
uint32_t reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT);
if (memory == 1) {
reg32 |= DMA_SxCR_CT;
}
@@ -417,7 +417,7 @@ the stream to be disabled and the transfer error flag to be set.
@returns unsigned int8. Memory buffer in use: 0 or 1
*/
u8 dma_get_target(u32 dma, u8 stream)
uint8_t dma_get_target(uint32_t dma, uint8_t stream)
{
if (DMA_SCR(dma, stream) & DMA_SxCR_CT) {
return 1;
@@ -441,7 +441,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_double_buffer_mode(u32 dma, u8 stream)
void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_DBM;
}
@@ -453,7 +453,7 @@ void dma_enable_double_buffer_mode(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_double_buffer_mode(u32 dma, u8 stream)
void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM;
}
@@ -470,7 +470,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_set_peripheral_flow_control(u32 dma, u8 stream)
void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL;
}
@@ -486,7 +486,7 @@ Ensure that the stream is disabled otherwise the setting will not be changed.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_set_dma_flow_control(u32 dma, u8 stream)
void dma_set_dma_flow_control(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL;
}
@@ -498,7 +498,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_TEIF);
DMA_SCR(dma, stream) |= DMA_SxCR_TEIE;
@@ -511,7 +511,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE;
}
@@ -523,7 +523,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_HTIF);
DMA_SCR(dma, stream) |= DMA_SxCR_HTIE;
@@ -536,7 +536,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE;
}
@@ -548,7 +548,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_TCIF);
DMA_SCR(dma, stream) |= DMA_SxCR_TCIE;
@@ -561,7 +561,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE;
}
@@ -573,7 +573,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_DMEIF);
DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE;
@@ -586,7 +586,7 @@ void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE;
}
@@ -598,7 +598,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
{
dma_clear_interrupt_flags(dma, stream, DMA_FEIF);
DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE;
@@ -611,7 +611,7 @@ void dma_enable_fifo_error_interrupt(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_fifo_error_interrupt(u32 dma, u8 stream)
void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE;
}
@@ -624,10 +624,10 @@ meaning if direct mode is enabled (as the FIFO is not used).
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
@returns u32 FIFO Status @ref dma_fifo_status
@returns uint32_t FIFO Status @ref dma_fifo_status
*/
u32 dma_fifo_status(u32 dma, u8 stream)
uint32_t dma_fifo_status(uint32_t dma, uint8_t stream)
{
return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK;
}
@@ -643,7 +643,7 @@ mode is selected.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_direct_mode(u32 dma, u8 stream)
void dma_enable_direct_mode(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS;
}
@@ -657,7 +657,7 @@ Data is transferred via a FIFO.
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_fifo_mode(u32 dma, u8 stream)
void dma_enable_fifo_mode(uint32_t dma, uint8_t stream)
{
DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS;
}
@@ -673,9 +673,9 @@ destination.
@param[in] threshold unsigned int8. Threshold setting @ref dma_fifo_thresh
*/
void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold)
{
u32 reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK);
uint32_t reg32 = (DMA_SFCR(dma, stream) & ~DMA_SxFCR_FTH_MASK);
DMA_SFCR(dma, stream) = (reg32 | threshold);
}
@@ -686,7 +686,7 @@ void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_enable_stream(u32 dma, u8 stream)
void dma_enable_stream(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) |= DMA_SxCR_EN;
}
@@ -700,7 +700,7 @@ void dma_enable_stream(u32 dma, u8 stream)
@param[in] stream unsigned int8. Stream number: @ref dma_st_number
*/
void dma_disable_stream(u32 dma, u8 stream)
void dma_disable_stream(uint32_t dma, uint8_t stream)
{
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
}
@@ -719,10 +719,10 @@ has no effect if the stream is enabled.
@param[in] address unsigned int32. Peripheral Address.
*/
void dma_set_peripheral_address(u32 dma, u8 stream, u32 address)
void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address)
{
if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) {
DMA_SPAR(dma, stream) = (u32 *) address;
DMA_SPAR(dma, stream) = (uint32_t *) address;
}
}
@@ -741,12 +741,12 @@ This is the default base memory address used in direct mode.
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address(u32 dma, u8 stream, u32 address)
void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address)
{
u32 reg32 = DMA_SCR(dma, stream);
uint32_t reg32 = DMA_SCR(dma, stream);
if (!(reg32 & DMA_SxCR_EN) ||
((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM0AR(dma, stream) = (u32 *) address;
DMA_SM0AR(dma, stream) = (uint32_t *) address;
}
}
@@ -763,12 +763,12 @@ to change this in double buffer mode when the current target is memory area 0
@param[in] address unsigned int32. Memory Initial Address.
*/
void dma_set_memory_address_1(u32 dma, u8 stream, u32 address)
void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address)
{
u32 reg32 = DMA_SCR(dma, stream);
uint32_t reg32 = DMA_SCR(dma, stream);
if (!(reg32 & DMA_SxCR_EN) ||
(!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) {
DMA_SM1AR(dma, stream) = (u32 *) address;
DMA_SM1AR(dma, stream) = (uint32_t *) address;
}
}
@@ -784,7 +784,7 @@ is not changed if the stream is enabled.
maximum).
*/
void dma_set_number_of_data(u32 dma, u8 stream, u16 number)
void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number)
{
DMA_SNDTR(dma, stream) = number;
}

24
lib/stm32/common/flash_common_f24.c
View File

@@ -20,7 +20,7 @@
#include <libopencm3/stm32/flash.h>
static inline void flash_set_program_size(u32 psize)
static inline void flash_set_program_size(uint32_t psize)
{
FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
FLASH_CR |= psize;
@@ -66,9 +66,9 @@ void flash_icache_reset(void)
FLASH_ACR |= FLASH_ACR_ICRST;
}
void flash_set_ws(u32 ws)
void flash_set_ws(uint32_t ws)
{
u32 reg32;
uint32_t reg32;
reg32 = FLASH_ACR;
reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
@@ -151,7 +151,7 @@ void flash_wait_for_last_operation(void)
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
void flash_program_double_word(u32 address, u64 data)
void flash_program_double_word(uint32_t address, uint64_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
@@ -170,7 +170,7 @@ void flash_program_double_word(u32 address, u64 data)
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_word(u32 address, u32 data)
void flash_program_word(uint32_t address, uint32_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
@@ -189,7 +189,7 @@ void flash_program_word(u32 address, u32 data)
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data)
void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
flash_set_program_size(FLASH_CR_PROGRAM_X16);
@@ -203,7 +203,7 @@ void flash_program_half_word(u32 address, u16 data)
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program_byte(u32 address, u8 data)
void flash_program_byte(uint32_t address, uint8_t data)
{
flash_wait_for_last_operation();
flash_set_program_size(FLASH_CR_PROGRAM_X8);
@@ -217,18 +217,18 @@ void flash_program_byte(u32 address, u8 data)
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_program(u32 address, u8 *data, u32 len)
void flash_program(uint32_t address, uint8_t *data, uint32_t len)
{
/* TODO: Use dword and word size program operations where possible for
* turbo speed.
*/
u32 i;
uint32_t i;
for (i = 0; i < len; i++) {
flash_program_byte(address+i, data[i]);
}
}
void flash_erase_sector(u8 sector, u32 program_size)
void flash_erase_sector(uint8_t sector, uint32_t program_size)
{
flash_wait_for_last_operation();
flash_set_program_size(program_size);
@@ -243,7 +243,7 @@ void flash_erase_sector(u8 sector, u32 program_size)
FLASH_CR &= ~(0xF << 3);
}
void flash_erase_all_sectors(u32 program_size)
void flash_erase_all_sectors(uint32_t program_size)
{
flash_wait_for_last_operation();
flash_set_program_size(program_size);
@@ -255,7 +255,7 @@ void flash_erase_all_sectors(u32 program_size)
FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
}
void flash_program_option_bytes(u32 data)
void flash_program_option_bytes(uint32_t data)
{
flash_wait_for_last_operation();

18
lib/stm32/common/gpio_common_all.c
View File

@@ -39,7 +39,7 @@ Set one or more pins of the given GPIO port to 1 in an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_set(u32 gpioport, u16 gpios)
void gpio_set(uint32_t gpioport, uint16_t gpios)
{
GPIO_BSRR(gpioport) = gpios;
}
@@ -54,7 +54,7 @@ Clear one or more pins of the given GPIO port to 0 in an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_clear(u32 gpioport, u16 gpios)
void gpio_clear(uint32_t gpioport, uint16_t gpios)
{
GPIO_BSRR(gpioport) = (gpios << 16);
}
@@ -69,7 +69,7 @@ void gpio_clear(u32 gpioport, u16 gpios)
@return Unsigned int16 value of the pin values. The bit position of the pin
value returned corresponds to the pin number.
*/
u16 gpio_get(u32 gpioport, u16 gpios)
uint16_t gpio_get(uint32_t gpioport, uint16_t gpios)
{
return gpio_port_read(gpioport) & gpios;
}
@@ -84,7 +84,7 @@ Toggle one or more pins of the given GPIO port. This is not an atomic operation.
If multiple pins are to be changed, use logical OR '|' to separate
them.
*/
void gpio_toggle(u32 gpioport, u16 gpios)
void gpio_toggle(uint32_t gpioport, uint16_t gpios)
{
GPIO_ODR(gpioport) ^= gpios;
}
@@ -98,9 +98,9 @@ valid pin data.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@return Unsigned int16. The value held in the specified GPIO port.
*/
u16 gpio_port_read(u32 gpioport)
uint16_t gpio_port_read(uint32_t gpioport)
{
return (u16)GPIO_IDR(gpioport);
return (uint16_t)GPIO_IDR(gpioport);
}
/*---------------------------------------------------------------------------*/
@@ -111,7 +111,7 @@ Write a value to the given GPIO port.
@param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id
@param[in] data Unsigned int16. The value to be written to the GPIO port.
*/
void gpio_port_write(u32 gpioport, u16 data)
void gpio_port_write(uint32_t gpioport, uint16_t data)
{
GPIO_ODR(gpioport) = data;
}
@@ -128,9 +128,9 @@ reset.
If multiple pins are to be locked, use logical OR '|' to separate
them.
*/
void gpio_port_config_lock(u32 gpioport, u16 gpios)
void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios)
{
u32 reg32;
uint32_t reg32;
/* Special "Lock Key Writing Sequence", see datasheet. */
GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */

18
lib/stm32/common/gpio_common_f24.c
View File

@@ -86,10 +86,10 @@ gpio_pup
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios)
{
u16 i;
u32 moder, pupd;
uint16_t i;
uint32_t moder, pupd;
/*
* We want to set the config only for the pins mentioned in gpios,
@@ -128,10 +128,10 @@ port.
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios)
{
u16 i;
u32 ospeedr;
uint16_t i;
uint32_t ospeedr;
if (otype == 0x1) {
GPIO_OTYPER(gpioport) |= gpios;
@@ -173,10 +173,10 @@ gpio_af_num
If multiple pins are to be set, use bitwise OR '|' to separate
them.
*/
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios)
{
u16 i;
u32 afrl, afrh;
uint16_t i;
uint32_t afrl, afrh;
afrl = GPIO_AFRL(gpioport);
afrh = GPIO_AFRH(gpioport);

14
lib/stm32/common/hash_common_f24.c
View File

@@ -40,7 +40,7 @@ Sets up the specified mode - either HASH or HMAC.
@param[in] mode unsigned int8. Hash processor mode: @ref hash_mode
*/
void hash_set_mode(u8 mode)
void hash_set_mode(uint8_t mode)
{
HASH_CR &= ~HASH_CR_MODE;
HASH_CR |= mode;
@@ -54,7 +54,7 @@ Sets up the specified algorithm - either MD5 or SHA1.
@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm
*/
void hash_set_algorithm(u8 algorithm)
void hash_set_algorithm(uint8_t algorithm)
{
HASH_CR &= ~HASH_CR_ALGO;
HASH_CR |= algorithm;
@@ -68,7 +68,7 @@ Sets up the specified data type: 32Bit, 16Bit, 8Bit, Bitstring.
@param[in] datatype unsigned int8. Hash data type: @ref hash_data_type
*/
void hash_set_data_type(u8 datatype)
void hash_set_data_type(uint8_t datatype)
{
HASH_CR &= ~HASH_CR_DATATYPE;
HASH_CR |= datatype;
@@ -82,7 +82,7 @@ Sets up the specified key length: Long, Short.
@param[in] keylength unsigned int8. Hash data type: @ref hash_key_length
*/
void hash_set_key_length(u8 keylength)
void hash_set_key_length(uint8_t keylength)
{
HASH_CR &= ~HASH_CR_LKEY;
HASH_CR |= keylength;
@@ -96,7 +96,7 @@ Specifies the number of valid bits in the last word.
@param[in] validbits unsigned int8. Number of valid bits.
*/
void hash_set_last_word_valid_bits(u8 validbits)
void hash_set_last_word_valid_bits(uint8_t validbits)
{
HASH_STR &= ~(HASH_STR_NBW);
HASH_STR |= 32 - validbits;
@@ -122,7 +122,7 @@ Puts data into the HASH processor's queue.
@param[in] data unsigned int32. Hash input data.
*/
void hash_add_data(u32 data)
void hash_add_data(uint32_t data)
{
HASH_DIN = data;
}
@@ -148,7 +148,7 @@ Makes a copy of the resulting hash.
@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm
*/
void hash_get_result(u32 *data)
void hash_get_result(uint32_t *data)
{
data[0] = HASH_HR[0];
data[1] = HASH_HR[1];

64
lib/stm32/common/i2c_common_all.c
View File

@@ -49,7 +49,7 @@ the reset condition. The reset is effected via the RCC peripheral reset system.
@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
*/
void i2c_reset(u32 i2c)
void i2c_reset(uint32_t i2c)
{
switch (i2c) {
case I2C1:
@@ -69,7 +69,7 @@ void i2c_reset(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_peripheral_enable(u32 i2c)
void i2c_peripheral_enable(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_PE;
}
@@ -83,7 +83,7 @@ In Slave mode, the peripheral is disabled only after communication has ended.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_peripheral_disable(u32 i2c)
void i2c_peripheral_disable(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_PE;
}
@@ -98,7 +98,7 @@ when the current bus activity is completed.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_send_start(u32 i2c)
void i2c_send_start(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_START;
}
@@ -112,7 +112,7 @@ mode, or simply release the bus if in Slave mode.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_send_stop(u32 i2c)
void i2c_send_stop(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_STOP;
}
@@ -124,7 +124,7 @@ Clear the "Send Stop" flag in the I2C config register
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_clear_stop(u32 i2c)
void i2c_clear_stop(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_STOP;
}
@@ -138,9 +138,9 @@ This sets an address for Slave mode operation, in 7 bit form.
@param[in] slave Unsigned int8. Slave address 0...127.
*/
void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave)
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
{
I2C_OAR1(i2c) = (u16)(slave << 1);
I2C_OAR1(i2c) = (uint16_t)(slave << 1);
I2C_OAR1(i2c) &= ~I2C_OAR1_ADDMODE;
I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
}
@@ -156,9 +156,9 @@ This sets an address for Slave mode operation, in 10 bit form.
@param[in] slave Unsigned int16. Slave address 0...1023.
*/
void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave)
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
{
I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave);
I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_ADDMODE | slave);
}
/*---------------------------------------------------------------------------*/
@@ -170,7 +170,7 @@ clock frequency must be set with @ref i2c_set_clock_frequency
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_fast_mode(u32 i2c)
void i2c_set_fast_mode(uint32_t i2c)
{
I2C_CCR(i2c) |= I2C_CCR_FS;
}
@@ -184,7 +184,7 @@ actual clock frequency must be set with @ref i2c_set_clock_frequency
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_standard_mode(u32 i2c)
void i2c_set_standard_mode(uint32_t i2c)
{
I2C_CCR(i2c) &= ~I2C_CCR_FS;
}
@@ -201,9 +201,9 @@ i2c_set_ccr
@param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock.
*/
void i2c_set_clock_frequency(u32 i2c, u8 freq)
void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq)
{
u16 reg16;
uint16_t reg16;
reg16 = I2C_CR2(i2c) & 0xffc0; /* Clear bits [5:0]. */
reg16 |= freq;
I2C_CR2(i2c) = reg16;
@@ -224,9 +224,9 @@ of the CCR field. It is a divisor of the peripheral clock frequency
@param[in] freq Unsigned int16. Bus Clock Frequency Setting 0...4095.
*/
void i2c_set_ccr(u32 i2c, u16 freq)
void i2c_set_ccr(uint32_t i2c, uint16_t freq)
{
u16 reg16;
uint16_t reg16;
reg16 = I2C_CCR(i2c) & 0xf000; /* Clear bits [11:0]. */
reg16 |= freq;
I2C_CCR(i2c) = reg16;
@@ -245,7 +245,7 @@ number.
@param[in] trise Unsigned int16. Rise Time Setting 0...63.
*/
void i2c_set_trise(u32 i2c, u16 trise)
void i2c_set_trise(uint32_t i2c, uint16_t trise)
{
I2C_TRISE(i2c) = trise;
}
@@ -259,9 +259,9 @@ void i2c_set_trise(u32 i2c, u16 trise)
send @ref i2c_rw.
*/
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite)
{
I2C_DR(i2c) = (u8)((slave << 1) | readwrite);
I2C_DR(i2c) = (uint8_t)((slave << 1) | readwrite);
}
/*---------------------------------------------------------------------------*/
@@ -271,7 +271,7 @@ void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite)
@param[in] data Unsigned int8. Byte to send.
*/
void i2c_send_data(u32 i2c, u8 data)
void i2c_send_data(uint32_t i2c, uint8_t data)
{
I2C_DR(i2c) = data;
}
@@ -281,7 +281,7 @@ void i2c_send_data(u32 i2c, u8 data)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
uint8_t i2c_get_data(u32 i2c)
uint8_t i2c_get_data(uint32_t i2c)
{
return I2C_DR(i2c) & 0xff;
}
@@ -292,7 +292,7 @@ uint8_t i2c_get_data(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] interrupt Unsigned int32. Interrupt to enable.
*/
void i2c_enable_interrupt(u32 i2c, u32 interrupt)
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
{
I2C_CR2(i2c) |= interrupt;
}
@@ -303,7 +303,7 @@ void i2c_enable_interrupt(u32 i2c, u32 interrupt)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] interrupt Unsigned int32. Interrupt to disable.
*/
void i2c_disable_interrupt(u32 i2c, u32 interrupt)
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
{
I2C_CR2(i2c) &= ~interrupt;
}
@@ -314,7 +314,7 @@ void i2c_disable_interrupt(u32 i2c, u32 interrupt)
Enables acking of own 7/10 bit address
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_enable_ack(u32 i2c)
void i2c_enable_ack(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_ACK;
}
@@ -325,7 +325,7 @@ void i2c_enable_ack(u32 i2c)
Disables acking of own 7/10 bit address
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_disable_ack(u32 i2c)
void i2c_disable_ack(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_ACK;
}
@@ -336,7 +336,7 @@ void i2c_disable_ack(u32 i2c)
Causes the I2C controller to NACK the reception of the next byte
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_nack_next(u32 i2c)
void i2c_nack_next(uint32_t i2c)
{
I2C_CR1(i2c) |= I2C_CR1_POS;
}
@@ -348,7 +348,7 @@ Causes the I2C controller to NACK the reception of the current byte
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_nack_current(u32 i2c)
void i2c_nack_current(uint32_t i2c)
{
I2C_CR1(i2c) &= ~I2C_CR1_POS;
}
@@ -359,7 +359,7 @@ void i2c_nack_current(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] dutycycle Unsigned int32. I2C duty cycle @ref i2c_duty_cycle.
*/
void i2c_set_dutycycle(u32 i2c, u32 dutycycle)
void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle)
{
if (dutycycle == I2C_CCR_DUTY_DIV2) {
I2C_CCR(i2c) &= ~I2C_CCR_DUTY;
@@ -373,7 +373,7 @@ void i2c_set_dutycycle(u32 i2c, u32 dutycycle)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_enable_dma(u32 i2c)
void i2c_enable_dma(uint32_t i2c)
{
I2C_CR2(i2c) |= I2C_CR2_DMAEN;
}
@@ -383,7 +383,7 @@ void i2c_enable_dma(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_disable_dma(u32 i2c)
void i2c_disable_dma(uint32_t i2c)
{
I2C_CR2(i2c) &= ~I2C_CR2_DMAEN;
}
@@ -393,7 +393,7 @@ void i2c_disable_dma(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_set_dma_last_transfer(u32 i2c)
void i2c_set_dma_last_transfer(uint32_t i2c)
{
I2C_CR2(i2c) |= I2C_CR2_LAST;
}
@@ -403,7 +403,7 @@ void i2c_set_dma_last_transfer(u32 i2c)
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_clear_dma_last_transfer(u32 i2c)
void i2c_clear_dma_last_transfer(uint32_t i2c)
{
I2C_CR2(i2c) &= ~I2C_CR2_LAST;
}

6
lib/stm32/common/iwdg_common_all.c
View File

@@ -66,13 +66,13 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds)
can occasionally occur if the prescale or preload registers are currently busy
loading a previous value.
@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset
@param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog reset
until a system reset is issued.
*/
void iwdg_set_period_ms(u32 period)
void iwdg_set_period_ms(uint32_t period)
{
u32 count, prescale, reload, exponent;
uint32_t count, prescale, reload, exponent;
/* Set the count to represent ticks of the 32kHz LSI clock */
count = (period << 5);

4
lib/stm32/common/pwr_common_all.c
View File

@@ -57,10 +57,10 @@ This provides voltage level threshold detection. The result of detection is
provided in the power voltage detector output flag (see @ref pwr_voltage_high)
or by setting the EXTI16 interrupt (see datasheet for configuration details).
@param[in] pvd_level u32. Taken from @ref pwr_pls.
@param[in] pvd_level uint32_t. Taken from @ref pwr_pls.
*/
void pwr_enable_power_voltage_detect(u32 pvd_level)
void pwr_enable_power_voltage_detect(uint32_t pvd_level)
{
PWR_CR &= ~PWR_CR_PLS_MASK;
PWR_CR |= (PWR_CR_PVDE | pvd_level);

4
lib/stm32/common/rtc_common_bcd.c
View File

@@ -33,7 +33,7 @@
This sets the RTC synchronous and asynchronous prescalars.
*/
void rtc_set_prescaler(u32 sync, u32 async)
void rtc_set_prescaler(uint32_t sync, uint32_t async)
{
/*
* Even if only one of the two fields needs to be changed,
@@ -86,7 +86,7 @@ void rtc_lock(void)
/** @brief Sets the wakeup time auto-reload value
*/
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel)
void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel)
{
/* FTFM:
* The following sequence is required to configure or change the wakeup

100
lib/stm32/common/spi_common_all.c
View File

@@ -79,7 +79,7 @@ the reset condition. The reset is effected via the RCC peripheral reset system.
spi_reg_base.
*/
void spi_reset(u32 spi_peripheral)
void spi_reset(uint32_t spi_peripheral)
{
switch (spi_peripheral) {
case SPI1:
@@ -119,9 +119,9 @@ spi_lsbfirst.
@returns int. Error code.
*/
int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst)
{
u32 reg32 = SPI_CR1(spi);
uint32_t reg32 = SPI_CR1(spi);
/* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */
reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT;
@@ -152,7 +152,7 @@ The SPI peripheral is enabled.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable(u32 spi)
void spi_enable(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */
}
@@ -166,9 +166,9 @@ The SPI peripheral is disabled.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable(u32 spi)
void spi_disable(uint32_t spi)
{
u32 reg32;
uint32_t reg32;
reg32 = SPI_CR1(spi);
reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */
@@ -186,12 +186,12 @@ prevents the BSY flag from becoming unreliable.
@returns data Unsigned int16. 8 or 16 bit data from final read.
*/
u16 spi_clean_disable(u32 spi)
uint16_t spi_clean_disable(uint32_t spi)
{
/* Wait to receive last data */
while (!(SPI_SR(spi) & SPI_SR_RXNE));
u16 data = SPI_DR(spi);
uint16_t data = SPI_DR(spi);
/* Wait to transmit last data */
while (!(SPI_SR(spi) & SPI_SR_TXE));
@@ -213,7 +213,7 @@ Data is written to the SPI interface.
@param[in] data Unsigned int16. 8 or 16 bit data to be written.
*/
void spi_write(u32 spi, u16 data)
void spi_write(uint32_t spi, uint16_t data)
{
/* Write data (8 or 16 bits, depending on DFF) into DR. */
SPI_DR(spi) = data;
@@ -229,7 +229,7 @@ finished.
@param[in] data Unsigned int16. 8 or 16 bit data to be written.
*/
void spi_send(u32 spi, u16 data)
void spi_send(uint32_t spi, uint16_t data)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_TXE));
@@ -247,7 +247,7 @@ Data is read from the SPI interface after the incoming transfer has finished.
@returns data Unsigned int16. 8 or 16 bit data.
*/
u16 spi_read(u32 spi)
uint16_t spi_read(uint32_t spi)
{
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_RXNE));
@@ -267,7 +267,7 @@ transfer has finished.
@returns data Unsigned int16. 8 or 16 bit data.
*/
u16 spi_xfer(u32 spi, u16 data)
uint16_t spi_xfer(uint32_t spi, uint16_t data)
{
spi_write(spi, data);
@@ -287,7 +287,7 @@ The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_mode(u32 spi)
void spi_set_bidirectional_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
}
@@ -302,7 +302,7 @@ clock wire and a unidirectional data wire.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_unidirectional_mode(u32 spi)
void spi_set_unidirectional_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
}
@@ -317,7 +317,7 @@ state.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_receive_only_mode(u32 spi)
void spi_set_bidirectional_receive_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
@@ -333,7 +333,7 @@ state.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_bidirectional_transmit_only_mode(u32 spi)
void spi_set_bidirectional_transmit_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
SPI_CR1(spi) |= SPI_CR1_BIDIOE;
@@ -347,7 +347,7 @@ The SPI peripheral is set to use a CRC field for transmit and receive.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_crc(u32 spi)
void spi_enable_crc(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CRCEN;
}
@@ -358,7 +358,7 @@ void spi_enable_crc(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_crc(u32 spi)
void spi_disable_crc(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
}
@@ -373,7 +373,7 @@ of a data or CRC word.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_next_tx_from_buffer(u32 spi)
void spi_set_next_tx_from_buffer(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
}
@@ -388,7 +388,7 @@ of a data or CRC word.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_next_tx_from_crc(u32 spi)
void spi_set_next_tx_from_crc(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
}
@@ -399,7 +399,7 @@ void spi_set_next_tx_from_crc(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_dff_8bit(u32 spi)
void spi_set_dff_8bit(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_DFF;
}
@@ -410,7 +410,7 @@ void spi_set_dff_8bit(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_dff_16bit(u32 spi)
void spi_set_dff_16bit(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_DFF;
}
@@ -421,7 +421,7 @@ void spi_set_dff_16bit(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_full_duplex_mode(u32 spi)
void spi_set_full_duplex_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
}
@@ -433,7 +433,7 @@ Transfers
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_receive_only_mode(u32 spi)
void spi_set_receive_only_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_RXONLY;
}
@@ -446,7 +446,7 @@ In slave mode the NSS hardware input is used as a select enable for the slave.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_software_slave_management(u32 spi)
void spi_disable_software_slave_management(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_SSM;
}
@@ -460,7 +460,7 @@ enable/disable of the slave (@ref spi_set_nss_high).
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_software_slave_management(u32 spi)
void spi_enable_software_slave_management(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SSM;
}
@@ -477,7 +477,7 @@ otherwise
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_nss_high(u32 spi)
void spi_set_nss_high(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_SSI;
}
@@ -491,7 +491,7 @@ the NSS signal with a slave select disable signal.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_nss_low(u32 spi)
void spi_set_nss_low(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_SSI;
}
@@ -502,7 +502,7 @@ void spi_set_nss_low(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_send_lsb_first(u32 spi)
void spi_send_lsb_first(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_LSBFIRST;
}
@@ -513,7 +513,7 @@ void spi_send_lsb_first(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_send_msb_first(u32 spi)
void spi_send_msb_first(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
}
@@ -528,9 +528,9 @@ values?
@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
*/
void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate)
{
u32 reg32;
uint32_t reg32;
if (baudrate > 7) {
return;
@@ -547,7 +547,7 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_master_mode(u32 spi)
void spi_set_master_mode(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_MSTR;
}
@@ -558,7 +558,7 @@ void spi_set_master_mode(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_slave_mode(u32 spi)
void spi_set_slave_mode(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_MSTR;
}
@@ -569,7 +569,7 @@ void spi_set_slave_mode(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_polarity_1(u32 spi)
void spi_set_clock_polarity_1(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CPOL;
}
@@ -580,7 +580,7 @@ void spi_set_clock_polarity_1(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_polarity_0(u32 spi)
void spi_set_clock_polarity_0(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CPOL;
}
@@ -591,7 +591,7 @@ void spi_set_clock_polarity_0(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_phase_1(u32 spi)
void spi_set_clock_phase_1(uint32_t spi)
{
SPI_CR1(spi) |= SPI_CR1_CPHA;
}
@@ -602,7 +602,7 @@ void spi_set_clock_phase_1(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_clock_phase_0(u32 spi)
void spi_set_clock_phase_0(uint32_t spi)
{
SPI_CR1(spi) &= ~SPI_CR1_CPHA;
}
@@ -613,7 +613,7 @@ void spi_set_clock_phase_0(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_tx_buffer_empty_interrupt(u32 spi)
void spi_enable_tx_buffer_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_TXEIE;
}
@@ -624,7 +624,7 @@ void spi_enable_tx_buffer_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_tx_buffer_empty_interrupt(u32 spi)
void spi_disable_tx_buffer_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
}
@@ -635,7 +635,7 @@ void spi_disable_tx_buffer_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_RXNEIE;
}
@@ -646,7 +646,7 @@ void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
}
@@ -657,7 +657,7 @@ void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_error_interrupt(u32 spi)
void spi_enable_error_interrupt(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_ERRIE;
}
@@ -668,7 +668,7 @@ void spi_enable_error_interrupt(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_error_interrupt(u32 spi)
void spi_disable_error_interrupt(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
}
@@ -682,7 +682,7 @@ SPI bus into slave mode. Multimaster mode is not possible.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_ss_output(u32 spi)
void spi_enable_ss_output(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_SSOE;
}
@@ -697,7 +697,7 @@ becomes a slave enable.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_ss_output(u32 spi)
void spi_disable_ss_output(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_SSOE;
}
@@ -712,7 +712,7 @@ SPI peripheral are given in the Technical Manual DMA section.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_tx_dma(u32 spi)
void spi_enable_tx_dma(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
}
@@ -723,7 +723,7 @@ void spi_enable_tx_dma(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_tx_dma(u32 spi)
void spi_disable_tx_dma(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
}
@@ -738,7 +738,7 @@ for each SPI peripheral are given in the Technical Manual DMA section.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_enable_rx_dma(u32 spi)
void spi_enable_rx_dma(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
}
@@ -749,7 +749,7 @@ void spi_enable_rx_dma(u32 spi)
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_disable_rx_dma(u32 spi)
void spi_disable_rx_dma(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN;
}

156
lib/stm32/common/timer_common_all.c
View File

@@ -113,7 +113,7 @@ reset condition. The reset is effected via the RCC peripheral reset system.
tim_reg_base (TIM9 .. TIM14 not yet supported here).
*/
void timer_reset(u32 timer_peripheral)
void timer_reset(uint32_t timer_peripheral)
{
switch (timer_peripheral) {
#if defined(TIM1_BASE)
@@ -198,7 +198,7 @@ tim_reg_base
enable bits to be set
*/
void timer_enable_irq(u32 timer_peripheral, u32 irq)
void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq)
{
TIM_DIER(timer_peripheral) |= irq;
}
@@ -212,7 +212,7 @@ tim_reg_base
enable bits to be cleared
*/
void timer_disable_irq(u32 timer_peripheral, u32 irq)
void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq)
{
TIM_DIER(timer_peripheral) &= ~irq;
}
@@ -233,7 +233,7 @@ tim_reg_base
@returns boolean: flag set.
*/
bool timer_interrupt_source(u32 timer_peripheral, u32 flag)
bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag)
{
/* flag not set or interrupt disabled or not an interrupt source */
if (((TIM_SR(timer_peripheral) &
@@ -259,7 +259,7 @@ tim_reg_base
@returns boolean: flag set.
*/
bool timer_get_flag(u32 timer_peripheral, u32 flag)
bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag)
{
if ((TIM_SR(timer_peripheral) & flag) != 0) {
return true;
@@ -276,7 +276,7 @@ tim_reg_base
@param[in] flag Unsigned int32. @ref tim_sr_values. Status register flag.
*/
void timer_clear_flag(u32 timer_peripheral, u32 flag)
void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag)
{
TIM_SR(timer_peripheral) &= ~flag;
}
@@ -309,10 +309,10 @@ tim_x_cr1_cdr
tim_x_cr1_dir
*/
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
u32 alignment, u32 direction)
void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div,
uint32_t alignment, uint32_t direction)
{
u32 cr1;
uint32_t cr1;
cr1 = TIM_CR1(timer_peripheral);
@@ -335,7 +335,7 @@ tim_reg_base
tim_x_cr1_cdr
*/
void timer_set_clock_division(u32 timer_peripheral, u32 clock_div)
void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div)
{
clock_div &= TIM_CR1_CKD_CK_INT_MASK;
TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK;
@@ -352,7 +352,7 @@ auto-reload register only at the next update event.
tim_reg_base
*/
void timer_enable_preload(u32 timer_peripheral)
void timer_enable_preload(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE;
}
@@ -368,7 +368,7 @@ current count cycle rather than for the cycle following an update event.
tim_reg_base
*/
void timer_disable_preload(u32 timer_peripheral)
void timer_disable_preload(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE;
}
@@ -383,7 +383,7 @@ tim_reg_base
@param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms
*/
void timer_set_alignment(u32 timer_peripheral, u32 alignment)
void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment)
{
alignment &= TIM_CR1_CMS_MASK;
TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK;
@@ -399,7 +399,7 @@ This has no effect if the timer is set to center aligned.
tim_reg_base
*/
void timer_direction_up(u32 timer_peripheral)
void timer_direction_up(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN;
}
@@ -413,7 +413,7 @@ This has no effect if the timer is set to center aligned.
tim_reg_base
*/
void timer_direction_down(u32 timer_peripheral)
void timer_direction_down(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN;
}
@@ -425,7 +425,7 @@ void timer_direction_down(u32 timer_peripheral)
tim_reg_base
*/
void timer_one_shot_mode(u32 timer_peripheral)
void timer_one_shot_mode(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_OPM;
}
@@ -437,7 +437,7 @@ void timer_one_shot_mode(u32 timer_peripheral)
tim_reg_base
*/
void timer_continuous_mode(u32 timer_peripheral)
void timer_continuous_mode(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM;
}
@@ -454,7 +454,7 @@ The events which will generate an interrupt or DMA request can be
tim_reg_base
*/
void timer_update_on_any(u32 timer_peripheral)
void timer_update_on_any(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS;
}
@@ -467,7 +467,7 @@ Events.
tim_reg_base
*/
void timer_update_on_overflow(u32 timer_peripheral)
void timer_update_on_overflow(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_URS;
}
@@ -479,7 +479,7 @@ void timer_update_on_overflow(u32 timer_peripheral)
tim_reg_base
*/
void timer_enable_update_event(u32 timer_peripheral)
void timer_enable_update_event(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS;
}
@@ -493,7 +493,7 @@ Update events are not generated and the shadow registers keep their values.
tim_reg_base
*/
void timer_disable_update_event(u32 timer_peripheral)
void timer_disable_update_event(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS;
}
@@ -507,7 +507,7 @@ This should be called after the timer initial configuration has been completed.
tim_reg_base
*/
void timer_enable_counter(u32 timer_peripheral)
void timer_enable_counter(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) |= TIM_CR1_CEN;
}
@@ -519,7 +519,7 @@ void timer_enable_counter(u32 timer_peripheral)
tim_reg_base
*/
void timer_disable_counter(u32 timer_peripheral)
void timer_disable_counter(uint32_t timer_peripheral)
{
TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN;
}
@@ -540,7 +540,7 @@ tim_x_cr2_ois. If several settings are to be made, use the logical OR of the
output control values.
*/
void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs)
void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -567,7 +567,7 @@ tim_reg_base
tim_x_cr2_ois
*/
void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs)
void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -589,7 +589,7 @@ input channels 1, 2, 3.
tim_reg_base
*/
void timer_set_ti1_ch123_xor(u32 timer_peripheral)
void timer_set_ti1_ch123_xor(uint32_t timer_peripheral)
{
TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S;
}
@@ -603,7 +603,7 @@ The first timer capture input is taken from the timer input channel 1 only.
tim_reg_base
*/
void timer_set_ti1_ch1(u32 timer_peripheral)
void timer_set_ti1_ch1(uint32_t timer_peripheral)
{
TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S;
}
@@ -619,7 +619,7 @@ tim_reg_base
@param[in] mode Unsigned int32. Master Mode @ref tim_mastermode
*/
void timer_set_master_mode(u32 timer_peripheral, u32 mode)
void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode)
{
TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK;
TIM_CR2(timer_peripheral) |= mode;
@@ -634,7 +634,7 @@ Capture/compare events will cause DMA requests to be generated.
tim_reg_base
*/
void timer_set_dma_on_compare_event(u32 timer_peripheral)
void timer_set_dma_on_compare_event(uint32_t timer_peripheral)
{
TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS;
}
@@ -648,7 +648,7 @@ Update events will cause DMA requests to be generated.
tim_reg_base
*/
void timer_set_dma_on_update_event(u32 timer_peripheral)
void timer_set_dma_on_update_event(uint32_t timer_peripheral)
{
TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS;
}
@@ -667,7 +667,7 @@ complementary outputs.
tim_reg_base
*/
void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral)
void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -692,7 +692,7 @@ complementary outputs.
tim_reg_base
*/
void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral)
void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -716,7 +716,7 @@ complementary outputs.
tim_reg_base
*/
void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral)
void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -739,7 +739,7 @@ complementary outputs.
tim_reg_base
*/
void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral)
void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -760,7 +760,7 @@ tim_reg_base
@param[in] value Unsigned int32. Prescaler values 0...0xFFFF.
*/
void timer_set_prescaler(u32 timer_peripheral, u32 value)
void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value)
{
TIM_PSC(timer_peripheral) = value;
}
@@ -778,7 +778,7 @@ tim_reg_base
@param[in] value Unsigned int32. Repetition values 0...0xFF.
*/
void timer_set_repetition_counter(u32 timer_peripheral, u32 value)
void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -800,7 +800,7 @@ tim_reg_base
@param[in] period Unsigned int32. Period in counter clock ticks.
*/
void timer_set_period(u32 timer_peripheral, u32 period)
void timer_set_period(uint32_t timer_peripheral, uint32_t period)
{
TIM_ARR(timer_peripheral) = period;
}
@@ -819,7 +819,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -853,7 +853,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -892,7 +892,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -927,7 +927,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -977,7 +977,7 @@ tim_reg_base
TIM_OCM_PWM1, TIM_OCM_PWM2
*/
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
enum tim_oc_mode oc_mode)
{
switch (oc_id) {
@@ -1126,7 +1126,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken)
*/
void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1158,7 +1158,7 @@ tim_reg_base
TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action)
*/
void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1193,7 +1193,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1255,7 +1255,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1317,7 +1317,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1379,7 +1379,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
switch (oc_id) {
case TIM_OC1:
@@ -1444,7 +1444,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
/* Acting for TIM1 and TIM8 only. */
@@ -1496,7 +1496,7 @@ tim_reg_base
timers 1 and 8)
*/
void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id)
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
/* Acting for TIM1 and TIM8 only. */
@@ -1546,7 +1546,7 @@ to the compare register.
@param[in] value Unsigned int32. Compare value.
*/
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value)
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value)
{
switch (oc_id) {
case TIM_OC1:
@@ -1585,7 +1585,7 @@ timer <b>even if break or deadtime features are not being used</b>.
TIM8
*/
void timer_enable_break_main_output(u32 timer_peripheral)
void timer_enable_break_main_output(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1608,7 +1608,7 @@ the Master Output Enable in the Break and Deadtime Register.
TIM8
*/
void timer_disable_break_main_output(u32 timer_peripheral)
void timer_disable_break_main_output(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1632,7 +1632,7 @@ break event.
TIM8
*/
void timer_enable_break_automatic_output(u32 timer_peripheral)
void timer_enable_break_automatic_output(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1656,7 +1656,7 @@ break event.
TIM8
*/
void timer_disable_break_automatic_output(u32 timer_peripheral)
void timer_disable_break_automatic_output(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1678,7 +1678,7 @@ Sets the break function to activate when the break input becomes high.
TIM8
*/
void timer_set_break_polarity_high(u32 timer_peripheral)
void timer_set_break_polarity_high(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1700,7 +1700,7 @@ Sets the break function to activate when the break input becomes low.
TIM8
*/
void timer_set_break_polarity_low(u32 timer_peripheral)
void timer_set_break_polarity_low(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1722,7 +1722,7 @@ Enables the break function of an advanced timer.
TIM8
*/
void timer_enable_break(u32 timer_peripheral)
void timer_enable_break(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1744,7 +1744,7 @@ Disables the break function of an advanced timer.
TIM8
*/
void timer_disable_break(u32 timer_peripheral)
void timer_disable_break(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1770,7 +1770,7 @@ inactive level as defined by the output polarity.
TIM8
*/
void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral)
void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1795,7 +1795,7 @@ disabled, the output is also disabled.
TIM8
*/
void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral)
void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1819,7 +1819,7 @@ inactive level as defined by the output polarity.
TIM8
*/
void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral)
void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1842,7 +1842,7 @@ timer. When the master output is disabled the output is also disabled.
TIM8
*/
void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral)
void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1867,7 +1867,7 @@ TIM8
@param[in] lock Unsigned int32. Lock specification @ref tim_lock
*/
void timer_set_break_lock(u32 timer_peripheral, u32 lock)
void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1899,7 +1899,7 @@ TIM8
above.
*/
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime)
void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime)
{
#if (defined(TIM1_BASE) || defined(TIM8_BASE))
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) {
@@ -1924,7 +1924,7 @@ generated.
@param[in] event Unsigned int32. Event specification @ref tim_event_gen
*/
void timer_generate_event(u32 timer_peripheral, u32 event)
void timer_generate_event(uint32_t timer_peripheral, uint32_t event)
{
TIM_EGR(timer_peripheral) |= event;
}
@@ -1938,7 +1938,7 @@ Read back the value of a timer's counter register contents
@returns Unsigned int32. Counter value.
*/
u32 timer_get_counter(u32 timer_peripheral)
uint32_t timer_get_counter(uint32_t timer_peripheral)
{
return TIM_CNT(timer_peripheral);
}
@@ -1952,7 +1952,7 @@ Set the value of a timer's counter register contents.
@param[in] count Unsigned int32. Counter value.
*/
void timer_set_counter(u32 timer_peripheral, u32 count)
void timer_set_counter(uint32_t timer_peripheral, uint32_t count)
{
TIM_CNT(timer_peripheral) = count;
}
@@ -1971,7 +1971,7 @@ valid.
@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
*/
void timer_ic_set_filter(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_filter(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_filter flt)
{
switch (ic) {
@@ -2004,7 +2004,7 @@ Set the number of events between each capture.
@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
*/
void timer_ic_set_prescaler(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_prescaler(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_psc psc)
{
switch (ic) {
@@ -2048,7 +2048,7 @@ internal trigger input selected through TS bit
@param[in] in ::tim_ic_input. Input Capture channel direction and source input.
*/
void timer_ic_set_input(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_input(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_input in)
{
in &= 3;
@@ -2086,7 +2086,7 @@ void timer_ic_set_input(u32 timer_peripheral, enum tim_ic_id ic,
@param[in] ic ::tim_ic_id. Input Capture channel designator.
*/
void timer_ic_enable(u32 timer_peripheral, enum tim_ic_id ic)
void timer_ic_enable(uint32_t timer_peripheral, enum tim_ic_id ic)
{
TIM_CCER(timer_peripheral) |= (0x1 << (ic * 4));
}
@@ -2098,7 +2098,7 @@ void timer_ic_enable(u32 timer_peripheral, enum tim_ic_id ic)
@param[in] ic ::tim_ic_id. Input Capture channel designator.
*/
void timer_ic_disable(u32 timer_peripheral, enum tim_ic_id ic)
void timer_ic_disable(uint32_t timer_peripheral, enum tim_ic_id ic)
{
TIM_CCER(timer_peripheral) &= ~(0x1 << (ic * 4));
}
@@ -2116,7 +2116,7 @@ valid.
@param[in] flt ::tim_ic_filter. Input Capture Filter identifier.
*/
void timer_slave_set_filter(u32 timer_peripheral, enum tim_ic_filter flt)
void timer_slave_set_filter(uint32_t timer_peripheral, enum tim_ic_filter flt)
{
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETF_MASK;
TIM_SMCR(timer_peripheral) |= flt << 8;
@@ -2131,7 +2131,7 @@ Set the external trigger frequency division ratio.
@param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler.
*/
void timer_slave_set_prescaler(u32 timer_peripheral, enum tim_ic_psc psc)
void timer_slave_set_prescaler(uint32_t timer_peripheral, enum tim_ic_psc psc)
{
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETPS_MASK;
TIM_SMCR(timer_peripheral) |= psc << 12;
@@ -2144,7 +2144,7 @@ void timer_slave_set_prescaler(u32 timer_peripheral, enum tim_ic_psc psc)
@param[in] pol ::tim_et_pol. Slave External Trigger polarity.
*/
void timer_slave_set_polarity(u32 timer_peripheral, enum tim_et_pol pol)
void timer_slave_set_polarity(uint32_t timer_peripheral, enum tim_et_pol pol)
{
if (pol) {
TIM_SMCR(timer_peripheral) |= TIM_SMCR_ETP;
@@ -2160,7 +2160,7 @@ void timer_slave_set_polarity(u32 timer_peripheral, enum tim_et_pol pol)
@param[in] mode Unsigned int8. Slave mode @ref tim_sms
*/
void timer_slave_set_mode(u32 timer_peripheral, u8 mode)
void timer_slave_set_mode(uint32_t timer_peripheral, uint8_t mode)
{
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_SMS_MASK;
TIM_SMCR(timer_peripheral) |= mode;
@@ -2173,7 +2173,7 @@ void timer_slave_set_mode(u32 timer_peripheral, u8 mode)
@param[in] trigger Unsigned int8. Slave trigger source @ref tim_ts
*/
void timer_slave_set_trigger(u32 timer_peripheral, u8 trigger)
void timer_slave_set_trigger(uint32_t timer_peripheral, uint8_t trigger)
{
TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_TS_MASK;
TIM_SMCR(timer_peripheral) |= trigger;

4
lib/stm32/common/timer_common_f24.c
View File

@@ -37,7 +37,7 @@ and similarly for TIM5 for oscillator calibration purposes.
@ref tim5_opt_trigger_remap.
*/
void timer_set_option(u32 timer_peripheral, u32 option)
void timer_set_option(uint32_t timer_peripheral, uint32_t option)
{
if (timer_peripheral == TIM2) {
TIM_OR(timer_peripheral) &= ~TIM2_OR_ITR1_RMP_MASK;
@@ -58,7 +58,7 @@ The timer channel must be set to input capture mode.
@param[in] pol ::tim_ic_pol. Input Capture polarity control.
*/
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_pol pol)
{
/* Clear CCxP and CCxNP to zero. For both edge trigger both fields are

64
lib/stm32/common/usart_common_all.c
View File

@@ -46,9 +46,9 @@ usart_reg_base
@param[in] baud unsigned 32 bit. Baud rate specified in Hz.
*/
void usart_set_baudrate(u32 usart, u32 baud)
void usart_set_baudrate(uint32_t usart, uint32_t baud)
{
u32 clock = rcc_ppre1_frequency;
uint32_t clock = rcc_ppre1_frequency;
#if defined STM32F2 || defined STM32F4
if ((usart == USART1) ||
@@ -85,7 +85,7 @@ usart_reg_base
@param[in] bits unsigned 32 bit. Word length in bits 8 or 9.
*/
void usart_set_databits(u32 usart, u32 bits)
void usart_set_databits(uint32_t usart, uint32_t bits)
{
if (bits == 8) {
USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */
@@ -104,9 +104,9 @@ usart_reg_base
@param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits.
*/
void usart_set_stopbits(u32 usart, u32 stopbits)
void usart_set_stopbits(uint32_t usart, uint32_t stopbits)
{
u32 reg32;
uint32_t reg32;
reg32 = USART_CR2(usart);
reg32 = (reg32 & ~USART_CR2_STOPBITS_MASK) | stopbits;
@@ -123,9 +123,9 @@ usart_reg_base
@param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity.
*/
void usart_set_parity(u32 usart, u32 parity)
void usart_set_parity(uint32_t usart, uint32_t parity)
{
u32 reg32;
uint32_t reg32;
reg32 = USART_CR1(usart);
reg32 = (reg32 & ~USART_PARITY_MASK) | parity;
@@ -142,9 +142,9 @@ usart_reg_base
@param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode.
*/
void usart_set_mode(u32 usart, u32 mode)
void usart_set_mode(uint32_t usart, uint32_t mode)
{
u32 reg32;
uint32_t reg32;
reg32 = USART_CR1(usart);
reg32 = (reg32 & ~USART_MODE_MASK) | mode;
@@ -161,9 +161,9 @@ usart_reg_base
@param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol.
*/
void usart_set_flow_control(u32 usart, u32 flowcontrol)
void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol)
{
u32 reg32;
uint32_t reg32;
reg32 = USART_CR3(usart);
reg32 = (reg32 & ~USART_FLOWCONTROL_MASK) | flowcontrol;
@@ -177,7 +177,7 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol)
usart_reg_base
*/
void usart_enable(u32 usart)
void usart_enable(uint32_t usart)
{
USART_CR1(usart) |= USART_CR1_UE;
}
@@ -191,7 +191,7 @@ At the end of the current frame, the USART is disabled to reduce power.
usart_reg_base
*/
void usart_disable(u32 usart)
void usart_disable(uint32_t usart)
{
USART_CR1(usart) &= ~USART_CR1_UE;
}
@@ -204,7 +204,7 @@ usart_reg_base
@param[in] data unsigned 16 bit.
*/
void usart_send(u32 usart, u16 data)
void usart_send(uint32_t usart, uint16_t data)
{
/* Send data. */
USART_DR(usart) = (data & USART_DR_MASK);
@@ -221,7 +221,7 @@ usart_reg_base
@returns unsigned 16 bit data word.
*/
u16 usart_recv(u32 usart)
uint16_t usart_recv(uint32_t usart)
{
/* Receive data. */
return USART_DR(usart) & USART_DR_MASK;
@@ -237,7 +237,7 @@ next data word.
usart_reg_base
*/
void usart_wait_send_ready(u32 usart)
void usart_wait_send_ready(uint32_t usart)
{
/* Wait until the data has been transferred into the shift register. */
while ((USART_SR(usart) & USART_SR_TXE) == 0);
@@ -252,7 +252,7 @@ Blocks until the receive data buffer holds a valid received data word.
usart_reg_base
*/
void usart_wait_recv_ready(u32 usart)
void usart_wait_recv_ready(uint32_t usart)
{
/* Wait until the data is ready to be received. */
while ((USART_SR(usart) & USART_SR_RXNE) == 0);
@@ -269,7 +269,7 @@ usart_reg_base
@param[in] data unsigned 16 bit.
*/
void usart_send_blocking(u32 usart, u16 data)
void usart_send_blocking(uint32_t usart, uint16_t data)
{
usart_wait_send_ready(usart);
usart_send(usart, data);
@@ -285,7 +285,7 @@ usart_reg_base
@returns unsigned 16 bit data word.
*/
u16 usart_recv_blocking(u32 usart)
uint16_t usart_recv_blocking(uint32_t usart)
{
usart_wait_recv_ready(usart);
@@ -305,7 +305,7 @@ DMA is available on:
usart_reg_base
*/
void usart_enable_rx_dma(u32 usart)
void usart_enable_rx_dma(uint32_t usart)
{
USART_CR3(usart) |= USART_CR3_DMAR;
}
@@ -317,7 +317,7 @@ void usart_enable_rx_dma(u32 usart)
usart_reg_base
*/
void usart_disable_rx_dma(u32 usart)
void usart_disable_rx_dma(uint32_t usart)
{
USART_CR3(usart) &= ~USART_CR3_DMAR;
}
@@ -335,7 +335,7 @@ DMA is available on:
usart_reg_base
*/
void usart_enable_tx_dma(u32 usart)
void usart_enable_tx_dma(uint32_t usart)
{
USART_CR3(usart) |= USART_CR3_DMAT;
}
@@ -347,7 +347,7 @@ void usart_enable_tx_dma(u32 usart)
usart_reg_base
*/
void usart_disable_tx_dma(u32 usart)
void usart_disable_tx_dma(uint32_t usart)
{
USART_CR3(usart) &= ~USART_CR3_DMAT;
}
@@ -359,7 +359,7 @@ void usart_disable_tx_dma(u32 usart)
usart_reg_base
*/
void usart_enable_rx_interrupt(u32 usart)
void usart_enable_rx_interrupt(uint32_t usart)
{
USART_CR1(usart) |= USART_CR1_RXNEIE;
}
@@ -372,7 +372,7 @@ void usart_enable_rx_interrupt(u32 usart)
usart_reg_base
*/
void usart_disable_rx_interrupt(u32 usart)
void usart_disable_rx_interrupt(uint32_t usart)
{
USART_CR1(usart) &= ~USART_CR1_RXNEIE;
}
@@ -384,7 +384,7 @@ void usart_disable_rx_interrupt(u32 usart)
usart_reg_base
*/
void usart_enable_tx_interrupt(u32 usart)
void usart_enable_tx_interrupt(uint32_t usart)
{
USART_CR1(usart) |= USART_CR1_TXEIE;
}
@@ -396,7 +396,7 @@ void usart_enable_tx_interrupt(u32 usart)
usart_reg_base
*/
void usart_disable_tx_interrupt(u32 usart)
void usart_disable_tx_interrupt(uint32_t usart)
{
USART_CR1(usart) &= ~USART_CR1_TXEIE;
}
@@ -408,7 +408,7 @@ void usart_disable_tx_interrupt(u32 usart)
usart_reg_base
*/
void usart_enable_error_interrupt(u32 usart)
void usart_enable_error_interrupt(uint32_t usart)
{
USART_CR3(usart) |= USART_CR3_EIE;
}
@@ -420,7 +420,7 @@ void usart_enable_error_interrupt(u32 usart)
usart_reg_base
*/
void usart_disable_error_interrupt(u32 usart)
void usart_disable_error_interrupt(uint32_t usart)
{
USART_CR3(usart) &= ~USART_CR3_EIE;
}
@@ -434,7 +434,7 @@ usart_reg_base
@returns boolean: flag set.
*/
bool usart_get_flag(u32 usart, u32 flag)
bool usart_get_flag(uint32_t usart, uint32_t flag)
{
return ((USART_SR(usart) & flag) != 0);
}
@@ -456,9 +456,9 @@ usart_reg_base
@returns boolean: flag and interrupt enable both set.
*/
bool usart_get_interrupt_source(u32 usart, u32 flag)
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag)
{
u32 flag_set = (USART_SR(usart) & flag);
uint32_t flag_set = (USART_SR(usart) & flag);
/* IDLE, RXNE, TC, TXE interrupts */
if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) {
return ((flag_set & USART_CR1(usart)) != 0);

16
lib/stm32/desig.c
View File

@@ -19,19 +19,19 @@
#include <libopencm3/stm32/desig.h>
u16 desig_get_flash_size(void)
uint16_t desig_get_flash_size(void)
{
return DESIG_FLASH_SIZE;
}
void desig_get_unique_id(u32 result[])
void desig_get_unique_id(uint32_t result[])
{
/* Could also just return a pointer to the start? read it as they wish?
*/
u16 bits15_0 = DESIG_UID_15_0;
u32 bits31_16 = DESIG_UID_31_16;
u32 bits63_32 = DESIG_UID_63_32;
u32 bits95_64 = DESIG_UID_95_64;
uint16_t bits15_0 = DESIG_UID_15_0;
uint32_t bits31_16 = DESIG_UID_31_16;
uint32_t bits63_32 = DESIG_UID_63_32;
uint32_t bits95_64 = DESIG_UID_95_64;
result[0] = bits95_64;
result[1] = bits63_32;
result[2] = bits31_16 << 16 | bits15_0;
@@ -41,10 +41,10 @@ void desig_get_unique_id_as_string(char *string,
unsigned int string_len)
{
int i, len;
u8 device_id[12];
uint8_t device_id[12];
static const char chars[] = "0123456789ABCDEF";
desig_get_unique_id((u32 *)device_id);
desig_get_unique_id((uint32_t *)device_id);
/* Each byte produces two characters */
len = (2 * sizeof(device_id) < string_len) ?

14
lib/stm32/exti2.c
View File

@@ -33,7 +33,7 @@
#error "invalid/unknown stm32 family for this code"
#endif
void exti_set_trigger(u32 extis, exti_trigger_type trig)
void exti_set_trigger(uint32_t extis, exti_trigger_type trig)
{
switch (trig) {
case EXTI_TRIGGER_RISING:
@@ -51,7 +51,7 @@ void exti_set_trigger(u32 extis, exti_trigger_type trig)
}
}
void exti_enable_request(u32 extis)
void exti_enable_request(uint32_t extis)
{
/* Enable interrupts. */
EXTI_IMR |= extis;
@@ -60,7 +60,7 @@ void exti_enable_request(u32 extis)
EXTI_EMR |= extis;
}
void exti_disable_request(u32 extis)
void exti_disable_request(uint32_t extis)
{
/* Disable interrupts. */
EXTI_IMR &= ~extis;
@@ -73,7 +73,7 @@ void exti_disable_request(u32 extis)
* Reset the interrupt request by writing a 1 to the corresponding
* pending bit register.
*/
void exti_reset_request(u32 extis)
void exti_reset_request(uint32_t extis)
{
EXTI_PR = extis;
}
@@ -81,7 +81,7 @@ void exti_reset_request(u32 extis)
/*
* Check the flag of a given EXTI interrupt.
* */
u32 exti_get_flag_status(u32 exti)
uint32_t exti_get_flag_status(uint32_t exti)
{
return EXTI_PR & exti;
}
@@ -92,9 +92,9 @@ u32 exti_get_flag_status(u32 exti)
*
* TODO: This could be rewritten in fewer lines of code.
*/
void exti_select_source(u32 exti, u32 gpioport)
void exti_select_source(uint32_t exti, uint32_t gpioport)
{
u8 shift, bits;
uint8_t shift, bits;
shift = bits = 0;

142
lib/stm32/f1/adc.c
View File

@@ -122,7 +122,7 @@ If the ADC is already on this function call has no effect.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_power_on(u32 adc)
void adc_power_on(uint32_t adc)
{
if (!(ADC_CR2(adc) & ADC_CR2_ADON)) {
ADC_CR2(adc) |= ADC_CR2_ADON;
@@ -142,7 +142,7 @@ adc_start_conversion_regular.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_start_conversion_direct(u32 adc)
void adc_start_conversion_direct(uint32_t adc)
{
if (ADC_CR2(adc) & ADC_CR2_ADON) {
ADC_CR2(adc) |= ADC_CR2_ADON;
@@ -186,7 +186,7 @@ Dual A/D converter modes possible:
@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod
*/
void adc_set_dual_mode(u32 mode)
void adc_set_dual_mode(uint32_t mode)
{
ADC1_CR1 |= mode;
}
@@ -202,7 +202,7 @@ adc_reg_base.
@returns bool. End of conversion flag.
*/
bool adc_eoc(u32 adc)
bool adc_eoc(uint32_t adc)
{
return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
}
@@ -217,7 +217,7 @@ adc_reg_base.
@returns bool. End of conversion flag.
*/
bool adc_eoc_injected(u32 adc)
bool adc_eoc_injected(uint32_t adc)
{
return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
}
@@ -234,7 +234,7 @@ adc_reg_base.
@returns Unsigned int32 conversion result.
*/
u32 adc_read_regular(u32 adc)
uint32_t adc_read_regular(uint32_t adc)
{
return ADC_DR(adc);
}
@@ -253,7 +253,7 @@ adc_reg_base.
@returns Unsigned int32 conversion result.
*/
u32 adc_read_injected(u32 adc, u8 reg)
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
{
switch (reg) {
case 1:
@@ -281,7 +281,7 @@ adc_reg_base.
@param[in] offset Unsigned int32.
*/
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
{
switch (reg) {
case 1:
@@ -310,7 +310,7 @@ alignment takes place, so the thresholds are left-aligned.
adc_reg_base.
*/
void adc_enable_analog_watchdog_regular(u32 adc)
void adc_enable_analog_watchdog_regular(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDEN;
}
@@ -322,7 +322,7 @@ void adc_enable_analog_watchdog_regular(u32 adc)
adc_reg_base.
*/
void adc_disable_analog_watchdog_regular(u32 adc)
void adc_disable_analog_watchdog_regular(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
}
@@ -338,7 +338,7 @@ alignment takes place, so the thresholds are left-aligned.
adc_reg_base.
*/
void adc_enable_analog_watchdog_injected(u32 adc)
void adc_enable_analog_watchdog_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JAWDEN;
}
@@ -350,7 +350,7 @@ void adc_enable_analog_watchdog_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_analog_watchdog_injected(u32 adc)
void adc_disable_analog_watchdog_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
}
@@ -372,7 +372,7 @@ adc_reg_base.
adc_cr1_discnum.
*/
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
{
if ((length-1) > 7) {
return;
@@ -388,7 +388,7 @@ void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
adc_reg_base.
*/
void adc_disable_discontinuous_mode_regular(u32 adc)
void adc_disable_discontinuous_mode_regular(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
}
@@ -404,7 +404,7 @@ entire group has been converted.
adc_reg_base.
*/
void adc_enable_discontinuous_mode_injected(u32 adc)
void adc_enable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
}
@@ -416,7 +416,7 @@ void adc_enable_discontinuous_mode_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_discontinuous_mode_injected(u32 adc)
void adc_disable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
}
@@ -432,7 +432,7 @@ channels is disabled as required.
adc_reg_base
*/
void adc_enable_automatic_injected_group_conversion(u32 adc)
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
{
adc_disable_external_trigger_injected(adc);
ADC_CR1(adc) |= ADC_CR1_JAUTO;
@@ -445,7 +445,7 @@ void adc_enable_automatic_injected_group_conversion(u32 adc)
adc_reg_base.
*/
void adc_disable_automatic_injected_group_conversion(u32 adc)
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
}
@@ -467,7 +467,7 @@ adc_enable_analog_watchdog_regular.
adc_reg_base.
*/
void adc_enable_analog_watchdog_on_all_channels(u32 adc)
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
}
@@ -490,9 +490,9 @@ adc_reg_base.
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel.
*/
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */
if (channel < 18) {
@@ -513,7 +513,7 @@ previous one. It can use single, continuous or discontinuous mode.
adc_reg_base.
*/
void adc_enable_scan_mode(u32 adc)
void adc_enable_scan_mode(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_SCAN;
}
@@ -524,7 +524,7 @@ void adc_enable_scan_mode(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_scan_mode(u32 adc)
void adc_disable_scan_mode(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_SCAN;
}
@@ -536,7 +536,7 @@ void adc_disable_scan_mode(u32 adc)
adc_reg_base.
*/
void adc_enable_eoc_interrupt_injected(u32 adc)
void adc_enable_eoc_interrupt_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
}
@@ -548,7 +548,7 @@ void adc_enable_eoc_interrupt_injected(u32 adc)
adc_reg_base.
*/
void adc_disable_eoc_interrupt_injected(u32 adc)
void adc_disable_eoc_interrupt_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
}
@@ -560,7 +560,7 @@ void adc_disable_eoc_interrupt_injected(u32 adc)
adc_reg_base.
*/
void adc_enable_awd_interrupt(u32 adc)
void adc_enable_awd_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDIE;
}
@@ -572,7 +572,7 @@ void adc_enable_awd_interrupt(u32 adc)
adc_reg_base.
*/
void adc_disable_awd_interrupt(u32 adc)
void adc_disable_awd_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
}
@@ -584,7 +584,7 @@ void adc_disable_awd_interrupt(u32 adc)
adc_reg_base.
*/
void adc_enable_eoc_interrupt(u32 adc)
void adc_enable_eoc_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_EOCIE;
}
@@ -596,7 +596,7 @@ void adc_enable_eoc_interrupt(u32 adc)
adc_reg_base.
*/
void adc_disable_eoc_interrupt(u32 adc)
void adc_disable_eoc_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
}
@@ -611,7 +611,7 @@ This enables both the sensor and the reference voltage measurements on channels
adc_reg_base.
*/
void adc_enable_temperature_sensor(u32 adc)
void adc_enable_temperature_sensor(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_TSVREFE;
}
@@ -626,7 +626,7 @@ voltage measurements.
adc_reg_base.
*/
void adc_disable_temperature_sensor(u32 adc)
void adc_disable_temperature_sensor(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_TSVREFE;
}
@@ -646,7 +646,7 @@ This is not the same as the ADC start conversion operation.
adc_reg_base.
*/
void adc_start_conversion_regular(u32 adc)
void adc_start_conversion_regular(uint32_t adc)
{
/* Start conversion on regular channels. */
ADC_CR2(adc) |= ADC_CR2_SWSTART;
@@ -670,7 +670,7 @@ This is not the same as the ADC start conversion operation.
adc_reg_base.
*/
void adc_start_conversion_injected(u32 adc)
void adc_start_conversion_injected(uint32_t adc)
{
/* Start conversion on injected channels. */
ADC_CR2(adc) |= ADC_CR2_JSWSTART;
@@ -710,9 +710,9 @@ adc_reg_base.
for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3.
*/
void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK));
reg32 |= (trigger);
@@ -727,7 +727,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
adc_reg_base.
*/
void adc_disable_external_trigger_regular(u32 adc)
void adc_disable_external_trigger_regular(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG;
}
@@ -763,9 +763,9 @@ adc_reg_base.
adc_trigger_injected_12 for ADC1 and ADC2, or @ref adc_trigger_injected_3 for
ADC3.
*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]
*/
@@ -781,7 +781,7 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
adc_reg_base.
*/
void adc_disable_external_trigger_injected(u32 adc)
void adc_disable_external_trigger_injected(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG;
}
@@ -793,7 +793,7 @@ void adc_disable_external_trigger_injected(u32 adc)
adc_reg_base.
*/
void adc_set_left_aligned(u32 adc)
void adc_set_left_aligned(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_ALIGN;
}
@@ -805,7 +805,7 @@ void adc_set_left_aligned(u32 adc)
adc_reg_base.
*/
void adc_set_right_aligned(u32 adc)
void adc_set_right_aligned(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
}
@@ -821,7 +821,7 @@ mode.
adc_reg_base.
*/
void adc_enable_dma(u32 adc)
void adc_enable_dma(uint32_t adc)
{
if ((adc == ADC1) | (adc == ADC3)) {
ADC_CR2(adc) |= ADC_CR2_DMA;
@@ -835,7 +835,7 @@ void adc_enable_dma(u32 adc)
adc_reg_base.
*/
void adc_disable_dma(u32 adc)
void adc_disable_dma(uint32_t adc)
{
if ((adc == ADC1) | (adc == ADC3)) {
ADC_CR2(adc) &= ~ADC_CR2_DMA;
@@ -852,7 +852,7 @@ done before every calibration operation.
adc_reg_base.
*/
void adc_reset_calibration(u32 adc)
void adc_reset_calibration(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_RSTCAL;
while (ADC_CR2(adc) & ADC_CR2_RSTCAL);
@@ -872,7 +872,7 @@ powered on. before calibration starts
adc_reg_base.
*/
void adc_calibration(u32 adc)
void adc_calibration(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_CAL;
while (ADC_CR2(adc) & ADC_CR2_CAL);
@@ -888,7 +888,7 @@ group immediately following completion of the previous channel group conversion.
adc_reg_base.
*/
void adc_set_continuous_conversion_mode(u32 adc)
void adc_set_continuous_conversion_mode(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_CONT;
}
@@ -903,7 +903,7 @@ and stops.
adc_reg_base.
*/
void adc_set_single_conversion_mode(u32 adc)
void adc_set_single_conversion_mode(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_CONT;
}
@@ -921,7 +921,7 @@ If the ADC is already on this function call will initiate a conversion.
adc_reg_base.
*/
void adc_on(u32 adc)
void adc_on(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_ADON;
}
@@ -935,7 +935,7 @@ Turn off the ADC to reduce power consumption to a few microamps.
adc_reg_base.
*/
void adc_off(u32 adc)
void adc_off(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ADON;
}
@@ -952,9 +952,9 @@ adc_channel.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
*/
void adc_set_sample_time(u32 adc, u8 channel, u8 time)
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
{
u32 reg32;
uint32_t reg32;
if (channel < 10) {
reg32 = ADC_SMPR2(adc);
@@ -980,10 +980,10 @@ adc_reg_base.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg.
*/
void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
{
u8 i;
u32 reg32 = 0;
uint8_t i;
uint32_t reg32 = 0;
for (i = 0; i <= 9; i++) {
reg32 |= (time << (i * 3));
@@ -1004,11 +1004,11 @@ adc_reg_base.
@param[in] threshold Unsigned int8. Upper threshold value.
*/
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
{
u32 reg32 = 0;
uint32_t reg32 = 0;
reg32 = (u32)threshold;
reg32 = (uint32_t)threshold;
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_HTR(adc) = reg32;
}
@@ -1021,11 +1021,11 @@ adc_reg_base.
@param[in] threshold Unsigned int8. Lower threshold value.
*/
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
{
u32 reg32 = 0;
uint32_t reg32 = 0;
reg32 = (u32)threshold;
reg32 = (uint32_t)threshold;
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_LTR(adc) = reg32;
}
@@ -1044,10 +1044,10 @@ adc_reg_base.
0..18.
*/
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
u8 i = 0;
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
uint8_t i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16) {
@@ -1085,10 +1085,10 @@ adc_reg_base.
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
*/
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
u32 reg32 = 0;
u8 i = 0;
uint32_t reg32 = 0;
uint8_t i = 0;
/* Maximum sequence length is 4 channels. */
if (length > 4) {
@@ -1109,15 +1109,15 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
/* Aliases */
#ifdef __GNUC__
void adc_set_continous_conversion_mode(u32 adc)
void adc_set_continous_conversion_mode(uint32_t adc)
__attribute__((alias("adc_set_continuous_conversion_mode")));
void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time)
__attribute__((alias("adc_set_sample_time")));
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time)
__attribute__((alias("adc_set_sample_time_on_all_channels")));
void adc_enable_jeoc_interrupt(u32 adc)
void adc_enable_jeoc_interrupt(uint32_t adc)
__attribute__((alias("adc_enable_eoc_interrupt_injected")));
void adc_disable_jeoc_interrupt(u32 adc)
void adc_disable_jeoc_interrupt(uint32_t adc)
__attribute__((alias("adc_disable_eoc_interrupt_injected")));
#endif

6
lib/stm32/f1/ethernet.c
View File

@@ -19,7 +19,7 @@
#include <libopencm3/stm32/f1/ethernet.h>
void eth_smi_write(u8 phy, u8 reg, u16 data)
void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data)
{
/* Set PHY and register addresses for write access. */
ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA);
@@ -35,7 +35,7 @@ void eth_smi_write(u8 phy, u8 reg, u16 data)
while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
}
u16 eth_smi_read(u8 phy, u8 reg)
uint16_t eth_smi_read(uint8_t phy, uint8_t reg)
{
/* Set PHY and register addresses for write access. */
ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA | ETH_MACMIIAR_MW);
@@ -48,5 +48,5 @@ u16 eth_smi_read(u8 phy, u8 reg)
while (ETH_MACMIIAR & ETH_MACMIIAR_MB);
/* Set register value. */
return (u16)(ETH_MACMIIDR);
return (uint16_t)(ETH_MACMIIDR);
}

14
lib/stm32/f1/exti.c
View File

@@ -20,7 +20,7 @@
#include <libopencm3/stm32/exti.h>
#include <libopencm3/stm32/f1/gpio.h>
void exti_set_trigger(u32 extis, exti_trigger_type trig)
void exti_set_trigger(uint32_t extis, exti_trigger_type trig)
{
switch (trig) {
case EXTI_TRIGGER_RISING:
@@ -38,7 +38,7 @@ void exti_set_trigger(u32 extis, exti_trigger_type trig)
}
}
void exti_enable_request(u32 extis)
void exti_enable_request(uint32_t extis)
{
/* Enable interrupts. */
EXTI_IMR |= extis;
@@ -47,7 +47,7 @@ void exti_enable_request(u32 extis)
EXTI_EMR |= extis;
}
void exti_disable_request(u32 extis)
void exti_disable_request(uint32_t extis)
{
/* Disable interrupts. */
EXTI_IMR &= ~extis;
@@ -60,7 +60,7 @@ void exti_disable_request(u32 extis)
* Reset the interrupt request by writing a 1 to the corresponding
* pending bit register.
*/
void exti_reset_request(u32 extis)
void exti_reset_request(uint32_t extis)
{
EXTI_PR |= extis;
}
@@ -68,7 +68,7 @@ void exti_reset_request(u32 extis)
/*
* Check the flag of a given EXTI interrupt.
* */
u32 exti_get_flag_status(u32 exti)
uint32_t exti_get_flag_status(uint32_t exti)
{
return EXTI_PR & exti;
}
@@ -79,9 +79,9 @@ u32 exti_get_flag_status(u32 exti)
*
* TODO: This could be rewritten in fewer lines of code.
*/
void exti_select_source(u32 exti, u32 gpioport)
void exti_select_source(uint32_t exti, uint32_t gpioport)
{
u8 shift, bits;
uint8_t shift, bits;
shift = bits = 0;

22
lib/stm32/f1/flash.c
View File

@@ -40,9 +40,9 @@ void flash_halfcycle_disable(void)
FLASH_ACR &= ~FLASH_ACR_HLFCYA;
}
void flash_set_ws(u32 ws)
void flash_set_ws(uint32_t ws)
{
u32 reg32;
uint32_t reg32;
reg32 = FLASH_ACR;
reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
@@ -93,7 +93,7 @@ void flash_clear_status_flags(void)
flash_clear_bsy_flag();
}
u32 flash_get_status_flags(void)
uint32_t flash_get_status_flags(void)
{
return FLASH_SR &= (FLASH_SR_PGERR |
FLASH_SR_EOP |
@@ -113,7 +113,7 @@ void flash_wait_for_last_operation(void)
while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY);
}
void flash_program_word(u32 address, u32 data)
void flash_program_word(uint32_t address, uint32_t data)
{
/* Ensure that all flash operations are complete. */
flash_wait_for_last_operation();
@@ -122,13 +122,13 @@ void flash_program_word(u32 address, u32 data)
FLASH_CR |= FLASH_CR_PG;
/* Program the first half of the word. */
(*(volatile u16 *)address) = (u16)data;
(*(volatile uint16_t *)address) = (uint16_t)data;
/* Wait for the write to complete. */
flash_wait_for_last_operation();
/* Program the second half of the word. */
(*(volatile u16 *)(address + 2)) = data >> 16;
(*(volatile uint16_t *)(address + 2)) = data >> 16;
/* Wait for the write to complete. */
flash_wait_for_last_operation();
@@ -137,20 +137,20 @@ void flash_program_word(u32 address, u32 data)
FLASH_CR &= ~FLASH_CR_PG;
}
void flash_program_half_word(u32 address, u16 data)
void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
FLASH_CR |= FLASH_CR_PG;
(*(volatile u16 *)address) = data;
(*(volatile uint16_t *)address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
}
void flash_erase_page(u32 page_address)
void flash_erase_page(uint32_t page_address)
{
flash_wait_for_last_operation();
@@ -187,7 +187,7 @@ void flash_erase_option_bytes(void)
FLASH_CR &= ~FLASH_CR_OPTER; /* Disable option byte erase. */
}
void flash_program_option_bytes(u32 address, u16 data)
void flash_program_option_bytes(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
@@ -196,7 +196,7 @@ void flash_program_option_bytes(u32 address, u16 data)
}
FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */
(*(volatile u16 *)address) = data;
(*(volatile uint16_t *)address) = data;
flash_wait_for_last_operation();
FLASH_CR &= ~FLASH_CR_OPTPG; /* Disable option byte programming. */
}

12
lib/stm32/f1/gpio.c
View File

@@ -92,10 +92,10 @@ open drain/push pull), for a set of GPIO pins on a given GPIO port.
them.
*/
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint16_t gpios)
{
u16 i, offset = 0;
u32 crl = 0, crh = 0, tmp32 = 0;
uint16_t i, offset = 0;
uint32_t crl = 0, crh = 0, tmp32 = 0;
/*
* We want to set the config only for the pins mentioned in gpios,
@@ -138,7 +138,7 @@ Enable the EVENTOUT signal and select the port and pin to be used.
@param[in] evoutport Unsigned int8. Port for EVENTOUT signal @ref afio_evcr_port
@param[in] evoutpin Unsigned int8. Pin for EVENTOUT signal @ref afio_evcr_pin
*/
void gpio_set_eventout(u8 evoutport, u8 evoutpin)
void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin)
{
AFIO_EVCR = AFIO_EVCR_EVOE | evoutport | evoutpin;
}
@@ -166,7 +166,7 @@ afio_remap, @ref afio_remap_can1, @ref afio_remap_tim3, @ref afio_remap_tim2,
@ref afio_remap_tim1, @ref afio_remap_usart3. For connectivity line devices
only @ref afio_remap_cld are also available.
*/
void gpio_primary_remap(u32 swjdisable, u32 maps)
void gpio_primary_remap(uint32_t swjdisable, uint32_t maps)
{
AFIO_MAPR |= (swjdisable & AFIO_MAPR_SWJ_MASK) | (maps & 0x1FFFFF);
}
@@ -185,7 +185,7 @@ The AFIO remapping feature is used only with the STM32F10x series.
@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref
afio_remap2
*/
void gpio_secondary_remap(u32 maps)
void gpio_secondary_remap(uint32_t maps)
{
AFIO_MAPR2 |= maps;
}

74
lib/stm32/f1/rcc.c
View File

@@ -54,9 +54,9 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/f1/flash.h>
/** Default ppre1 peripheral clock frequency after reset. */
u32 rcc_ppre1_frequency = 8000000;
uint32_t rcc_ppre1_frequency = 8000000;
/** Default ppre2 peripheral clock frequency after reset. */
u32 rcc_ppre2_frequency = 8000000;
uint32_t rcc_ppre2_frequency = 8000000;
/*---------------------------------------------------------------------------*/
/** @brief RCC Clear the Oscillator Ready Interrupt Flag
@@ -435,7 +435,7 @@ if they are controlled by the same register</em>.
@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
*/
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg |= en;
}
@@ -457,7 +457,7 @@ disabling.
@li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en
*/
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg &= ~en;
}
@@ -478,7 +478,7 @@ they are controlled by the same register</em>.
@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
*/
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
{
*reg |= reset;
}
@@ -499,7 +499,7 @@ simultaneously <em>only if they are controlled by the same register</em>.
@li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
*/
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
{
*reg &= ~clear_reset;
}
@@ -510,9 +510,9 @@ void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
@param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs
*/
void rcc_set_sysclk_source(u32 clk)
void rcc_set_sysclk_source(uint32_t clk)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
@@ -527,9 +527,9 @@ void rcc_set_sysclk_source(u32 clk)
@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
*/
void rcc_set_pll_multiplication_factor(u32 mul)
void rcc_set_pll_multiplication_factor(uint32_t mul)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18));
@@ -544,9 +544,9 @@ void rcc_set_pll_multiplication_factor(u32 mul)
@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
*/
void rcc_set_pll2_multiplication_factor(u32 mul)
void rcc_set_pll2_multiplication_factor(uint32_t mul)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR2;
reg32 &= ~((1 << 11) | (1 << 10) | (1 << 9) | (1 << 8));
@@ -561,9 +561,9 @@ void rcc_set_pll2_multiplication_factor(u32 mul)
@param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
*/
void rcc_set_pll3_multiplication_factor(u32 mul)
void rcc_set_pll3_multiplication_factor(uint32_t mul)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR2;
reg32 &= ~((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12));
@@ -578,9 +578,9 @@ void rcc_set_pll3_multiplication_factor(u32 mul)
@param[in] pllsrc Unsigned int32. PLL clock source @ref rcc_cfgr_pcs
*/
void rcc_set_pll_source(u32 pllsrc)
void rcc_set_pll_source(uint32_t pllsrc)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(1 << 16);
@@ -595,9 +595,9 @@ void rcc_set_pll_source(u32 pllsrc)
@param[in] pllxtpre Unsigned int32. HSE division factor @ref rcc_cfgr_hsepre
*/
void rcc_set_pllxtpre(u32 pllxtpre)
void rcc_set_pllxtpre(uint32_t pllxtpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(1 << 17);
@@ -609,12 +609,12 @@ void rcc_set_pllxtpre(u32 pllxtpre)
The ADC's have a common clock prescale setting.
@param[in] adcpre u32. Prescale divider taken from @ref rcc_cfgr_adcpre
@param[in] adcpre uint32_t. Prescale divider taken from @ref rcc_cfgr_adcpre
*/
void rcc_set_adcpre(u32 adcpre)
void rcc_set_adcpre(uint32_t adcpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 14) | (1 << 15));
@@ -627,9 +627,9 @@ void rcc_set_adcpre(u32 adcpre)
@param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre
*/
void rcc_set_ppre2(u32 ppre2)
void rcc_set_ppre2(uint32_t ppre2)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 11) | (1 << 12) | (1 << 13));
@@ -644,9 +644,9 @@ void rcc_set_ppre2(u32 ppre2)
@param[in] ppre1 Unsigned int32. APB1 prescale factor @ref rcc_cfgr_apb1pre
*/
void rcc_set_ppre1(u32 ppre1)
void rcc_set_ppre1(uint32_t ppre1)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 8) | (1 << 9) | (1 << 10));
@@ -659,9 +659,9 @@ void rcc_set_ppre1(u32 ppre1)
@param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre
*/
void rcc_set_hpre(u32 hpre)
void rcc_set_hpre(uint32_t hpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
@@ -679,40 +679,40 @@ The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
@param[in] usbpre Unsigned int32. USB prescale factor @ref rcc_cfgr_usbpre
*/
void rcc_set_usbpre(u32 usbpre)
void rcc_set_usbpre(uint32_t usbpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(1 << 22);
RCC_CFGR = (reg32 | (usbpre << 22));
}
void rcc_set_prediv1(u32 prediv)
void rcc_set_prediv1(uint32_t prediv)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR2;
reg32 &= ~(1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
RCC_CFGR2 |= (reg32 | prediv);
}
void rcc_set_prediv2(u32 prediv)
void rcc_set_prediv2(uint32_t prediv)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR2;
reg32 &= ~(1 << 7) | (1 << 6) | (1 << 5) | (1 << 4);
RCC_CFGR2 |= (reg32 | (prediv << 4));
}
void rcc_set_prediv1_source(u32 rccsrc)
void rcc_set_prediv1_source(uint32_t rccsrc)
{
RCC_CFGR2 &= ~(1 << 16);
RCC_CFGR2 |= (rccsrc << 16);
}
void rcc_set_mco(u32 mcosrc)
void rcc_set_mco(uint32_t mcosrc)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24));
RCC_CFGR |= (reg32 | (mcosrc << 24));
@@ -727,7 +727,7 @@ void rcc_set_mco(u32 mcosrc)
@li 02 indicates PLL
*/
u32 rcc_system_clock_source(void)
uint32_t rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return (RCC_CFGR & 0x000c) >> 2;

28
lib/stm32/f1/rtc.c
View File

@@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
void rtc_awake_from_off(osc_t clock_source)
{
u32 reg32;
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);
@@ -106,7 +106,7 @@ void rtc_awake_from_off(osc_t clock_source)
void rtc_enter_config_mode(void)
{
u32 reg32;
uint32_t reg32;
/* Wait until the RTOFF bit is 1 (no RTC register writes ongoing). */
while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
@@ -117,7 +117,7 @@ void rtc_enter_config_mode(void)
void rtc_exit_config_mode(void)
{
u32 reg32;
uint32_t reg32;
/* Exit configuration mode. */
RTC_CRL &= ~RTC_CRL_CNF;
@@ -126,7 +126,7 @@ void rtc_exit_config_mode(void)
while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
}
void rtc_set_alarm_time(u32 alarm_time)
void rtc_set_alarm_time(uint32_t alarm_time)
{
rtc_enter_config_mode();
RTC_ALRL = (alarm_time & 0x0000ffff);
@@ -148,7 +148,7 @@ void rtc_disable_alarm(void)
rtc_exit_config_mode();
}
void rtc_set_prescale_val(u32 prescale_val)
void rtc_set_prescale_val(uint32_t prescale_val)
{
rtc_enter_config_mode();
RTC_PRLL = prescale_val & 0x0000ffff; /* PRL[15:0] */
@@ -156,22 +156,22 @@ void rtc_set_prescale_val(u32 prescale_val)
rtc_exit_config_mode();
}
u32 rtc_get_counter_val(void)
uint32_t rtc_get_counter_val(void)
{
return (RTC_CNTH << 16) | RTC_CNTL;
}
u32 rtc_get_prescale_div_val(void)
uint32_t rtc_get_prescale_div_val(void)
{
return (RTC_DIVH << 16) | RTC_DIVL;
}
u32 rtc_get_alarm_val(void)
uint32_t rtc_get_alarm_val(void)
{
return (RTC_ALRH << 16) | RTC_ALRL;
}
void rtc_set_counter_val(u32 counter_val)
void rtc_set_counter_val(uint32_t counter_val)
{
rtc_enter_config_mode();
RTC_CNTH = (counter_val & 0xffff0000) >> 16; /* CNT[31:16] */
@@ -237,9 +237,9 @@ void rtc_clear_flag(rtcflag_t flag_val)
}
}
u32 rtc_check_flag(rtcflag_t flag_val)
uint32_t rtc_check_flag(rtcflag_t flag_val)
{
u32 reg32;
uint32_t reg32;
/* Read correct flag. */
switch (flag_val) {
@@ -262,7 +262,7 @@ u32 rtc_check_flag(rtcflag_t flag_val)
void rtc_awake_from_standby(void)
{
u32 reg32;
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);
@@ -279,9 +279,9 @@ void rtc_awake_from_standby(void)
while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
}
void rtc_auto_awake(osc_t clock_source, u32 prescale_val)
void rtc_auto_awake(osc_t clock_source, uint32_t prescale_val)
{
u32 reg32;
uint32_t reg32;
/* Enable power and backup interface clocks. */
RCC_APB1ENR |= (RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN);

2
lib/stm32/f1/timer.c
View File

@@ -46,7 +46,7 @@ in which case this file must be added to the compile list. */
@param[in] pol ::tim_ic_pol. Input Capture polarity.
*/
void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic,
void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic,
enum tim_ic_pol pol)
{
if (pol) {

42
lib/stm32/f2/rcc.c
View File

@@ -24,8 +24,8 @@
#include <libopencm3/stm32/f2/flash.h>
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
u32 rcc_ppre1_frequency = 16000000;
u32 rcc_ppre2_frequency = 16000000;
uint32_t rcc_ppre1_frequency = 16000000;
uint32_t rcc_ppre2_frequency = 16000000;
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = {
{ /* 120MHz */
@@ -264,81 +264,81 @@ void rcc_osc_bypass_disable(osc_t osc)
}
}
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg |= en;
}
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg &= ~en;
}
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
{
*reg |= reset;
}
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
{
*reg &= ~clear_reset;
}
void rcc_set_sysclk_source(u32 clk)
void rcc_set_sysclk_source(uint32_t clk)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
}
void rcc_set_pll_source(u32 pllsrc)
void rcc_set_pll_source(uint32_t pllsrc)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_PLLCFGR;
reg32 &= ~(1 << 22);
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
}
void rcc_set_ppre2(u32 ppre2)
void rcc_set_ppre2(uint32_t ppre2)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
RCC_CFGR = (reg32 | (ppre2 << 13));
}
void rcc_set_ppre1(u32 ppre1)
void rcc_set_ppre1(uint32_t ppre1)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
RCC_CFGR = (reg32 | (ppre1 << 10));
}
void rcc_set_hpre(u32 hpre)
void rcc_set_hpre(uint32_t hpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
}
void rcc_set_rtcpre(u32 rtcpre)
void rcc_set_rtcpre(uint32_t rtcpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
RCC_CFGR = (reg32 | (rtcpre << 16));
}
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
@@ -346,7 +346,7 @@ void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
@@ -355,7 +355,7 @@ void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
u32 rcc_system_clock_source(void)
uint32_t rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return (RCC_CFGR & 0x000c) >> 2;

148
lib/stm32/f4/adc.c
View File

@@ -52,7 +52,7 @@ adc_set_clk_prescale(RCC_CFGR_ADCPRE_BY2);
adc_disable_scan_mode(ADC1);
adc_set_single_conversion_mode(ADC1);
adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
u8 channels[] = ADC_CHANNEL0;
uint8_t channels[] = ADC_CHANNEL0;
adc_set_regular_sequence(ADC1, 1, channels);
adc_set_multi_mode(ADC_CCR_MULTI_INDEPENDENT);
adc_power_on(ADC1);
@@ -94,7 +94,7 @@ Turn off the ADC to reduce power consumption to a few microamps.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_off(u32 adc)
void adc_off(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ADON;
}
@@ -109,7 +109,7 @@ alignment takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_analog_watchdog_regular(u32 adc)
void adc_enable_analog_watchdog_regular(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDEN;
}
@@ -120,7 +120,7 @@ void adc_enable_analog_watchdog_regular(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_analog_watchdog_regular(u32 adc)
void adc_disable_analog_watchdog_regular(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
}
@@ -135,7 +135,7 @@ alignment takes place, so the thresholds are left-aligned.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_analog_watchdog_injected(u32 adc)
void adc_enable_analog_watchdog_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JAWDEN;
}
@@ -146,7 +146,7 @@ void adc_enable_analog_watchdog_injected(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_analog_watchdog_injected(u32 adc)
void adc_disable_analog_watchdog_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
}
@@ -167,7 +167,7 @@ of the subgroup at the beginning of the whole group.
adc_cr1_discnum
*/
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
{
if ((length-1) > 7) {
return;
@@ -182,7 +182,7 @@ void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_discontinuous_mode_regular(u32 adc)
void adc_disable_discontinuous_mode_regular(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
}
@@ -197,7 +197,7 @@ entire group has been converted.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_discontinuous_mode_injected(u32 adc)
void adc_enable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
}
@@ -208,7 +208,7 @@ void adc_enable_discontinuous_mode_injected(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_discontinuous_mode_injected(u32 adc)
void adc_disable_discontinuous_mode_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
}
@@ -223,7 +223,7 @@ channels is disabled as required.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_automatic_injected_group_conversion(u32 adc)
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
{
adc_disable_external_trigger_injected(adc);
ADC_CR1(adc) |= ADC_CR1_JAUTO;
@@ -235,7 +235,7 @@ void adc_enable_automatic_injected_group_conversion(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_automatic_injected_group_conversion(u32 adc)
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
}
@@ -256,7 +256,7 @@ adc_enable_analog_watchdog_regular.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_analog_watchdog_on_all_channels(u32 adc)
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
}
@@ -278,9 +278,9 @@ adc_enable_analog_watchdog_regular.
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
*/
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel)
{
u32 reg32;
uint32_t reg32;
reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
if (channel < 18) {
@@ -300,7 +300,7 @@ previous one. It can use single, continuous or discontinuous mode.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_scan_mode(u32 adc)
void adc_enable_scan_mode(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_SCAN;
}
@@ -311,7 +311,7 @@ void adc_enable_scan_mode(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_scan_mode(u32 adc)
void adc_disable_scan_mode(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_SCAN;
}
@@ -322,7 +322,7 @@ void adc_disable_scan_mode(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_eoc_interrupt_injected(u32 adc)
void adc_enable_eoc_interrupt_injected(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
}
@@ -333,7 +333,7 @@ void adc_enable_eoc_interrupt_injected(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_eoc_interrupt_injected(u32 adc)
void adc_disable_eoc_interrupt_injected(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
}
@@ -344,7 +344,7 @@ void adc_disable_eoc_interrupt_injected(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_awd_interrupt(u32 adc)
void adc_enable_awd_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_AWDIE;
}
@@ -355,7 +355,7 @@ void adc_enable_awd_interrupt(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_awd_interrupt(u32 adc)
void adc_disable_awd_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
}
@@ -366,7 +366,7 @@ void adc_disable_awd_interrupt(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_eoc_interrupt(u32 adc)
void adc_enable_eoc_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_EOCIE;
}
@@ -377,7 +377,7 @@ void adc_enable_eoc_interrupt(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_eoc_interrupt(u32 adc)
void adc_disable_eoc_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
}
@@ -391,7 +391,7 @@ hardware once conversion starts.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_start_conversion_regular(u32 adc)
void adc_start_conversion_regular(uint32_t adc)
{
/* Start conversion on regular channels. */
ADC_CR2(adc) |= ADC_CR2_SWSTART;
@@ -409,7 +409,7 @@ hardware once conversion starts.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_start_conversion_injected(u32 adc)
void adc_start_conversion_injected(uint32_t adc)
{
/* Start conversion on injected channels. */
ADC_CR2(adc) |= ADC_CR2_JSWSTART;
@@ -424,7 +424,7 @@ void adc_start_conversion_injected(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_left_aligned(u32 adc)
void adc_set_left_aligned(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_ALIGN;
}
@@ -435,7 +435,7 @@ void adc_set_left_aligned(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_right_aligned(u32 adc)
void adc_set_right_aligned(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
}
@@ -446,7 +446,7 @@ void adc_set_right_aligned(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_dma(u32 adc)
void adc_enable_dma(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_DMA;
}
@@ -457,7 +457,7 @@ void adc_enable_dma(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_dma(u32 adc)
void adc_disable_dma(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_DMA;
}
@@ -471,7 +471,7 @@ group immediately following completion of the previous channel group conversion.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_continuous_conversion_mode(u32 adc)
void adc_set_continuous_conversion_mode(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_CONT;
}
@@ -485,7 +485,7 @@ and stops.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_single_conversion_mode(u32 adc)
void adc_set_single_conversion_mode(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_CONT;
}
@@ -501,9 +501,9 @@ adc_channel
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
*/
void adc_set_sample_time(u32 adc, u8 channel, u8 time)
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
{
u32 reg32;
uint32_t reg32;
if (channel < 10) {
reg32 = ADC_SMPR2(adc);
@@ -528,10 +528,10 @@ for all channels.
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
*/
void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
{
u8 i;
u32 reg32 = 0;
uint8_t i;
uint32_t reg32 = 0;
for (i = 0; i <= 9; i++) {
reg32 |= (time << (i * 3));
@@ -551,11 +551,11 @@ void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
@param[in] threshold Unsigned int8. Upper threshold value
*/
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
{
u32 reg32 = 0;
uint32_t reg32 = 0;
reg32 = (u32)threshold;
reg32 = (uint32_t)threshold;
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_HTR(adc) = reg32;
}
@@ -567,11 +567,11 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
@param[in] threshold Unsigned int8. Lower threshold value
*/
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
{
u32 reg32 = 0;
uint32_t reg32 = 0;
reg32 = (u32)threshold;
reg32 = (uint32_t)threshold;
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_LTR(adc) = reg32;
}
@@ -588,10 +588,10 @@ conversion is reset and conversion begins again with the newly defined group.
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
*/
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
u8 i = 0;
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
uint8_t i = 0;
/* Maximum sequence length is 16 channels. */
if (length > 16) {
@@ -628,10 +628,10 @@ conversion is reset and conversion begins again with the newly defined group.
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
*/
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
{
u32 reg32 = 0;
u8 i = 0;
uint32_t reg32 = 0;
uint8_t i = 0;
/* Maximum sequence length is 4 channels. */
if ((length-1) > 3) {
@@ -657,7 +657,7 @@ converted.
@returns bool. End of conversion flag.
*/
bool adc_eoc(u32 adc)
bool adc_eoc(uint32_t adc)
{
return (ADC_SR(adc) & ADC_SR_EOC) != 0;
}
@@ -671,7 +671,7 @@ This flag is set after all channels of an injected group have been converted.
@returns bool. End of conversion flag.
*/
bool adc_eoc_injected(u32 adc)
bool adc_eoc_injected(uint32_t adc)
{
return (ADC_SR(adc) & ADC_SR_JEOC) != 0;
}
@@ -687,7 +687,7 @@ an appropriate dual mode has been set @see adc_set_dual_mode.
@returns Unsigned int32 conversion result.
*/
u32 adc_read_regular(u32 adc)
uint32_t adc_read_regular(uint32_t adc)
{
return ADC_DR(adc);
}
@@ -705,7 +705,7 @@ adc_set_injected_offset.
@returns Unsigned int32 conversion result.
*/
u32 adc_read_injected(u32 adc, u8 reg)
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
{
switch (reg) {
case 1:
@@ -732,7 +732,7 @@ for each injected data register.
@param[in] offset Unsigned int32.
*/
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
{
switch (reg) {
case 1:
@@ -760,7 +760,7 @@ If the ADC is already on this function call will have no effect.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_power_on(u32 adc)
void adc_power_on(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_ADON;
}
@@ -774,9 +774,9 @@ The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
adc_ccr_adcpre
*/
void adc_set_clk_prescale(u32 prescale)
void adc_set_clk_prescale(uint32_t prescale)
{
u32 reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale);
uint32_t reg32 = ((ADC_CCR & ~ADC_CCR_ADCPRE_MASK) | prescale);
ADC_CCR = reg32;
}
@@ -791,7 +791,7 @@ The various modes possible are described in the reference manual.
@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode
*/
void adc_set_multi_mode(u32 mode)
void adc_set_multi_mode(uint32_t mode)
{
ADC_CCR |= mode;
}
@@ -809,9 +809,9 @@ the trigger polarity is zero, triggering is disabled.
adc_trigger_polarity_regular
*/
void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity)
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity)
{
u32 reg32 = ADC_CR2(adc);
uint32_t reg32 = ADC_CR2(adc);
reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK);
reg32 |= (trigger | polarity);
@@ -824,7 +824,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_external_trigger_regular(u32 adc)
void adc_disable_external_trigger_regular(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK;
}
@@ -841,9 +841,9 @@ the polarity of the trigger event: rising or falling edge or both.
adc_trigger_polarity_injected
*/
void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity)
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity)
{
u32 reg32 = ADC_CR2(adc);
uint32_t reg32 = ADC_CR2(adc);
reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK);
reg32 |= (trigger | polarity);
@@ -856,7 +856,7 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_external_trigger_injected(u32 adc)
void adc_disable_external_trigger_injected(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK;
}
@@ -871,9 +871,9 @@ corresponding reduction in conversion time (resolution + 3 ADC clock cycles).
@param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res
*/
void adc_set_resolution(u32 adc, u16 resolution)
void adc_set_resolution(uint32_t adc, uint16_t resolution)
{
u32 reg32 = ADC_CR1(adc);
uint32_t reg32 = ADC_CR1(adc);
reg32 &= ~ADC_CR1_RES_MASK;
reg32 |= resolution;
@@ -890,7 +890,7 @@ terminated and any conversion sequence is aborted.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_enable_overrun_interrupt(u32 adc)
void adc_enable_overrun_interrupt(uint32_t adc)
{
ADC_CR1(adc) |= ADC_CR1_OVRIE;
}
@@ -901,7 +901,7 @@ void adc_enable_overrun_interrupt(u32 adc)
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_disable_overrun_interrupt(u32 adc)
void adc_disable_overrun_interrupt(uint32_t adc)
{
ADC_CR1(adc) &= ~ADC_CR1_OVRIE;
}
@@ -917,7 +917,7 @@ any conversion sequence is aborted.
@returns Unsigned int32 conversion result.
*/
bool adc_get_overrun_flag(u32 adc)
bool adc_get_overrun_flag(uint32_t adc)
{
return ADC_SR(adc) & ADC_SR_OVR;
}
@@ -933,7 +933,7 @@ conversions (see the reference manual).
@returns Unsigned int32 conversion result.
*/
void adc_clear_overrun_flag(u32 adc)
void adc_clear_overrun_flag(uint32_t adc)
{
/* need to write zero to clear this */
ADC_SR(adc) &= ~ADC_SR_OVR;
@@ -948,7 +948,7 @@ sequence. Overrun detection is enabled only if DMA is enabled.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_eoc_after_each(u32 adc)
void adc_eoc_after_each(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_EOCS;
}
@@ -962,7 +962,7 @@ the sequence. Overrun detection is enabled always.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_eoc_after_group(u32 adc)
void adc_eoc_after_group(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_EOCS;
}
@@ -976,7 +976,7 @@ in the DMA sequence. This allows DMA to be used in continuous circular mode.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_dma_continue(u32 adc)
void adc_set_dma_continue(uint32_t adc)
{
ADC_CR2(adc) |= ADC_CR2_DDS;
}
@@ -990,7 +990,7 @@ sequence. This can avoid overrun errors.
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
*/
void adc_set_dma_terminate(u32 adc)
void adc_set_dma_terminate(uint32_t adc)
{
ADC_CR2(adc) &= ~ADC_CR2_DDS;
}
@@ -1003,7 +1003,7 @@ This flag is set when the converted voltage crosses the high or low thresholds.
@returns bool. AWD flag.
*/
bool adc_awd(u32 adc)
bool adc_awd(uint32_t adc)
{
return ADC_SR(adc) & ADC_SR_AWD;
}

42
lib/stm32/f4/rcc.c
View File

@@ -25,8 +25,8 @@
#include <libopencm3/stm32/f4/flash.h>
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
u32 rcc_ppre1_frequency = 16000000;
u32 rcc_ppre2_frequency = 16000000;
uint32_t rcc_ppre1_frequency = 16000000;
uint32_t rcc_ppre2_frequency = 16000000;
const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = {
{ /* 48MHz */
@@ -381,81 +381,81 @@ void rcc_osc_bypass_disable(osc_t osc)
}
}
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg |= en;
}
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg &= ~en;
}
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
{
*reg |= reset;
}
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
{
*reg &= ~clear_reset;
}
void rcc_set_sysclk_source(u32 clk)
void rcc_set_sysclk_source(uint32_t clk)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
}
void rcc_set_pll_source(u32 pllsrc)
void rcc_set_pll_source(uint32_t pllsrc)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_PLLCFGR;
reg32 &= ~(1 << 22);
RCC_PLLCFGR = (reg32 | (pllsrc << 22));
}
void rcc_set_ppre2(u32 ppre2)
void rcc_set_ppre2(uint32_t ppre2)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
RCC_CFGR = (reg32 | (ppre2 << 13));
}
void rcc_set_ppre1(u32 ppre1)
void rcc_set_ppre1(uint32_t ppre1)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
RCC_CFGR = (reg32 | (ppre1 << 10));
}
void rcc_set_hpre(u32 hpre)
void rcc_set_hpre(uint32_t hpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
}
void rcc_set_rtcpre(u32 rtcpre)
void rcc_set_rtcpre(uint32_t rtcpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20));
RCC_CFGR = (reg32 | (rtcpre << 16));
}
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
@@ -463,7 +463,7 @@ void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq)
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq)
{
RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
(plln << RCC_PLLCFGR_PLLN_SHIFT) |
@@ -472,7 +472,7 @@ void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq)
(pllq << RCC_PLLCFGR_PLLQ_SHIFT);
}
u32 rcc_system_clock_source(void)
uint32_t rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return (RCC_CFGR & 0x000c) >> 2;

4
lib/stm32/l1/flash.c
View File

@@ -41,9 +41,9 @@ void flash_prefetch_disable(void)
FLASH_ACR &= ~FLASH_ACR_PRFTEN;
}
void flash_set_ws(u32 ws)
void flash_set_ws(uint32_t ws)
{
u32 reg32;
uint32_t reg32;
reg32 = FLASH_ACR;
reg32 &= ~(1 << 0);

2
lib/stm32/l1/pwr.c
View File

@@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
void pwr_set_vos_scale(vos_scale_t scale)
{
/* You are not allowed to write zeros here, don't try and optimize! */
u32 reg = PWR_CR;
uint32_t reg = PWR_CR;
reg &= ~(PWR_CR_VOS_MASK);
switch (scale) {
case RANGE1:

46
lib/stm32/l1/rcc.c
View File

@@ -26,8 +26,8 @@
#include <libopencm3/stm32/pwr.h>
/* Set the default ppre1 and ppre2 peripheral clock frequencies after reset. */
u32 rcc_ppre1_frequency = 2097000;
u32 rcc_ppre2_frequency = 2097000;
uint32_t rcc_ppre1_frequency = 2097000;
uint32_t rcc_ppre2_frequency = 2097000;
const clock_scale_t clock_config[CLOCK_CONFIG_END] = {
{ /* 24MHz PLL from HSI */
@@ -346,38 +346,38 @@ void rcc_osc_bypass_disable(osc_t osc)
}
}
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg |= en;
}
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en)
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
{
*reg &= ~en;
}
void rcc_peripheral_reset(volatile u32 *reg, u32 reset)
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
{
*reg |= reset;
}
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset)
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
{
*reg &= ~clear_reset;
}
void rcc_set_sysclk_source(u32 clk)
void rcc_set_sysclk_source(uint32_t clk)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 1) | (1 << 0));
RCC_CFGR = (reg32 | clk);
}
void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor)
void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, uint32_t divisor)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
@@ -389,58 +389,58 @@ void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor)
RCC_CFGR = reg32;
}
void rcc_set_pll_source(u32 pllsrc)
void rcc_set_pll_source(uint32_t pllsrc)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~(1 << 16);
RCC_CFGR = (reg32 | (pllsrc << 16));
}
void rcc_set_ppre2(u32 ppre2)
void rcc_set_ppre2(uint32_t ppre2)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 12) | (1 << 11));
RCC_CFGR = (reg32 | (ppre2 << 11));
}
void rcc_set_ppre1(u32 ppre1)
void rcc_set_ppre1(uint32_t ppre1)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 9) | (1 << 8));
RCC_CFGR = (reg32 | (ppre1 << 8));
}
void rcc_set_hpre(u32 hpre)
void rcc_set_hpre(uint32_t hpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
}
void rcc_set_rtcpre(u32 rtcpre)
void rcc_set_rtcpre(uint32_t rtcpre)
{
u32 reg32;
uint32_t reg32;
reg32 = RCC_CR;
reg32 &= ~((1 << 30) | (1 << 29));
RCC_CR = (reg32 | (rtcpre << 29));
}
u32 rcc_system_clock_source(void)
uint32_t rcc_system_clock_source(void)
{
/* Return the clock source which is used as system clock. */
return (RCC_CFGR & 0x000c) >> 2;
}
void rcc_rtc_select_clock(u32 clock)
void rcc_rtc_select_clock(uint32_t clock)
{
RCC_CSR &= ~(RCC_CSR_RTCSEL_MASK << RCC_CSR_RTCSEL_SHIFT);
RCC_CSR |= (clock << RCC_CSR_RTCSEL_SHIFT);
@@ -450,7 +450,7 @@ void rcc_clock_setup_msi(const clock_scale_t *clock)
{
/* Enable internal multi-speed oscillator. */
u32 reg = RCC_ICSCR;
uint32_t reg = RCC_ICSCR;
reg &= ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT);
reg |= (clock->msi_range << RCC_ICSCR_MSIRANGE_SHIFT);
RCC_ICSCR = reg;

2
lib/stm32/l1/timer.c
View File

@@ -45,7 +45,7 @@ Set timer options register on TIM2 or TIM3, used for trigger remapping.
@ref tim3_opt_trigger_remap.
*/
void timer_set_option(u32 timer_peripheral, u32 option)
void timer_set_option(uint32_t timer_peripheral, uint32_t option)
{
if (timer_peripheral == TIM2) {
TIM_OR(timer_peripheral) &= ~TIM2_OR_ITR1_RMP_MASK;

18
lib/usb/usb.c
View File

@@ -65,7 +65,7 @@ usbd_device *usbd_init(const usbd_driver *driver,
const struct usb_device_descriptor *dev,
const struct usb_config_descriptor *conf,
const char **strings, int num_strings,
u8 *control_buffer, u16 control_buffer_size)
uint8_t *control_buffer, uint16_t control_buffer_size)
{
usbd_device *usbd_dev;
@@ -137,34 +137,34 @@ void usbd_disconnect(usbd_device *usbd_dev, bool disconnected)
}
}
void usbd_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
void (*callback)(usbd_device *usbd_dev, u8 ep))
void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size,
void (*callback)(usbd_device *usbd_dev, uint8_t ep))
{
usbd_dev->driver->ep_setup(usbd_dev, addr, type, max_size, callback);
}
u16 usbd_ep_write_packet(usbd_device *usbd_dev, u8 addr,
const void *buf, u16 len)
uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len)
{
return usbd_dev->driver->ep_write_packet(usbd_dev, addr, buf, len);
}
u16 usbd_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len)
uint16_t usbd_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len)
{
return usbd_dev->driver->ep_read_packet(usbd_dev, addr, buf, len);
}
void usbd_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
{
usbd_dev->driver->ep_stall_set(usbd_dev, addr, stall);
}
u8 usbd_ep_stall_get(usbd_device *usbd_dev, u8 addr)
uint8_t usbd_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
{
return usbd_dev->driver->ep_stall_get(usbd_dev, addr);
}
void usbd_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
void usbd_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
{
usbd_dev->driver->ep_nak_set(usbd_dev, addr, nak);
}

12
lib/usb/usb_control.c
View File

@@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license
#include "usb_private.h"
/* Register application callback function for handling USB control requests. */
int usbd_register_control_callback(usbd_device *usbd_dev, u8 type, u8 type_mask,
int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type, uint8_t type_mask,
usbd_control_callback callback)
{
int i;
@@ -85,10 +85,10 @@ static void usb_control_send_chunk(usbd_device *usbd_dev)
static int usb_control_recv_chunk(usbd_device *usbd_dev)
{
u16 packetsize = MIN(usbd_dev->desc->bMaxPacketSize0,
uint16_t packetsize = MIN(usbd_dev->desc->bMaxPacketSize0,
usbd_dev->control_state.req.wLength -
usbd_dev->control_state.ctrl_len);
u16 size = usbd_ep_read_packet(usbd_dev, 0,
uint16_t size = usbd_ep_read_packet(usbd_dev, 0,
usbd_dev->control_state.ctrl_buf +
usbd_dev->control_state.ctrl_len,
packetsize);
@@ -177,7 +177,7 @@ static void usb_control_setup_write(usbd_device *usbd_dev,
/* Do not appear to belong to the API, so are omitted from docs */
/**@}*/
void _usbd_control_setup(usbd_device *usbd_dev, u8 ea)
void _usbd_control_setup(usbd_device *usbd_dev, uint8_t ea)
{
struct usb_setup_data *req = &usbd_dev->control_state.req;
(void)ea;
@@ -198,7 +198,7 @@ void _usbd_control_setup(usbd_device *usbd_dev, u8 ea)
}
}
void _usbd_control_out(usbd_device *usbd_dev, u8 ea)
void _usbd_control_out(usbd_device *usbd_dev, uint8_t ea)
{
(void)ea;
@@ -244,7 +244,7 @@ void _usbd_control_out(usbd_device *usbd_dev, u8 ea)
}
}
void _usbd_control_in(usbd_device *usbd_dev, u8 ea)
void _usbd_control_in(usbd_device *usbd_dev, uint8_t ea)
{
(void)ea;
struct usb_setup_data *req = &(usbd_dev->control_state.req);

74
lib/usb/usb_f103.c
View File

@@ -25,21 +25,21 @@
#include "usb_private.h"
static usbd_device *stm32f103_usbd_init(void);
static void stm32f103_set_address(usbd_device *usbd_dev, u8 addr);
static void stm32f103_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type,
u16 max_size,
void (*callback) (usbd_device *usbd_dev, u8 ep));
static void stm32f103_set_address(usbd_device *usbd_dev, uint8_t addr);
static void stm32f103_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type,
uint16_t max_size,
void (*callback) (usbd_device *usbd_dev, uint8_t ep));
static void stm32f103_endpoints_reset(usbd_device *usbd_dev);
static void stm32f103_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall);
static u8 stm32f103_ep_stall_get(usbd_device *usbd_dev, u8 addr);
static void stm32f103_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak);
static u16 stm32f103_ep_write_packet(usbd_device *usbd_dev, u8 addr,
const void *buf, u16 len);
static u16 stm32f103_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
u16 len);
static void stm32f103_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
static uint8_t stm32f103_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
static void stm32f103_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
static uint16_t stm32f103_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len);
static uint16_t stm32f103_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf,
uint16_t len);
static void stm32f103_poll(usbd_device *usbd_dev);
static u8 force_nak[8];
static uint8_t force_nak[8];
static struct _usbd_device usbd_dev;
const struct _usbd_driver stm32f103_usb_driver = {
@@ -69,7 +69,7 @@ static usbd_device *stm32f103_usbd_init(void)
return &usbd_dev;
}
static void stm32f103_set_address(usbd_device *dev, u8 addr)
static void stm32f103_set_address(usbd_device *dev, uint8_t addr)
{
(void)dev;
/* Set device address and enable. */
@@ -82,7 +82,7 @@ static void stm32f103_set_address(usbd_device *dev, u8 addr)
* @param ep Index of endpoint to configure.
* @param size Size in bytes of the RX buffer.
*/
static void usb_set_ep_rx_bufsize(usbd_device *dev, u8 ep, u32 size)
static void usb_set_ep_rx_bufsize(usbd_device *dev, uint8_t ep, uint32_t size)
{
(void)dev;
if (size > 62) {
@@ -98,18 +98,18 @@ static void usb_set_ep_rx_bufsize(usbd_device *dev, u8 ep, u32 size)
}
}
static void stm32f103_ep_setup(usbd_device *dev, u8 addr, u8 type,
u16 max_size,
void (*callback) (usbd_device *usbd_dev, u8 ep))
static void stm32f103_ep_setup(usbd_device *dev, uint8_t addr, uint8_t type,
uint16_t max_size,
void (*callback) (usbd_device *usbd_dev, uint8_t ep))
{
/* Translate USB standard type codes to STM32. */
const u16 typelookup[] = {
const uint16_t typelookup[] = {
[USB_ENDPOINT_ATTR_CONTROL] = USB_EP_TYPE_CONTROL,
[USB_ENDPOINT_ATTR_ISOCHRONOUS] = USB_EP_TYPE_ISO,
[USB_ENDPOINT_ATTR_BULK] = USB_EP_TYPE_BULK,
[USB_ENDPOINT_ATTR_INTERRUPT] = USB_EP_TYPE_INTERRUPT,
};
u8 dir = addr & 0x80;
uint8_t dir = addr & 0x80;
addr &= 0x7f;
/* Assign address. */
@@ -152,7 +152,7 @@ static void stm32f103_endpoints_reset(usbd_device *dev)
dev->pm_top = 0x40 + (2 * dev->desc->bMaxPacketSize0);
}
static void stm32f103_ep_stall_set(usbd_device *dev, u8 addr, u8 stall)
static void stm32f103_ep_stall_set(usbd_device *dev, uint8_t addr, uint8_t stall)
{
(void)dev;
if (addr == 0) {
@@ -181,7 +181,7 @@ static void stm32f103_ep_stall_set(usbd_device *dev, u8 addr, u8 stall)
}
}
static u8 stm32f103_ep_stall_get(usbd_device *dev, u8 addr)
static uint8_t stm32f103_ep_stall_get(usbd_device *dev, uint8_t addr)
{
(void)dev;
if (addr & 0x80) {
@@ -196,7 +196,7 @@ static u8 stm32f103_ep_stall_get(usbd_device *dev, u8 addr)
return 0;
}
static void stm32f103_ep_nak_set(usbd_device *dev, u8 addr, u8 nak)
static void stm32f103_ep_nak_set(usbd_device *dev, uint8_t addr, uint8_t nak)
{
(void)dev;
/* It does not make sence to force NAK on IN endpoints. */
@@ -220,18 +220,18 @@ static void stm32f103_ep_nak_set(usbd_device *dev, u8 addr, u8 nak)
* @param buf Source pointer to data buffer.
* @param len Number of bytes to copy.
*/
static void usb_copy_to_pm(volatile void *vPM, const void *buf, u16 len)
static void usb_copy_to_pm(volatile void *vPM, const void *buf, uint16_t len)
{
const u16 *lbuf = buf;
volatile u16 *PM = vPM;
const uint16_t *lbuf = buf;
volatile uint16_t *PM = vPM;
for (len = (len + 1) >> 1; len; PM += 2, lbuf++, len--) {
*PM = *lbuf;
}
}
static u16 stm32f103_ep_write_packet(usbd_device *dev, u8 addr,
const void *buf, u16 len)
static uint16_t stm32f103_ep_write_packet(usbd_device *dev, uint8_t addr,
const void *buf, uint16_t len)
{
(void)dev;
addr &= 0x7F;
@@ -254,23 +254,23 @@ static u16 stm32f103_ep_write_packet(usbd_device *dev, u8 addr,
* @param vPM Destination pointer into packet memory.
* @param len Number of bytes to copy.
*/
static void usb_copy_from_pm(void *buf, const volatile void *vPM, u16 len)
static void usb_copy_from_pm(void *buf, const volatile void *vPM, uint16_t len)
{
u16 *lbuf = buf;
const volatile u16 *PM = vPM;
u8 odd = len & 1;
uint16_t *lbuf = buf;
const volatile uint16_t *PM = vPM;
uint8_t odd = len & 1;
for (len >>= 1; len; PM += 2, lbuf++, len--) {
*lbuf = *PM;
}
if (odd) {
*(u8 *) lbuf = *(u8 *) PM;
*(uint8_t *) lbuf = *(uint8_t *) PM;
}
}
static u16 stm32f103_ep_read_packet(usbd_device *dev, u8 addr, void *buf,
u16 len)
static uint16_t stm32f103_ep_read_packet(usbd_device *dev, uint8_t addr, void *buf,
uint16_t len)
{
(void)dev;
if ((*USB_EP_REG(addr) & USB_EP_RX_STAT) == USB_EP_RX_STAT_VALID) {
@@ -290,7 +290,7 @@ static u16 stm32f103_ep_read_packet(usbd_device *dev, u8 addr, void *buf,
static void stm32f103_poll(usbd_device *dev)
{
u16 istr = *USB_ISTR_REG;
uint16_t istr = *USB_ISTR_REG;
if (istr & USB_ISTR_RESET) {
dev->pm_top = 0x40;
@@ -300,8 +300,8 @@ static void stm32f103_poll(usbd_device *dev)
}
if (istr & USB_ISTR_CTR) {
u8 ep = istr & USB_ISTR_EP_ID;
u8 type = (istr & USB_ISTR_DIR) ? 1 : 0;
uint8_t ep = istr & USB_ISTR_EP_ID;
uint8_t type = (istr & USB_ISTR_DIR) ? 1 : 0;
if (type) /* OUT or SETUP transaction */
type += (*USB_EP_REG(ep) & USB_EP_SETUP) ? 1 : 0;

42
lib/usb/usb_fx07_common.c
View File

@@ -31,21 +31,21 @@
* according to the selected cores base address. */
#define dev_base_address (usbd_dev->driver->base_address)
#define REBASE(x) MMIO32((x)+(dev_base_address))
#define REBASE_FIFO(x) ((volatile u32*)((dev_base_address) + (OTG_FIFO(x))))
#define REBASE_FIFO(x) ((volatile uint32_t*)((dev_base_address) + (OTG_FIFO(x))))
void stm32fx07_set_address(usbd_device *usbd_dev, u8 addr)
void stm32fx07_set_address(usbd_device *usbd_dev, uint8_t addr)
{
REBASE(OTG_DCFG) = (REBASE(OTG_DCFG) & ~OTG_FS_DCFG_DAD) | (addr << 4);
}
void stm32fx07_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
void (*callback) (usbd_device *usbd_dev, u8 ep))
void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size,
void (*callback) (usbd_device *usbd_dev, uint8_t ep))
{
/*
* Configure endpoint address and type. Allocate FIFO memory for
* endpoint. Install callback funciton.
*/
u8 dir = addr & 0x80;
uint8_t dir = addr & 0x80;
addr &= 0x7f;
if (addr == 0) { /* For the default control endpoint */
@@ -120,7 +120,7 @@ void stm32fx07_endpoints_reset(usbd_device *usbd_dev)
usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0;
}
void stm32fx07_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
{
if (addr == 0) {
if (stall) {
@@ -149,7 +149,7 @@ void stm32fx07_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall)
}
}
u8 stm32fx07_ep_stall_get(usbd_device *usbd_dev, u8 addr)
uint8_t stm32fx07_ep_stall_get(usbd_device *usbd_dev, uint8_t addr)
{
/* Return non-zero if STALL set. */
if (addr & 0x80) {
@@ -161,7 +161,7 @@ u8 stm32fx07_ep_stall_get(usbd_device *usbd_dev, u8 addr)
}
}
void stm32fx07_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
void stm32fx07_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak)
{
/* It does not make sence to force NAK on IN endpoints. */
if (addr & 0x80) {
@@ -177,10 +177,10 @@ void stm32fx07_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak)
}
}
u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr,
const void *buf, u16 len)
uint16_t stm32fx07_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len)
{
const u32 *buf32 = buf;
const uint32_t *buf32 = buf;
int i;
addr &= 0x7F;
@@ -194,7 +194,7 @@ u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr,
REBASE(OTG_DIEPTSIZ(addr)) = OTG_FS_DIEPSIZ0_PKTCNT | len;
REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_EPENA |
OTG_FS_DIEPCTL0_CNAK;
volatile u32 *fifo = REBASE_FIFO(addr);
volatile uint32_t *fifo = REBASE_FIFO(addr);
/* Copy buffer to endpoint FIFO, note - memcpy does not work */
for (i = len; i > 0; i -= 4) {
@@ -204,16 +204,16 @@ u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr,
return len;
}
u16 stm32fx07_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len)
uint16_t stm32fx07_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len)
{
int i;
u32 *buf32 = buf;
u32 extra;
uint32_t *buf32 = buf;
uint32_t extra;
len = MIN(len, usbd_dev->rxbcnt);
usbd_dev->rxbcnt -= len;
volatile u32 *fifo = REBASE_FIFO(addr);
volatile uint32_t *fifo = REBASE_FIFO(addr);
for (i = len; i >= 4; i -= 4) {
*buf32++ = *fifo++;
}
@@ -234,7 +234,7 @@ u16 stm32fx07_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len)
void stm32fx07_poll(usbd_device *usbd_dev)
{
/* Read interrupt status register. */
u32 intsts = REBASE(OTG_GINTSTS);
uint32_t intsts = REBASE(OTG_GINTSTS);
int i;
if (intsts & OTG_FS_GINTSTS_ENUMDNE) {
@@ -248,15 +248,15 @@ void stm32fx07_poll(usbd_device *usbd_dev)
/* Note: RX and TX handled differently in this device. */
if (intsts & OTG_FS_GINTSTS_RXFLVL) {
/* Receive FIFO non-empty. */
u32 rxstsp = REBASE(OTG_GRXSTSP);
u32 pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK;
uint32_t rxstsp = REBASE(OTG_GRXSTSP);
uint32_t pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK;
if ((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) &&
(pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP)) {
return;
}
u8 ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK;
u8 type;
uint8_t ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK;
uint8_t type;
if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP) {
type = USB_TRANSACTION_SETUP;
} else {

20
lib/usb/usb_fx07_common.h
View File

@@ -20,17 +20,17 @@
#ifndef __USB_FX07_COMMON_H_
#define __USB_FX07_COMMON_H_
void stm32fx07_set_address(usbd_device *usbd_dev, u8 addr);
void stm32fx07_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
void (*callback)(usbd_device *usbd_dev, u8 ep));
void stm32fx07_set_address(usbd_device *usbd_dev, uint8_t addr);
void stm32fx07_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size,
void (*callback)(usbd_device *usbd_dev, uint8_t ep));
void stm32fx07_endpoints_reset(usbd_device *usbd_dev);
void stm32fx07_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall);
u8 stm32fx07_ep_stall_get(usbd_device *usbd_dev, u8 addr);
void stm32fx07_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak);
u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr, const void *buf,
u16 len);
u16 stm32fx07_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf,
u16 len);
void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
uint8_t stm32fx07_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
void stm32fx07_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
uint16_t stm32fx07_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf,
uint16_t len);
uint16_t stm32fx07_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf,
uint16_t len);
void stm32fx07_poll(usbd_device *usbd_dev);
void stm32fx07_disconnect(usbd_device *usbd_dev, bool disconnected);

70
lib/usb/usb_private.h
View File

@@ -48,13 +48,13 @@ struct _usbd_device {
const char **strings;
int num_strings;
u8 *ctrl_buf; /**< Internal buffer used for control transfers */
u16 ctrl_buf_len;
uint8_t *ctrl_buf; /**< Internal buffer used for control transfers */
uint16_t ctrl_buf_len;
u8 current_address;
u8 current_config;
uint8_t current_address;
uint8_t current_config;
u16 pm_top; /**< Top of allocated endpoint buffer memory */
uint16_t pm_top; /**< Top of allocated endpoint buffer memory */
/* User callback functions for various USB events */
void (*user_callback_reset)(void);
@@ -69,22 +69,22 @@ struct _usbd_device {
DATA_OUT, LAST_DATA_OUT, STATUS_OUT,
} state;
struct usb_setup_data req __aligned(4);
u8 *ctrl_buf;
u16 ctrl_len;
uint8_t *ctrl_buf;
uint16_t ctrl_len;
void (*complete)(usbd_device *usbd_dev,
struct usb_setup_data *req);
} control_state;
struct user_control_callback {
usbd_control_callback cb;
u8 type;
u8 type_mask;
uint8_t type;
uint8_t type_mask;
} user_control_callback[MAX_USER_CONTROL_CALLBACK];
void (*user_callback_ctr[8][3])(usbd_device *usbd_dev, u8 ea);
void (*user_callback_ctr[8][3])(usbd_device *usbd_dev, uint8_t ea);
/* User callback function for some standard USB function hooks */
void (*user_callback_set_config)(usbd_device *usbd_dev, u16 wValue);
void (*user_callback_set_config)(usbd_device *usbd_dev, uint16_t wValue);
const struct _usbd_driver *driver;
@@ -92,12 +92,12 @@ struct _usbd_device {
uint16_t fifo_mem_top;
uint16_t fifo_mem_top_ep0;
u8 force_nak[4];
uint8_t force_nak[4];
/*
* We keep a backup copy of the out endpoint size registers to restore
* them after a transaction.
*/
u32 doeptsiz[4];
uint32_t doeptsiz[4];
/*
* Received packet size for each endpoint. This is assigned in
* stm32f107_poll() which reads the packet status push register GRXSTSP
@@ -115,43 +115,43 @@ enum _usbd_transaction {
/* Do not appear to belong to the API, so are omitted from docs */
/**@}*/
void _usbd_control_in(usbd_device *usbd_dev, u8 ea);
void _usbd_control_out(usbd_device *usbd_dev, u8 ea);
void _usbd_control_setup(usbd_device *usbd_dev, u8 ea);
void _usbd_control_in(usbd_device *usbd_dev, uint8_t ea);
void _usbd_control_out(usbd_device *usbd_dev, uint8_t ea);
void _usbd_control_setup(usbd_device *usbd_dev, uint8_t ea);
int _usbd_standard_request_device(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf,
u16 *len);
struct usb_setup_data *req, uint8_t **buf,
uint16_t *len);
int _usbd_standard_request_interface(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf,
u16 *len);
struct usb_setup_data *req, uint8_t **buf,
uint16_t *len);
int _usbd_standard_request_endpoint(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf,
u16 *len);
struct usb_setup_data *req, uint8_t **buf,
uint16_t *len);
int _usbd_standard_request(usbd_device *usbd_dev, struct usb_setup_data *req,
u8 **buf, u16 *len);
uint8_t **buf, uint16_t *len);
void _usbd_reset(usbd_device *usbd_dev);
/* Functions provided by the hardware abstraction. */
struct _usbd_driver {
usbd_device *(*init)(void);
void (*set_address)(usbd_device *usbd_dev, u8 addr);
void (*ep_setup)(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size,
void (*cb)(usbd_device *usbd_dev, u8 ep));
void (*set_address)(usbd_device *usbd_dev, uint8_t addr);
void (*ep_setup)(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size,
void (*cb)(usbd_device *usbd_dev, uint8_t ep));
void (*ep_reset)(usbd_device *usbd_dev);
void (*ep_stall_set)(usbd_device *usbd_dev, u8 addr, u8 stall);
void (*ep_nak_set)(usbd_device *usbd_dev, u8 addr, u8 nak);
u8 (*ep_stall_get)(usbd_device *usbd_dev, u8 addr);
u16 (*ep_write_packet)(usbd_device *usbd_dev, u8 addr, const void *buf,
u16 len);
u16 (*ep_read_packet)(usbd_device *usbd_dev, u8 addr, void *buf,
u16 len);
void (*ep_stall_set)(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
void (*ep_nak_set)(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
uint8_t (*ep_stall_get)(usbd_device *usbd_dev, uint8_t addr);
uint16_t (*ep_write_packet)(usbd_device *usbd_dev, uint8_t addr, const void *buf,
uint16_t len);
uint16_t (*ep_read_packet)(usbd_device *usbd_dev, uint8_t addr, void *buf,
uint16_t len);
void (*poll)(usbd_device *usbd_dev);
void (*disconnect)(usbd_device *usbd_dev, bool disconnected);
u32 base_address;
uint32_t base_address;
bool set_address_before_status;
u16 rx_fifo_size;
uint16_t rx_fifo_size;
};
#endif

68
lib/usb/usb_standard.c
View File

@@ -41,18 +41,18 @@ LGPL License Terms @ref lgpl_license
void usbd_register_set_config_callback(usbd_device *usbd_dev,
void (*callback)(usbd_device *usbd_dev,
u16 wValue))
uint16_t wValue))
{
usbd_dev->user_callback_set_config = callback;
}
static u16 build_config_descriptor(usbd_device *usbd_dev,
u8 index, u8 *buf, u16 len)
static uint16_t build_config_descriptor(usbd_device *usbd_dev,
uint8_t index, uint8_t *buf, uint16_t len)
{
u8 *tmpbuf = buf;
uint8_t *tmpbuf = buf;
const struct usb_config_descriptor *cfg = &usbd_dev->config[index];
u16 count, total = 0, totallen = 0;
u16 i, j, k;
uint16_t count, total = 0, totallen = 0;
uint16_t i, j, k;
memcpy(buf, cfg, count = MIN(len, cfg->bLength));
buf += count;
@@ -103,24 +103,24 @@ static u16 build_config_descriptor(usbd_device *usbd_dev,
}
/* Fill in wTotalLength. */
*(u16 *)(tmpbuf + 2) = totallen;
*(uint16_t *)(tmpbuf + 2) = totallen;
return total;
}
static int usb_descriptor_type(u16 wValue)
static int usb_descriptor_type(uint16_t wValue)
{
return wValue >> 8;
}
static int usb_descriptor_index(u16 wValue)
static int usb_descriptor_index(uint16_t wValue)
{
return wValue & 0xFF;
}
static int usb_standard_get_descriptor(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
int i, array_idx, descr_idx;
struct usb_string_descriptor *sd;
@@ -129,7 +129,7 @@ static int usb_standard_get_descriptor(usbd_device *usbd_dev,
switch (usb_descriptor_type(req->wValue)) {
case USB_DT_DEVICE:
*buf = (u8 *) usbd_dev->desc;
*buf = (uint8_t *) usbd_dev->desc;
*len = MIN(*len, usbd_dev->desc->bLength);
return USBD_REQ_HANDLED;
case USB_DT_CONFIGURATION:
@@ -182,7 +182,7 @@ static int usb_standard_get_descriptor(usbd_device *usbd_dev,
}
sd->bDescriptorType = USB_DT_STRING;
*buf = (u8 *)sd;
*buf = (uint8_t *)sd;
return USBD_REQ_HANDLED;
}
@@ -190,8 +190,8 @@ static int usb_standard_get_descriptor(usbd_device *usbd_dev,
}
static int usb_standard_set_address(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf,
u16 *len)
struct usb_setup_data *req, uint8_t **buf,
uint16_t *len)
{
(void)req;
(void)buf;
@@ -217,7 +217,7 @@ static int usb_standard_set_address(usbd_device *usbd_dev,
static int usb_standard_set_configuration(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
int i;
@@ -252,7 +252,7 @@ static int usb_standard_set_configuration(usbd_device *usbd_dev,
static int usb_standard_get_configuration(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
(void)req;
@@ -266,7 +266,7 @@ static int usb_standard_get_configuration(usbd_device *usbd_dev,
static int usb_standard_set_interface(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
(void)usbd_dev;
(void)req;
@@ -283,7 +283,7 @@ static int usb_standard_set_interface(usbd_device *usbd_dev,
static int usb_standard_get_interface(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
(void)usbd_dev;
(void)req;
@@ -298,7 +298,7 @@ static int usb_standard_get_interface(usbd_device *usbd_dev,
static int usb_standard_device_get_status(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
(void)usbd_dev;
(void)req;
@@ -316,7 +316,7 @@ static int usb_standard_device_get_status(usbd_device *usbd_dev,
static int usb_standard_interface_get_status(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
(void)usbd_dev;
(void)req;
@@ -333,7 +333,7 @@ static int usb_standard_interface_get_status(usbd_device *usbd_dev,
static int usb_standard_endpoint_get_status(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
(void)req;
@@ -348,7 +348,7 @@ static int usb_standard_endpoint_get_status(usbd_device *usbd_dev,
static int usb_standard_endpoint_stall(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
(void)buf;
(void)len;
@@ -360,7 +360,7 @@ static int usb_standard_endpoint_stall(usbd_device *usbd_dev,
static int usb_standard_endpoint_unstall(usbd_device *usbd_dev,
struct usb_setup_data *req,
u8 **buf, u16 *len)
uint8_t **buf, uint16_t *len)
{
(void)buf;
(void)len;
@@ -374,11 +374,11 @@ static int usb_standard_endpoint_unstall(usbd_device *usbd_dev,
/**@}*/
int _usbd_standard_request_device(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf,
u16 *len)
struct usb_setup_data *req, uint8_t **buf,
uint16_t *len)
{
int (*command)(usbd_device *usbd_dev, struct usb_setup_data *req, u8
**buf, u16 *len) = NULL;
int (*command)(usbd_device *usbd_dev, struct usb_setup_data *req, uint8_t
**buf, uint16_t *len) = NULL;
switch (req->bRequest) {
case USB_REQ_CLEAR_FEATURE:
@@ -428,11 +428,11 @@ int _usbd_standard_request_device(usbd_device *usbd_dev,
}
int _usbd_standard_request_interface(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf,
u16 *len)
struct usb_setup_data *req, uint8_t **buf,
uint16_t *len)
{
int (*command)(usbd_device *usbd_dev, struct usb_setup_data *req,
u8 **buf, u16 *len) = NULL;
uint8_t **buf, uint16_t *len) = NULL;
switch (req->bRequest) {
case USB_REQ_CLEAR_FEATURE:
@@ -458,11 +458,11 @@ int _usbd_standard_request_interface(usbd_device *usbd_dev,
}
int _usbd_standard_request_endpoint(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf,
u16 *len)
struct usb_setup_data *req, uint8_t **buf,
uint16_t *len)
{
int (*command) (usbd_device *usbd_dev, struct usb_setup_data *req,
u8 **buf, u16 *len) = NULL;
uint8_t **buf, uint16_t *len) = NULL;
switch (req->bRequest) {
case USB_REQ_CLEAR_FEATURE:
@@ -495,7 +495,7 @@ int _usbd_standard_request_endpoint(usbd_device *usbd_dev,
}
int _usbd_standard_request(usbd_device *usbd_dev,
struct usb_setup_data *req, u8 **buf, u16 *len)
struct usb_setup_data *req, uint8_t **buf, uint16_t *len)
{
/* FIXME: Have class/vendor requests as well. */
if ((req->bmRequestType & USB_REQ_TYPE_TYPE) != USB_REQ_TYPE_STANDARD) {