Changed to use stdint types.
This commit is contained in:
Piotr Esden-Tempski
@@ -644,31 +644,31 @@ LGPL License Terms @ref lgpl_license
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BEGIN_DECLS
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void can_reset(u32 canport);
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int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
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bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp,
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void can_reset(uint32_t canport);
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int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart,
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bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, uint32_t brp,
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bool loopback, bool silent);
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void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
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u32 fr1, u32 fr2, u32 fifo, bool enable);
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void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
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u16 id2, u16 mask2, u32 fifo, bool enable);
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void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
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u32 fifo, bool enable);
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void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
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u16 id3, u16 id4, u32 fifo, bool enable);
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void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
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u32 fifo, bool enable);
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void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, bool id_list_mode,
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uint32_t fr1, uint32_t fr2, uint32_t fifo, bool enable);
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void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t mask1,
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uint16_t id2, uint16_t mask2, uint32_t fifo, bool enable);
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void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, uint32_t mask,
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uint32_t fifo, bool enable);
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void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, uint16_t id2,
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uint16_t id3, uint16_t id4, uint32_t fifo, bool enable);
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void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, uint32_t id2,
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uint32_t fifo, bool enable);
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void can_enable_irq(u32 canport, u32 irq);
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void can_disable_irq(u32 canport, u32 irq);
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void can_enable_irq(uint32_t canport, uint32_t irq);
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void can_disable_irq(uint32_t canport, uint32_t irq);
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int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data);
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void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
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bool *rtr, u32 *fmi, u8 *length, u8 *data);
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int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, uint8_t length, uint8_t *data);
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void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, bool *ext,
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bool *rtr, uint32_t *fmi, uint8_t *length, uint8_t *data);
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void can_fifo_release(u32 canport, u8 fifo);
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bool can_available_mailbox(u32 canport);
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void can_fifo_release(uint32_t canport, uint8_t fifo);
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bool can_available_mailbox(uint32_t canport);
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END_DECLS
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#endif
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@@ -81,7 +81,7 @@ void crc_reset(void);
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* @param data new word to add to the crc calculator
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* @return final crc calculator value
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*/
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u32 crc_calculate(u32 data);
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uint32_t crc_calculate(uint32_t data);
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/**
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* Add a block of data to the CRC calculator and return the final result
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@@ -89,7 +89,7 @@ u32 crc_calculate(u32 data);
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* @param size length of data, in 32bit increments
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* @return final CRC calculator value
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*/
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u32 crc_calculate_block(u32 *datap, int size);
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uint32_t crc_calculate_block(uint32_t *datap, int size);
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END_DECLS
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@@ -400,12 +400,12 @@ void dac_dma_enable(data_channel dac_channel);
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void dac_dma_disable(data_channel dac_channel);
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void dac_trigger_enable(data_channel dac_channel);
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void dac_trigger_disable(data_channel dac_channel);
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void dac_set_trigger_source(u32 dac_trig_src);
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void dac_set_waveform_generation(u32 dac_wave_ens);
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void dac_set_trigger_source(uint32_t dac_trig_src);
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void dac_set_waveform_generation(uint32_t dac_wave_ens);
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void dac_disable_waveform_generation(data_channel dac_channel);
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void dac_set_waveform_characteristics(u32 dac_mamp);
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void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_channel dac_channel);
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void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2, data_align dac_data_format);
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void dac_set_waveform_characteristics(uint32_t dac_mamp);
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void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format, data_channel dac_channel);
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void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2, data_align dac_data_format);
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void dac_software_trigger(data_channel dac_channel);
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END_DECLS
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@@ -385,31 +385,31 @@ group.
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BEGIN_DECLS
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void dma_channel_reset(u32 dma, u8 channel);
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void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts);
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bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupts);
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void dma_enable_mem2mem_mode(u32 dma, u8 channel);
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void dma_set_priority(u32 dma, u8 channel, u32 prio);
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void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size);
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void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size);
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void dma_enable_memory_increment_mode(u32 dma, u8 channel);
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void dma_disable_memory_increment_mode(u32 dma, u8 channel);
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void dma_enable_peripheral_increment_mode(u32 dma, u8 channel);
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void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
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void dma_enable_circular_mode(u32 dma, u8 channel);
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void dma_set_read_from_peripheral(u32 dma, u8 channel);
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void dma_set_read_from_memory(u32 dma, u8 channel);
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void dma_enable_transfer_error_interrupt(u32 dma, u8 channel);
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void dma_disable_transfer_error_interrupt(u32 dma, u8 channel);
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void dma_enable_half_transfer_interrupt(u32 dma, u8 channel);
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void dma_disable_half_transfer_interrupt(u32 dma, u8 channel);
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void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel);
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void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel);
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void dma_enable_channel(u32 dma, u8 channel);
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void dma_disable_channel(u32 dma, u8 channel);
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void dma_set_peripheral_address(u32 dma, u8 channel, u32 address);
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void dma_set_memory_address(u32 dma, u8 channel, u32 address);
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void dma_set_number_of_data(u32 dma, u8 channel, u16 number);
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void dma_channel_reset(uint32_t dma, uint8_t channel);
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void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, uint32_t interrupts);
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bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts);
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void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel);
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void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio);
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void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size);
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void dma_set_peripheral_size(uint32_t dma, uint8_t channel, uint32_t peripheral_size);
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void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel);
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void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
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void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
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void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
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void dma_enable_circular_mode(uint32_t dma, uint8_t channel);
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void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel);
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void dma_set_read_from_memory(uint32_t dma, uint8_t channel);
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void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel);
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void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel);
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void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel);
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void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel);
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void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
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void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel);
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void dma_enable_channel(uint32_t dma, uint8_t channel);
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void dma_disable_channel(uint32_t dma, uint8_t channel);
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void dma_set_peripheral_address(uint32_t dma, uint8_t channel, uint32_t address);
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void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address);
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void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number);
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END_DECLS
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@@ -572,48 +572,48 @@ BEGIN_DECLS
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* different configuration options.
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*/
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void dma_stream_reset(u32 dma, u8 stream);
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void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts);
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bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt);
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void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction);
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void dma_set_priority(u32 dma, u8 stream, u32 prio);
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void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size);
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void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size);
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void dma_enable_memory_increment_mode(u32 dma, u8 stream);
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void dma_disable_memory_increment_mode(u32 dma, u8 channel);
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void dma_enable_peripheral_increment_mode(u32 dma, u8 stream);
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void dma_disable_peripheral_increment_mode(u32 dma, u8 channel);
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void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream);
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void dma_enable_circular_mode(u32 dma, u8 stream);
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void dma_channel_select(u32 dma, u8 stream, u32 channel);
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void dma_set_memory_burst(u32 dma, u8 stream, u32 burst);
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void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst);
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void dma_set_initial_target(u32 dma, u8 stream, u8 memory);
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u8 dma_get_target(u32 dma, u8 stream);
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void dma_enable_double_buffer_mode(u32 dma, u8 stream);
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void dma_disable_double_buffer_mode(u32 dma, u8 stream);
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void dma_set_peripheral_flow_control(u32 dma, u8 stream);
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void dma_set_dma_flow_control(u32 dma, u8 stream);
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void dma_enable_transfer_error_interrupt(u32 dma, u8 stream);
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void dma_disable_transfer_error_interrupt(u32 dma, u8 stream);
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void dma_enable_half_transfer_interrupt(u32 dma, u8 stream);
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void dma_disable_half_transfer_interrupt(u32 dma, u8 stream);
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void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream);
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void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream);
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u32 dma_fifo_status(u32 dma, u8 stream);
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void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream);
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void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream);
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void dma_enable_fifo_error_interrupt(u32 dma, u8 stream);
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void dma_disable_fifo_error_interrupt(u32 dma, u8 stream);
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void dma_enable_direct_mode(u32 dma, u8 stream);
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void dma_enable_fifo_mode(u32 dma, u8 stream);
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void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold);
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void dma_enable_stream(u32 dma, u8 stream);
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void dma_disable_stream(u32 dma, u8 stream);
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void dma_set_peripheral_address(u32 dma, u8 stream, u32 address);
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void dma_set_memory_address(u32 dma, u8 stream, u32 address);
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void dma_set_memory_address_1(u32 dma, u8 stream, u32 address);
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void dma_set_number_of_data(u32 dma, u8 stream, u16 number);
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void dma_stream_reset(uint32_t dma, uint8_t stream);
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void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, uint32_t interrupts);
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bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt);
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void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction);
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void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio);
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void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size);
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void dma_set_peripheral_size(uint32_t dma, uint8_t stream, uint32_t peripheral_size);
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void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream);
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void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel);
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void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream);
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void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel);
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void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream);
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void dma_enable_circular_mode(uint32_t dma, uint8_t stream);
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void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel);
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void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst);
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void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst);
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void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory);
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uint8_t dma_get_target(uint32_t dma, uint8_t stream);
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void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream);
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void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream);
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void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream);
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void dma_set_dma_flow_control(uint32_t dma, uint8_t stream);
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void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream);
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void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream);
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void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream);
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void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream);
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void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream);
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void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream);
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uint32_t dma_fifo_status(uint32_t dma, uint8_t stream);
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void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream);
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void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream);
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void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream);
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void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream);
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void dma_enable_direct_mode(uint32_t dma, uint8_t stream);
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void dma_enable_fifo_mode(uint32_t dma, uint8_t stream);
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void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold);
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void dma_enable_stream(uint32_t dma, uint8_t stream);
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void dma_disable_stream(uint32_t dma, uint8_t stream);
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void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address);
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void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address);
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void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address);
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void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number);
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END_DECLS
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/**@}*/
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@@ -110,10 +110,10 @@
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/* --- FLASH Keys -----------------------------------------------------------*/
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#define FLASH_KEYR_KEY1 ((u32)0x45670123)
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#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
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#define FLASH_OPTKEYR_KEY1 ((u32)0x08192a3b)
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#define FLASH_OPTKEYR_KEY2 ((u32)0x4c5d6e7f)
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#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
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#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
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#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b)
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#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f)
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/* --- Function prototypes ------------------------------------------------- */
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@@ -127,7 +127,7 @@ void flash_prefetch_enable(void);
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void flash_prefetch_disable(void);
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void flash_dcache_reset(void);
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void flash_icache_reset(void);
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void flash_set_ws(u32 ws);
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void flash_set_ws(uint32_t ws);
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void flash_unlock(void);
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void flash_lock(void);
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void flash_clear_pgserr_flag(void);
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@@ -139,15 +139,15 @@ void flash_clear_bsy_flag(void);
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void flash_clear_status_flags(void);
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void flash_unlock_option_bytes(void);
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void flash_lock_option_bytes(void);
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void flash_erase_all_sectors(u32 program_size);
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void flash_erase_sector(u8 sector, u32 program_size);
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void flash_program_double_word(u32 address, u64 data);
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void flash_program_word(u32 address, u32 data);
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void flash_program_half_word(u32 address, u16 data);
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void flash_program_byte(u32 address, u8 data);
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void flash_program(u32 address, u8 *data, u32 len);
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void flash_erase_all_sectors(uint32_t program_size);
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void flash_erase_sector(uint8_t sector, uint32_t program_size);
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void flash_program_double_word(uint32_t address, uint64_t data);
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void flash_program_word(uint32_t address, uint32_t data);
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void flash_program_half_word(uint32_t address, uint16_t data);
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void flash_program_byte(uint32_t address, uint8_t data);
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void flash_program(uint32_t address, uint8_t *data, uint32_t len);
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void flash_wait_for_last_operation(void);
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void flash_program_option_bytes(u32 data);
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void flash_program_option_bytes(uint32_t data);
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END_DECLS
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@@ -74,13 +74,13 @@ specific memorymap.h header before including this header file.*/
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BEGIN_DECLS
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|
||||
void gpio_set(u32 gpioport, u16 gpios);
|
||||
void gpio_clear(u32 gpioport, u16 gpios);
|
||||
u16 gpio_get(u32 gpioport, u16 gpios);
|
||||
void gpio_toggle(u32 gpioport, u16 gpios);
|
||||
u16 gpio_port_read(u32 gpioport);
|
||||
void gpio_port_write(u32 gpioport, u16 data);
|
||||
void gpio_port_config_lock(u32 gpioport, u16 gpios);
|
||||
void gpio_set(uint32_t gpioport, uint16_t gpios);
|
||||
void gpio_clear(uint32_t gpioport, uint16_t gpios);
|
||||
uint16_t gpio_get(uint32_t gpioport, uint16_t gpios);
|
||||
void gpio_toggle(uint32_t gpioport, uint16_t gpios);
|
||||
uint16_t gpio_port_read(uint32_t gpioport);
|
||||
void gpio_port_write(uint32_t gpioport, uint16_t data);
|
||||
void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -287,9 +287,9 @@ BEGIN_DECLS
|
||||
* sounding functions that have very different functionality.
|
||||
*/
|
||||
|
||||
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
|
||||
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
|
||||
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
|
||||
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios);
|
||||
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios);
|
||||
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios);
|
||||
|
||||
END_DECLS
|
||||
/**@}*/
|
||||
|
||||
@@ -161,15 +161,15 @@ Mikhail Avkhimenia <mikhail@avkhimenia.net>
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void hash_set_mode(u8 mode);
|
||||
void hash_set_algorithm(u8 algorithm);
|
||||
void hash_set_data_type(u8 datatype);
|
||||
void hash_set_key_length(u8 keylength);
|
||||
void hash_set_last_word_valid_bits(u8 validbits);
|
||||
void hash_set_mode(uint8_t mode);
|
||||
void hash_set_algorithm(uint8_t algorithm);
|
||||
void hash_set_data_type(uint8_t datatype);
|
||||
void hash_set_key_length(uint8_t keylength);
|
||||
void hash_set_last_word_valid_bits(uint8_t validbits);
|
||||
void hash_init(void);
|
||||
void hash_add_data(u32 data);
|
||||
void hash_add_data(uint32_t data);
|
||||
void hash_digest(void);
|
||||
void hash_get_result(u32 *data);
|
||||
void hash_get_result(uint32_t *data);
|
||||
|
||||
END_DECLS
|
||||
/**@}*/
|
||||
|
||||
@@ -357,33 +357,33 @@ specific memorymap.h header before including this header file.*/
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void i2c_reset(u32 i2c);
|
||||
void i2c_peripheral_enable(u32 i2c);
|
||||
void i2c_peripheral_disable(u32 i2c);
|
||||
void i2c_send_start(u32 i2c);
|
||||
void i2c_send_stop(u32 i2c);
|
||||
void i2c_clear_stop(u32 i2c);
|
||||
void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave);
|
||||
void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave);
|
||||
void i2c_set_fast_mode(u32 i2c);
|
||||
void i2c_set_standard_mode(u32 i2c);
|
||||
void i2c_set_clock_frequency(u32 i2c, u8 freq);
|
||||
void i2c_set_ccr(u32 i2c, u16 freq);
|
||||
void i2c_set_trise(u32 i2c, u16 trise);
|
||||
void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite);
|
||||
void i2c_send_data(u32 i2c, u8 data);
|
||||
uint8_t i2c_get_data(u32 i2c);
|
||||
void i2c_enable_interrupt(u32 i2c, u32 interrupt);
|
||||
void i2c_disable_interrupt(u32 i2c, u32 interrupt);
|
||||
void i2c_enable_ack(u32 i2c);
|
||||
void i2c_disable_ack(u32 i2c);
|
||||
void i2c_nack_next(u32 i2c);
|
||||
void i2c_nack_current(u32 i2c);
|
||||
void i2c_set_dutycycle(u32 i2c, u32 dutycycle);
|
||||
void i2c_enable_dma(u32 i2c);
|
||||
void i2c_disable_dma(u32 i2c);
|
||||
void i2c_set_dma_last_transfer(u32 i2c);
|
||||
void i2c_clear_dma_last_transfer(u32 i2c);
|
||||
void i2c_reset(uint32_t i2c);
|
||||
void i2c_peripheral_enable(uint32_t i2c);
|
||||
void i2c_peripheral_disable(uint32_t i2c);
|
||||
void i2c_send_start(uint32_t i2c);
|
||||
void i2c_send_stop(uint32_t i2c);
|
||||
void i2c_clear_stop(uint32_t i2c);
|
||||
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave);
|
||||
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave);
|
||||
void i2c_set_fast_mode(uint32_t i2c);
|
||||
void i2c_set_standard_mode(uint32_t i2c);
|
||||
void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq);
|
||||
void i2c_set_ccr(uint32_t i2c, uint16_t freq);
|
||||
void i2c_set_trise(uint32_t i2c, uint16_t trise);
|
||||
void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite);
|
||||
void i2c_send_data(uint32_t i2c, uint8_t data);
|
||||
uint8_t i2c_get_data(uint32_t i2c);
|
||||
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt);
|
||||
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt);
|
||||
void i2c_enable_ack(uint32_t i2c);
|
||||
void i2c_disable_ack(uint32_t i2c);
|
||||
void i2c_nack_next(uint32_t i2c);
|
||||
void i2c_nack_current(uint32_t i2c);
|
||||
void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle);
|
||||
void i2c_enable_dma(uint32_t i2c);
|
||||
void i2c_disable_dma(uint32_t i2c);
|
||||
void i2c_set_dma_last_transfer(uint32_t i2c);
|
||||
void i2c_clear_dma_last_transfer(uint32_t i2c);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -106,7 +106,7 @@ specific memorymap.h header before including this header file.*/
|
||||
BEGIN_DECLS
|
||||
|
||||
void iwdg_start(void);
|
||||
void iwdg_set_period_ms(u32 period);
|
||||
void iwdg_set_period_ms(uint32_t period);
|
||||
bool iwdg_reload_busy(void);
|
||||
bool iwdg_prescaler_busy(void);
|
||||
void iwdg_reset(void);
|
||||
|
||||
@@ -108,7 +108,7 @@ BEGIN_DECLS
|
||||
|
||||
void pwr_disable_backup_domain_write_protect(void);
|
||||
void pwr_enable_backup_domain_write_protect(void);
|
||||
void pwr_enable_power_voltage_detect(u32 pvd_level);
|
||||
void pwr_enable_power_voltage_detect(uint32_t pvd_level);
|
||||
void pwr_disable_power_voltage_detect(void);
|
||||
void pwr_clear_standby_flag(void);
|
||||
void pwr_clear_wakeup_flag(void);
|
||||
|
||||
@@ -330,11 +330,11 @@ specific memorymap.h header before including this header file.*/
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void rtc_set_prescaler(u32 sync, u32 async);
|
||||
void rtc_set_prescaler(uint32_t sync, uint32_t async);
|
||||
void rtc_wait_for_synchro(void);
|
||||
void rtc_lock(void);
|
||||
void rtc_unlock(void);
|
||||
void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel);
|
||||
void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel);
|
||||
void rtc_clear_wakeup_flag(void);
|
||||
|
||||
END_DECLS
|
||||
|
||||
@@ -355,52 +355,52 @@ specific memorymap.h header before including this header file.*/
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void spi_reset(u32 spi_peripheral);
|
||||
int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst);
|
||||
void spi_enable(u32 spi);
|
||||
void spi_disable(u32 spi);
|
||||
u16 spi_clean_disable(u32 spi);
|
||||
void spi_write(u32 spi, u16 data);
|
||||
void spi_send(u32 spi, u16 data);
|
||||
u16 spi_read(u32 spi);
|
||||
u16 spi_xfer(u32 spi, u16 data);
|
||||
void spi_set_bidirectional_mode(u32 spi);
|
||||
void spi_set_unidirectional_mode(u32 spi);
|
||||
void spi_set_bidirectional_receive_only_mode(u32 spi);
|
||||
void spi_set_bidirectional_transmit_only_mode(u32 spi);
|
||||
void spi_enable_crc(u32 spi);
|
||||
void spi_disable_crc(u32 spi);
|
||||
void spi_set_next_tx_from_buffer(u32 spi);
|
||||
void spi_set_next_tx_from_crc(u32 spi);
|
||||
void spi_set_dff_8bit(u32 spi);
|
||||
void spi_set_dff_16bit(u32 spi);
|
||||
void spi_set_full_duplex_mode(u32 spi);
|
||||
void spi_set_receive_only_mode(u32 spi);
|
||||
void spi_disable_software_slave_management(u32 spi);
|
||||
void spi_enable_software_slave_management(u32 spi);
|
||||
void spi_set_nss_high(u32 spi);
|
||||
void spi_set_nss_low(u32 spi);
|
||||
void spi_send_lsb_first(u32 spi);
|
||||
void spi_send_msb_first(u32 spi);
|
||||
void spi_set_baudrate_prescaler(u32 spi, u8 baudrate);
|
||||
void spi_set_master_mode(u32 spi);
|
||||
void spi_set_slave_mode(u32 spi);
|
||||
void spi_set_clock_polarity_1(u32 spi);
|
||||
void spi_set_clock_polarity_0(u32 spi);
|
||||
void spi_set_clock_phase_1(u32 spi);
|
||||
void spi_set_clock_phase_0(u32 spi);
|
||||
void spi_enable_tx_buffer_empty_interrupt(u32 spi);
|
||||
void spi_disable_tx_buffer_empty_interrupt(u32 spi);
|
||||
void spi_enable_rx_buffer_not_empty_interrupt(u32 spi);
|
||||
void spi_disable_rx_buffer_not_empty_interrupt(u32 spi);
|
||||
void spi_enable_error_interrupt(u32 spi);
|
||||
void spi_disable_error_interrupt(u32 spi);
|
||||
void spi_enable_ss_output(u32 spi);
|
||||
void spi_disable_ss_output(u32 spi);
|
||||
void spi_enable_tx_dma(u32 spi);
|
||||
void spi_disable_tx_dma(u32 spi);
|
||||
void spi_enable_rx_dma(u32 spi);
|
||||
void spi_disable_rx_dma(u32 spi);
|
||||
void spi_reset(uint32_t spi_peripheral);
|
||||
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, uint32_t dff, uint32_t lsbfirst);
|
||||
void spi_enable(uint32_t spi);
|
||||
void spi_disable(uint32_t spi);
|
||||
uint16_t spi_clean_disable(uint32_t spi);
|
||||
void spi_write(uint32_t spi, uint16_t data);
|
||||
void spi_send(uint32_t spi, uint16_t data);
|
||||
uint16_t spi_read(uint32_t spi);
|
||||
uint16_t spi_xfer(uint32_t spi, uint16_t data);
|
||||
void spi_set_bidirectional_mode(uint32_t spi);
|
||||
void spi_set_unidirectional_mode(uint32_t spi);
|
||||
void spi_set_bidirectional_receive_only_mode(uint32_t spi);
|
||||
void spi_set_bidirectional_transmit_only_mode(uint32_t spi);
|
||||
void spi_enable_crc(uint32_t spi);
|
||||
void spi_disable_crc(uint32_t spi);
|
||||
void spi_set_next_tx_from_buffer(uint32_t spi);
|
||||
void spi_set_next_tx_from_crc(uint32_t spi);
|
||||
void spi_set_dff_8bit(uint32_t spi);
|
||||
void spi_set_dff_16bit(uint32_t spi);
|
||||
void spi_set_full_duplex_mode(uint32_t spi);
|
||||
void spi_set_receive_only_mode(uint32_t spi);
|
||||
void spi_disable_software_slave_management(uint32_t spi);
|
||||
void spi_enable_software_slave_management(uint32_t spi);
|
||||
void spi_set_nss_high(uint32_t spi);
|
||||
void spi_set_nss_low(uint32_t spi);
|
||||
void spi_send_lsb_first(uint32_t spi);
|
||||
void spi_send_msb_first(uint32_t spi);
|
||||
void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate);
|
||||
void spi_set_master_mode(uint32_t spi);
|
||||
void spi_set_slave_mode(uint32_t spi);
|
||||
void spi_set_clock_polarity_1(uint32_t spi);
|
||||
void spi_set_clock_polarity_0(uint32_t spi);
|
||||
void spi_set_clock_phase_1(uint32_t spi);
|
||||
void spi_set_clock_phase_0(uint32_t spi);
|
||||
void spi_enable_tx_buffer_empty_interrupt(uint32_t spi);
|
||||
void spi_disable_tx_buffer_empty_interrupt(uint32_t spi);
|
||||
void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi);
|
||||
void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi);
|
||||
void spi_enable_error_interrupt(uint32_t spi);
|
||||
void spi_disable_error_interrupt(uint32_t spi);
|
||||
void spi_enable_ss_output(uint32_t spi);
|
||||
void spi_disable_ss_output(uint32_t spi);
|
||||
void spi_enable_tx_dma(uint32_t spi);
|
||||
void spi_disable_tx_dma(uint32_t spi);
|
||||
void spi_enable_rx_dma(uint32_t spi);
|
||||
void spi_disable_rx_dma(uint32_t spi);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -1029,86 +1029,86 @@ enum tim_et_pol {
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void timer_reset(u32 timer_peripheral);
|
||||
void timer_enable_irq(u32 timer_peripheral, u32 irq);
|
||||
void timer_disable_irq(u32 timer_peripheral, u32 irq);
|
||||
bool timer_interrupt_source(u32 timer_peripheral, u32 flag);
|
||||
bool timer_get_flag(u32 timer_peripheral, u32 flag);
|
||||
void timer_clear_flag(u32 timer_peripheral, u32 flag);
|
||||
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
|
||||
u32 alignment, u32 direction);
|
||||
void timer_set_clock_division(u32 timer_peripheral, u32 clock_div);
|
||||
void timer_enable_preload(u32 timer_peripheral);
|
||||
void timer_disable_preload(u32 timer_peripheral);
|
||||
void timer_set_alignment(u32 timer_peripheral, u32 alignment);
|
||||
void timer_direction_up(u32 timer_peripheral);
|
||||
void timer_direction_down(u32 timer_peripheral);
|
||||
void timer_one_shot_mode(u32 timer_peripheral);
|
||||
void timer_continuous_mode(u32 timer_peripheral);
|
||||
void timer_update_on_any(u32 timer_peripheral);
|
||||
void timer_update_on_overflow(u32 timer_peripheral);
|
||||
void timer_enable_update_event(u32 timer_peripheral);
|
||||
void timer_disable_update_event(u32 timer_peripheral);
|
||||
void timer_enable_counter(u32 timer_peripheral);
|
||||
void timer_disable_counter(u32 timer_peripheral);
|
||||
void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs);
|
||||
void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs);
|
||||
void timer_set_ti1_ch123_xor(u32 timer_peripheral);
|
||||
void timer_set_ti1_ch1(u32 timer_peripheral);
|
||||
void timer_set_master_mode(u32 timer_peripheral, u32 mode);
|
||||
void timer_set_dma_on_compare_event(u32 timer_peripheral);
|
||||
void timer_set_dma_on_update_event(u32 timer_peripheral);
|
||||
void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral);
|
||||
void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral);
|
||||
void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral);
|
||||
void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral);
|
||||
void timer_set_prescaler(u32 timer_peripheral, u32 value);
|
||||
void timer_set_repetition_counter(u32 timer_peripheral, u32 value);
|
||||
void timer_set_period(u32 timer_peripheral, u32 period);
|
||||
void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
|
||||
void timer_reset(uint32_t timer_peripheral);
|
||||
void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq);
|
||||
void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq);
|
||||
bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag);
|
||||
bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag);
|
||||
void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag);
|
||||
void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div,
|
||||
uint32_t alignment, uint32_t direction);
|
||||
void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div);
|
||||
void timer_enable_preload(uint32_t timer_peripheral);
|
||||
void timer_disable_preload(uint32_t timer_peripheral);
|
||||
void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment);
|
||||
void timer_direction_up(uint32_t timer_peripheral);
|
||||
void timer_direction_down(uint32_t timer_peripheral);
|
||||
void timer_one_shot_mode(uint32_t timer_peripheral);
|
||||
void timer_continuous_mode(uint32_t timer_peripheral);
|
||||
void timer_update_on_any(uint32_t timer_peripheral);
|
||||
void timer_update_on_overflow(uint32_t timer_peripheral);
|
||||
void timer_enable_update_event(uint32_t timer_peripheral);
|
||||
void timer_disable_update_event(uint32_t timer_peripheral);
|
||||
void timer_enable_counter(uint32_t timer_peripheral);
|
||||
void timer_disable_counter(uint32_t timer_peripheral);
|
||||
void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs);
|
||||
void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs);
|
||||
void timer_set_ti1_ch123_xor(uint32_t timer_peripheral);
|
||||
void timer_set_ti1_ch1(uint32_t timer_peripheral);
|
||||
void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode);
|
||||
void timer_set_dma_on_compare_event(uint32_t timer_peripheral);
|
||||
void timer_set_dma_on_update_event(uint32_t timer_peripheral);
|
||||
void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral);
|
||||
void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral);
|
||||
void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral);
|
||||
void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral);
|
||||
void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value);
|
||||
void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value);
|
||||
void timer_set_period(uint32_t timer_peripheral, uint32_t period);
|
||||
void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
|
||||
enum tim_oc_mode oc_mode);
|
||||
void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value);
|
||||
void timer_enable_break_main_output(u32 timer_peripheral);
|
||||
void timer_disable_break_main_output(u32 timer_peripheral);
|
||||
void timer_enable_break_automatic_output(u32 timer_peripheral);
|
||||
void timer_disable_break_automatic_output(u32 timer_peripheral);
|
||||
void timer_set_break_polarity_high(u32 timer_peripheral);
|
||||
void timer_set_break_polarity_low(u32 timer_peripheral);
|
||||
void timer_enable_break(u32 timer_peripheral);
|
||||
void timer_disable_break(u32 timer_peripheral);
|
||||
void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral);
|
||||
void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral);
|
||||
void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral);
|
||||
void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral);
|
||||
void timer_set_break_lock(u32 timer_peripheral, u32 lock);
|
||||
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
|
||||
void timer_generate_event(u32 timer_peripheral, u32 event);
|
||||
u32 timer_get_counter(u32 timer_peripheral);
|
||||
void timer_set_counter(u32 timer_peripheral, u32 count);
|
||||
void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_polarity_high(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_idle_state_set(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, enum tim_oc_id oc_id);
|
||||
void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, uint32_t value);
|
||||
void timer_enable_break_main_output(uint32_t timer_peripheral);
|
||||
void timer_disable_break_main_output(uint32_t timer_peripheral);
|
||||
void timer_enable_break_automatic_output(uint32_t timer_peripheral);
|
||||
void timer_disable_break_automatic_output(uint32_t timer_peripheral);
|
||||
void timer_set_break_polarity_high(uint32_t timer_peripheral);
|
||||
void timer_set_break_polarity_low(uint32_t timer_peripheral);
|
||||
void timer_enable_break(uint32_t timer_peripheral);
|
||||
void timer_disable_break(uint32_t timer_peripheral);
|
||||
void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral);
|
||||
void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral);
|
||||
void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral);
|
||||
void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral);
|
||||
void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock);
|
||||
void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime);
|
||||
void timer_generate_event(uint32_t timer_peripheral, uint32_t event);
|
||||
uint32_t timer_get_counter(uint32_t timer_peripheral);
|
||||
void timer_set_counter(uint32_t timer_peripheral, uint32_t count);
|
||||
|
||||
void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
|
||||
void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
|
||||
void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in);
|
||||
void timer_ic_enable(u32 timer, enum tim_ic_id ic);
|
||||
void timer_ic_disable(u32 timer, enum tim_ic_id ic);
|
||||
void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic, enum tim_ic_filter flt);
|
||||
void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic, enum tim_ic_psc psc);
|
||||
void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic, enum tim_ic_input in);
|
||||
void timer_ic_enable(uint32_t timer, enum tim_ic_id ic);
|
||||
void timer_ic_disable(uint32_t timer, enum tim_ic_id ic);
|
||||
|
||||
void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt);
|
||||
void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc);
|
||||
void timer_slave_set_polarity(u32 timer, enum tim_et_pol pol);
|
||||
void timer_slave_set_mode(u32 timer, u8 mode);
|
||||
void timer_slave_set_trigger(u32 timer, u8 trigger);
|
||||
void timer_slave_set_filter(uint32_t timer, enum tim_ic_filter flt);
|
||||
void timer_slave_set_prescaler(uint32_t timer, enum tim_ic_psc psc);
|
||||
void timer_slave_set_polarity(uint32_t timer, enum tim_et_pol pol);
|
||||
void timer_slave_set_mode(uint32_t timer, uint8_t mode);
|
||||
void timer_slave_set_trigger(uint32_t timer, uint8_t trigger);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -98,8 +98,8 @@ enum tim_ic_pol {
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void timer_set_option(u32 timer_peripheral, u32 option);
|
||||
void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
|
||||
void timer_set_option(uint32_t timer_peripheral, uint32_t option);
|
||||
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -346,32 +346,32 @@ specific memorymap.h header before including this header file.*/
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void usart_set_baudrate(u32 usart, u32 baud);
|
||||
void usart_set_databits(u32 usart, u32 bits);
|
||||
void usart_set_stopbits(u32 usart, u32 stopbits);
|
||||
void usart_set_parity(u32 usart, u32 parity);
|
||||
void usart_set_mode(u32 usart, u32 mode);
|
||||
void usart_set_flow_control(u32 usart, u32 flowcontrol);
|
||||
void usart_enable(u32 usart);
|
||||
void usart_disable(u32 usart);
|
||||
void usart_send(u32 usart, u16 data);
|
||||
u16 usart_recv(u32 usart);
|
||||
void usart_wait_send_ready(u32 usart);
|
||||
void usart_wait_recv_ready(u32 usart);
|
||||
void usart_send_blocking(u32 usart, u16 data);
|
||||
u16 usart_recv_blocking(u32 usart);
|
||||
void usart_enable_rx_dma(u32 usart);
|
||||
void usart_disable_rx_dma(u32 usart);
|
||||
void usart_enable_tx_dma(u32 usart);
|
||||
void usart_disable_tx_dma(u32 usart);
|
||||
void usart_enable_rx_interrupt(u32 usart);
|
||||
void usart_disable_rx_interrupt(u32 usart);
|
||||
void usart_enable_tx_interrupt(u32 usart);
|
||||
void usart_disable_tx_interrupt(u32 usart);
|
||||
void usart_enable_error_interrupt(u32 usart);
|
||||
void usart_disable_error_interrupt(u32 usart);
|
||||
bool usart_get_flag(u32 usart, u32 flag);
|
||||
bool usart_get_interrupt_source(u32 usart, u32 flag);
|
||||
void usart_set_baudrate(uint32_t usart, uint32_t baud);
|
||||
void usart_set_databits(uint32_t usart, uint32_t bits);
|
||||
void usart_set_stopbits(uint32_t usart, uint32_t stopbits);
|
||||
void usart_set_parity(uint32_t usart, uint32_t parity);
|
||||
void usart_set_mode(uint32_t usart, uint32_t mode);
|
||||
void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol);
|
||||
void usart_enable(uint32_t usart);
|
||||
void usart_disable(uint32_t usart);
|
||||
void usart_send(uint32_t usart, uint16_t data);
|
||||
uint16_t usart_recv(uint32_t usart);
|
||||
void usart_wait_send_ready(uint32_t usart);
|
||||
void usart_wait_recv_ready(uint32_t usart);
|
||||
void usart_send_blocking(uint32_t usart, uint16_t data);
|
||||
uint16_t usart_recv_blocking(uint32_t usart);
|
||||
void usart_enable_rx_dma(uint32_t usart);
|
||||
void usart_disable_rx_dma(uint32_t usart);
|
||||
void usart_enable_tx_dma(uint32_t usart);
|
||||
void usart_disable_tx_dma(uint32_t usart);
|
||||
void usart_enable_rx_interrupt(uint32_t usart);
|
||||
void usart_disable_rx_interrupt(uint32_t usart);
|
||||
void usart_enable_tx_interrupt(uint32_t usart);
|
||||
void usart_disable_tx_interrupt(uint32_t usart);
|
||||
void usart_enable_error_interrupt(uint32_t usart);
|
||||
void usart_disable_error_interrupt(uint32_t usart);
|
||||
bool usart_get_flag(uint32_t usart, uint32_t flag);
|
||||
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -42,14 +42,14 @@ BEGIN_DECLS
|
||||
* Read the onboard flash size
|
||||
* @return flash size in KB
|
||||
*/
|
||||
u16 desig_get_flash_size(void);
|
||||
uint16_t desig_get_flash_size(void);
|
||||
|
||||
/**
|
||||
* Read the full 96 bit unique identifier
|
||||
* Note: ST specifies that bits 31..16 are _also_ reserved for future use
|
||||
* @param result pointer to at least 3xu32s (96 bits)
|
||||
* @param result pointer to at least 3xuint32_ts (96 bits)
|
||||
*/
|
||||
void desig_get_unique_id(u32 result[]);
|
||||
void desig_get_unique_id(uint32_t result[]);
|
||||
|
||||
/**
|
||||
* Read the full 96 bit unique identifier and return it as a
|
||||
|
||||
@@ -66,12 +66,12 @@ typedef enum trigger_e {
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void exti_set_trigger(u32 extis, exti_trigger_type trig);
|
||||
void exti_enable_request(u32 extis);
|
||||
void exti_disable_request(u32 extis);
|
||||
void exti_reset_request(u32 extis);
|
||||
void exti_select_source(u32 exti, u32 gpioport);
|
||||
u32 exti_get_flag_status(u32 exti);
|
||||
void exti_set_trigger(uint32_t extis, exti_trigger_type trig);
|
||||
void exti_enable_request(uint32_t extis);
|
||||
void exti_disable_request(uint32_t extis);
|
||||
void exti_reset_request(uint32_t extis);
|
||||
void exti_select_source(uint32_t exti, uint32_t gpioport);
|
||||
uint32_t exti_get_flag_status(uint32_t exti);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -635,70 +635,70 @@ and ADC2
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void adc_power_on(u32 adc);
|
||||
void adc_start_conversion_direct(u32 adc);
|
||||
void adc_set_single_channel(u32 adc, u8 channel);
|
||||
void adc_set_dual_mode(u32 mode);
|
||||
bool adc_eoc(u32 adc);
|
||||
bool adc_eoc_injected(u32 adc);
|
||||
u32 adc_read_regular(u32 adc);
|
||||
u32 adc_read_injected(u32 adc, u8 reg);
|
||||
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
|
||||
void adc_enable_analog_watchdog_regular(u32 adc);
|
||||
void adc_disable_analog_watchdog_regular(u32 adc);
|
||||
void adc_enable_analog_watchdog_injected(u32 adc);
|
||||
void adc_disable_analog_watchdog_injected(u32 adc);
|
||||
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
|
||||
void adc_disable_discontinuous_mode_regular(u32 adc);
|
||||
void adc_enable_discontinuous_mode_injected(u32 adc);
|
||||
void adc_disable_discontinuous_mode_injected(u32 adc);
|
||||
void adc_enable_automatic_injected_group_conversion(u32 adc);
|
||||
void adc_disable_automatic_injected_group_conversion(u32 adc);
|
||||
void adc_enable_analog_watchdog_on_all_channels(u32 adc);
|
||||
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
|
||||
void adc_enable_scan_mode(u32 adc);
|
||||
void adc_disable_scan_mode(u32 adc);
|
||||
void adc_enable_eoc_interrupt_injected(u32 adc);
|
||||
void adc_disable_eoc_interrupt_injected(u32 adc);
|
||||
void adc_enable_awd_interrupt(u32 adc);
|
||||
void adc_disable_awd_interrupt(u32 adc);
|
||||
void adc_enable_eoc_interrupt(u32 adc);
|
||||
void adc_disable_eoc_interrupt(u32 adc);
|
||||
void adc_enable_temperature_sensor(u32 adc);
|
||||
void adc_disable_temperature_sensor(u32 adc);
|
||||
void adc_start_conversion_regular(u32 adc);
|
||||
void adc_start_conversion_injected(u32 adc);
|
||||
void adc_enable_external_trigger_regular(u32 adc, u32 trigger);
|
||||
void adc_disable_external_trigger_regular(u32 adc);
|
||||
void adc_enable_external_trigger_injected(u32 adc, u32 trigger);
|
||||
void adc_disable_external_trigger_injected(u32 adc);
|
||||
void adc_set_left_aligned(u32 adc);
|
||||
void adc_set_right_aligned(u32 adc);
|
||||
void adc_enable_dma(u32 adc);
|
||||
void adc_disable_dma(u32 adc);
|
||||
void adc_reset_calibration(u32 adc);
|
||||
void adc_calibration(u32 adc);
|
||||
void adc_set_continuous_conversion_mode(u32 adc);
|
||||
void adc_set_single_conversion_mode(u32 adc);
|
||||
void adc_on(u32 adc)
|
||||
void adc_power_on(uint32_t adc);
|
||||
void adc_start_conversion_direct(uint32_t adc);
|
||||
void adc_set_single_channel(uint32_t adc, uint8_t channel);
|
||||
void adc_set_dual_mode(uint32_t mode);
|
||||
bool adc_eoc(uint32_t adc);
|
||||
bool adc_eoc_injected(uint32_t adc);
|
||||
uint32_t adc_read_regular(uint32_t adc);
|
||||
uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
|
||||
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
|
||||
void adc_enable_analog_watchdog_regular(uint32_t adc);
|
||||
void adc_disable_analog_watchdog_regular(uint32_t adc);
|
||||
void adc_enable_analog_watchdog_injected(uint32_t adc);
|
||||
void adc_disable_analog_watchdog_injected(uint32_t adc);
|
||||
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
|
||||
void adc_disable_discontinuous_mode_regular(uint32_t adc);
|
||||
void adc_enable_discontinuous_mode_injected(uint32_t adc);
|
||||
void adc_disable_discontinuous_mode_injected(uint32_t adc);
|
||||
void adc_enable_automatic_injected_group_conversion(uint32_t adc);
|
||||
void adc_disable_automatic_injected_group_conversion(uint32_t adc);
|
||||
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
|
||||
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel);
|
||||
void adc_enable_scan_mode(uint32_t adc);
|
||||
void adc_disable_scan_mode(uint32_t adc);
|
||||
void adc_enable_eoc_interrupt_injected(uint32_t adc);
|
||||
void adc_disable_eoc_interrupt_injected(uint32_t adc);
|
||||
void adc_enable_awd_interrupt(uint32_t adc);
|
||||
void adc_disable_awd_interrupt(uint32_t adc);
|
||||
void adc_enable_eoc_interrupt(uint32_t adc);
|
||||
void adc_disable_eoc_interrupt(uint32_t adc);
|
||||
void adc_enable_temperature_sensor(uint32_t adc);
|
||||
void adc_disable_temperature_sensor(uint32_t adc);
|
||||
void adc_start_conversion_regular(uint32_t adc);
|
||||
void adc_start_conversion_injected(uint32_t adc);
|
||||
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger);
|
||||
void adc_disable_external_trigger_regular(uint32_t adc);
|
||||
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger);
|
||||
void adc_disable_external_trigger_injected(uint32_t adc);
|
||||
void adc_set_left_aligned(uint32_t adc);
|
||||
void adc_set_right_aligned(uint32_t adc);
|
||||
void adc_enable_dma(uint32_t adc);
|
||||
void adc_disable_dma(uint32_t adc);
|
||||
void adc_reset_calibration(uint32_t adc);
|
||||
void adc_calibration(uint32_t adc);
|
||||
void adc_set_continuous_conversion_mode(uint32_t adc);
|
||||
void adc_set_single_conversion_mode(uint32_t adc);
|
||||
void adc_on(uint32_t adc)
|
||||
LIBOPENCM3_DEPRECATED("will be removed in the first release");
|
||||
void adc_off(u32 adc);
|
||||
void adc_set_sample_time(u32 adc, u8 channel, u8 time);
|
||||
void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
|
||||
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
|
||||
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
|
||||
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
|
||||
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
|
||||
void adc_off(uint32_t adc);
|
||||
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
|
||||
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
|
||||
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
|
||||
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
|
||||
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
|
||||
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
|
||||
|
||||
void adc_set_continous_conversion_mode(u32 adc)
|
||||
void adc_set_continous_conversion_mode(uint32_t adc)
|
||||
LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode");
|
||||
void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
|
||||
void adc_set_conversion_time(uint32_t adc, uint8_t channel, uint8_t time)
|
||||
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time");
|
||||
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
|
||||
void adc_set_conversion_time_on_all_channels(uint32_t adc, uint8_t time)
|
||||
LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels");
|
||||
void adc_enable_jeoc_interrupt(u32 adc)
|
||||
void adc_enable_jeoc_interrupt(uint32_t adc)
|
||||
LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected");
|
||||
void adc_disable_jeoc_interrupt(u32 adc)
|
||||
void adc_disable_jeoc_interrupt(uint32_t adc)
|
||||
LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected");
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -202,8 +202,8 @@
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void eth_smi_write(u8 phy, u8 reg, u16 data);
|
||||
u16 eth_smi_read(u8 phy, u8 reg);
|
||||
void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data);
|
||||
uint16_t eth_smi_read(uint8_t phy, uint8_t reg);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -83,9 +83,9 @@
|
||||
|
||||
/* --- FLASH Keys -----------------------------------------------------------*/
|
||||
|
||||
#define FLASH_RDP_KEY ((u16)0x00a5)
|
||||
#define FLASH_KEYR_KEY1 ((u32)0x45670123)
|
||||
#define FLASH_KEYR_KEY2 ((u32)0xcdef89ab)
|
||||
#define FLASH_RDP_KEY ((uint16_t)0x00a5)
|
||||
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123)
|
||||
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab)
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
@@ -95,7 +95,7 @@ void flash_prefetch_buffer_enable(void);
|
||||
void flash_prefetch_buffer_disable(void);
|
||||
void flash_halfcycle_enable(void);
|
||||
void flash_halfcycle_disable(void);
|
||||
void flash_set_ws(u32 ws);
|
||||
void flash_set_ws(uint32_t ws);
|
||||
void flash_unlock(void);
|
||||
void flash_lock(void);
|
||||
void flash_clear_pgerr_flag(void);
|
||||
@@ -103,15 +103,15 @@ void flash_clear_eop_flag(void);
|
||||
void flash_clear_wrprterr_flag(void);
|
||||
void flash_clear_bsy_flag(void);
|
||||
void flash_clear_status_flags(void);
|
||||
u32 flash_get_status_flags(void);
|
||||
uint32_t flash_get_status_flags(void);
|
||||
void flash_unlock_option_bytes(void);
|
||||
void flash_erase_all_pages(void);
|
||||
void flash_erase_page(u32 page_address);
|
||||
void flash_program_word(u32 address, u32 data);
|
||||
void flash_program_half_word(u32 address, u16 data);
|
||||
void flash_erase_page(uint32_t page_address);
|
||||
void flash_program_word(uint32_t address, uint32_t data);
|
||||
void flash_program_half_word(uint32_t address, uint16_t data);
|
||||
void flash_wait_for_last_operation(void);
|
||||
void flash_erase_option_bytes(void);
|
||||
void flash_program_option_bytes(u32 address, u16 data);
|
||||
void flash_program_option_bytes(uint32_t address, uint16_t data);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -948,10 +948,10 @@ Line Devices only
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios);
|
||||
void gpio_set_eventout(u8 evoutport, u8 evoutpin);
|
||||
void gpio_primary_remap(u32 swjenable, u32 maps);
|
||||
void gpio_secondary_remap(u32 maps);
|
||||
void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, uint16_t gpios);
|
||||
void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin);
|
||||
void gpio_primary_remap(uint32_t swjenable, uint32_t maps);
|
||||
void gpio_secondary_remap(uint32_t maps);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -25,9 +25,9 @@
|
||||
/* --- STM32 specific peripheral definitions ------------------------------- */
|
||||
|
||||
/* Memory map for all busses */
|
||||
#define FLASH_BASE ((u32)0x08000000)
|
||||
#define PERIPH_BASE ((u32)0x40000000)
|
||||
#define INFO_BASE ((u32)0x1ffff000)
|
||||
#define FLASH_BASE ((uint32_t)0x08000000)
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000)
|
||||
#define INFO_BASE ((uint32_t)0x1ffff000)
|
||||
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
|
||||
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
|
||||
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)
|
||||
|
||||
@@ -490,8 +490,8 @@ LGPL License Terms @ref lgpl_license
|
||||
#define RCC_CFGR2_PREDIV2_DIV16 0xf
|
||||
|
||||
/* --- Variable definitions ------------------------------------------------ */
|
||||
extern u32 rcc_ppre1_frequency;
|
||||
extern u32 rcc_ppre2_frequency;
|
||||
extern uint32_t rcc_ppre1_frequency;
|
||||
extern uint32_t rcc_ppre2_frequency;
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
@@ -512,28 +512,28 @@ void rcc_osc_on(osc_t osc);
|
||||
void rcc_osc_off(osc_t osc);
|
||||
void rcc_css_enable(void);
|
||||
void rcc_css_disable(void);
|
||||
void rcc_set_mco(u32 mcosrc);
|
||||
void rcc_set_mco(uint32_t mcosrc);
|
||||
void rcc_osc_bypass_enable(osc_t osc);
|
||||
void rcc_osc_bypass_disable(osc_t osc);
|
||||
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
|
||||
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
|
||||
void rcc_set_sysclk_source(u32 clk);
|
||||
void rcc_set_pll_multiplication_factor(u32 mul);
|
||||
void rcc_set_pll2_multiplication_factor(u32 mul);
|
||||
void rcc_set_pll3_multiplication_factor(u32 mul);
|
||||
void rcc_set_pll_source(u32 pllsrc);
|
||||
void rcc_set_pllxtpre(u32 pllxtpre);
|
||||
void rcc_set_adcpre(u32 adcpre);
|
||||
void rcc_set_ppre2(u32 ppre2);
|
||||
void rcc_set_ppre1(u32 ppre1);
|
||||
void rcc_set_hpre(u32 hpre);
|
||||
void rcc_set_usbpre(u32 usbpre);
|
||||
void rcc_set_prediv1(u32 prediv);
|
||||
void rcc_set_prediv2(u32 prediv);
|
||||
void rcc_set_prediv1_source(u32 rccsrc);
|
||||
u32 rcc_system_clock_source(void);
|
||||
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
|
||||
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
|
||||
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
|
||||
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
|
||||
void rcc_set_sysclk_source(uint32_t clk);
|
||||
void rcc_set_pll_multiplication_factor(uint32_t mul);
|
||||
void rcc_set_pll2_multiplication_factor(uint32_t mul);
|
||||
void rcc_set_pll3_multiplication_factor(uint32_t mul);
|
||||
void rcc_set_pll_source(uint32_t pllsrc);
|
||||
void rcc_set_pllxtpre(uint32_t pllxtpre);
|
||||
void rcc_set_adcpre(uint32_t adcpre);
|
||||
void rcc_set_ppre2(uint32_t ppre2);
|
||||
void rcc_set_ppre1(uint32_t ppre1);
|
||||
void rcc_set_hpre(uint32_t hpre);
|
||||
void rcc_set_usbpre(uint32_t usbpre);
|
||||
void rcc_set_prediv1(uint32_t prediv);
|
||||
void rcc_set_prediv2(uint32_t prediv);
|
||||
void rcc_set_prediv1_source(uint32_t rccsrc);
|
||||
uint32_t rcc_system_clock_source(void);
|
||||
void rcc_clock_setup_in_hsi_out_64mhz(void);
|
||||
void rcc_clock_setup_in_hsi_out_48mhz(void);
|
||||
void rcc_clock_setup_in_hsi_out_24mhz(void);
|
||||
|
||||
@@ -150,20 +150,20 @@ BEGIN_DECLS
|
||||
void rtc_awake_from_off(osc_t clock_source);
|
||||
void rtc_enter_config_mode(void);
|
||||
void rtc_exit_config_mode(void);
|
||||
void rtc_set_alarm_time(u32 alarm_time);
|
||||
void rtc_set_alarm_time(uint32_t alarm_time);
|
||||
void rtc_enable_alarm(void);
|
||||
void rtc_disable_alarm(void);
|
||||
void rtc_set_prescale_val(u32 prescale_val);
|
||||
u32 rtc_get_counter_val(void);
|
||||
u32 rtc_get_prescale_div_val(void);
|
||||
u32 rtc_get_alarm_val(void);
|
||||
void rtc_set_counter_val(u32 counter_val);
|
||||
void rtc_set_prescale_val(uint32_t prescale_val);
|
||||
uint32_t rtc_get_counter_val(void);
|
||||
uint32_t rtc_get_prescale_div_val(void);
|
||||
uint32_t rtc_get_alarm_val(void);
|
||||
void rtc_set_counter_val(uint32_t counter_val);
|
||||
void rtc_interrupt_enable(rtcflag_t flag_val);
|
||||
void rtc_interrupt_disable(rtcflag_t flag_val);
|
||||
void rtc_clear_flag(rtcflag_t flag_val);
|
||||
u32 rtc_check_flag(rtcflag_t flag_val);
|
||||
uint32_t rtc_check_flag(rtcflag_t flag_val);
|
||||
void rtc_awake_from_standby(void);
|
||||
void rtc_auto_awake(osc_t clock_source, u32 prescale_val);
|
||||
void rtc_auto_awake(osc_t clock_source, uint32_t prescale_val);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -47,7 +47,7 @@ enum tim_ic_pol {
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
|
||||
void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, enum tim_ic_pol pol);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -49,17 +49,17 @@ LGPL License Terms @ref lgpl_license
|
||||
/* --- USB general registers ----------------------------------------------- */
|
||||
|
||||
/* USB Control register */
|
||||
#define USB_CNTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x40))
|
||||
#define USB_CNTR_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x40))
|
||||
/* USB Interrupt status register */
|
||||
#define USB_ISTR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x44))
|
||||
#define USB_ISTR_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x44))
|
||||
/* USB Frame number register */
|
||||
#define USB_FNR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x48))
|
||||
#define USB_FNR_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x48))
|
||||
/* USB Device address register */
|
||||
#define USB_DADDR_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x4C))
|
||||
#define USB_DADDR_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x4C))
|
||||
/* USB Buffer table address register */
|
||||
#define USB_BTABLE_REG ((volatile u32 *)(USB_DEV_FS_BASE + 0x50))
|
||||
#define USB_BTABLE_REG ((volatile uint32_t *)(USB_DEV_FS_BASE + 0x50))
|
||||
/* USB EP register */
|
||||
#define USB_EP_REG(EP) ((volatile u32 *)(USB_DEV_FS_BASE) + (EP))
|
||||
#define USB_EP_REG(EP) ((volatile uint32_t *)(USB_DEV_FS_BASE) + (EP))
|
||||
|
||||
/* --- USB control register masks / bits ----------------------------------- */
|
||||
|
||||
@@ -245,16 +245,16 @@ LGPL License Terms @ref lgpl_license
|
||||
#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG)
|
||||
|
||||
#define USB_EP_TX_ADDR(EP) \
|
||||
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
|
||||
((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2))
|
||||
|
||||
#define USB_EP_TX_COUNT(EP) \
|
||||
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
|
||||
((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2))
|
||||
|
||||
#define USB_EP_RX_ADDR(EP) \
|
||||
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
|
||||
((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2))
|
||||
|
||||
#define USB_EP_RX_COUNT(EP) \
|
||||
((u32 *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
|
||||
((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2))
|
||||
|
||||
/* --- USB BTABLE manipulators --------------------------------------------- */
|
||||
|
||||
@@ -268,10 +268,10 @@ LGPL License Terms @ref lgpl_license
|
||||
#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT)
|
||||
|
||||
#define USB_GET_EP_TX_BUFF(EP) \
|
||||
(USB_PMA_BASE + (u8 *)(USB_GET_EP_TX_ADDR(EP) * 2))
|
||||
(USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(EP) * 2))
|
||||
|
||||
#define USB_GET_EP_RX_BUFF(EP) \
|
||||
(USB_PMA_BASE + (u8 *)(USB_GET_EP_RX_ADDR(EP) * 2))
|
||||
(USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(EP) * 2))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -28,61 +28,61 @@
|
||||
#define USB_DT_ENDPOINT 0x05
|
||||
|
||||
struct usb_desc_head {
|
||||
u8 length; /* Descriptor size 0x012 */
|
||||
u8 type; /* Descriptor type ID */
|
||||
uint8_t length; /* Descriptor size 0x012 */
|
||||
uint8_t type; /* Descriptor type ID */
|
||||
};
|
||||
|
||||
struct usb_device_desc {
|
||||
struct usb_desc_head h; /* Size 0x12, ID 0x01 */
|
||||
u16 bcd_usb; /* USB Version */
|
||||
u8 class; /* Device class */
|
||||
u8 sub_class; /* Subclass code */
|
||||
u8 protocol; /* Protocol code */
|
||||
u8 max_psize; /* Maximum packet size -> 64bytes */
|
||||
u16 vendor; /* Vendor number */
|
||||
u16 product; /* Device number */
|
||||
u16 bcd_dev; /* Device version */
|
||||
u8 man_desc; /* Index of manufacturer string desc */
|
||||
u8 prod_desc; /* Index of product string desc */
|
||||
u8 sn_desc; /* Index of serial number string desc */
|
||||
u8 num_conf; /* Number of possible configurations */
|
||||
uint16_t bcd_usb; /* USB Version */
|
||||
uint8_t class; /* Device class */
|
||||
uint8_t sub_class; /* Subclass code */
|
||||
uint8_t protocol; /* Protocol code */
|
||||
uint8_t max_psize; /* Maximum packet size -> 64bytes */
|
||||
uint16_t vendor; /* Vendor number */
|
||||
uint16_t product; /* Device number */
|
||||
uint16_t bcd_dev; /* Device version */
|
||||
uint8_t man_desc; /* Index of manufacturer string desc */
|
||||
uint8_t prod_desc; /* Index of product string desc */
|
||||
uint8_t sn_desc; /* Index of serial number string desc */
|
||||
uint8_t num_conf; /* Number of possible configurations */
|
||||
};
|
||||
|
||||
struct usb_conf_desc_header {
|
||||
struct usb_desc_head h; /* Size 0x09, Id 0x02 */
|
||||
u16 tot_leng; /* Total length of data */
|
||||
u8 num_int; /* Number of interfaces */
|
||||
u8 conf_val; /* Configuration selector */
|
||||
u8 conf_desc; /* Index of conf string desc */
|
||||
u8 attr; /* Attribute bitmap:
|
||||
uint16_t tot_leng; /* Total length of data */
|
||||
uint8_t num_int; /* Number of interfaces */
|
||||
uint8_t conf_val; /* Configuration selector */
|
||||
uint8_t conf_desc; /* Index of conf string desc */
|
||||
uint8_t attr; /* Attribute bitmap:
|
||||
* 7 : Bus powered
|
||||
* 6 : Self powered
|
||||
* 5 : Remote wakeup
|
||||
* 4..0 : Reserved -> 0000
|
||||
*/
|
||||
u8 max_power; /* Maximum power consumption in 2mA steps */
|
||||
uint8_t max_power; /* Maximum power consumption in 2mA steps */
|
||||
};
|
||||
|
||||
struct usb_int_desc_header {
|
||||
struct usb_desc_head h; /* Size 0x09, Id 0x04 */
|
||||
u8 iface_num; /* Interface id number */
|
||||
u8 alt_setting; /* Alternative setting selector */
|
||||
u8 num_endp; /* Endpoints used */
|
||||
u8 class; /* Interface class */
|
||||
u8 sub_class; /* Subclass code */
|
||||
u8 protocol; /* Protocol code */
|
||||
u8 iface_desc; /* Index of interface string desc */
|
||||
uint8_t iface_num; /* Interface id number */
|
||||
uint8_t alt_setting; /* Alternative setting selector */
|
||||
uint8_t num_endp; /* Endpoints used */
|
||||
uint8_t class; /* Interface class */
|
||||
uint8_t sub_class; /* Subclass code */
|
||||
uint8_t protocol; /* Protocol code */
|
||||
uint8_t iface_desc; /* Index of interface string desc */
|
||||
};
|
||||
|
||||
struct usb_ep_desc {
|
||||
struct usb_desc_head h; /* Size 0x07, Id 0x05 */
|
||||
u8 ep_addr; /* Endpoint address:
|
||||
uint8_t ep_addr; /* Endpoint address:
|
||||
0..3 : Endpoint Number
|
||||
4..6 : Reserved -> 0
|
||||
7 : Direction 0=out 1=in */
|
||||
u8 ep_attr; /* Endpoint attributes */
|
||||
u16 max_psize; /* Maximum packet size -> 64bytes */
|
||||
u8 interval; /* Interval for polling endpoint
|
||||
uint8_t ep_attr; /* Endpoint attributes */
|
||||
uint16_t max_psize; /* Maximum packet size -> 64bytes */
|
||||
uint8_t interval; /* Interval for polling endpoint
|
||||
data. Ignored for bulk & control
|
||||
endpoints. */
|
||||
};
|
||||
@@ -95,7 +95,7 @@ struct usb_conf_desc {
|
||||
|
||||
struct usb_string_desc {
|
||||
struct usb_desc_head h; /* Size > 0x02, Id 0x03 */
|
||||
u16 string[]; /* String UTF16 encoded */
|
||||
uint16_t string[]; /* String UTF16 encoded */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -450,8 +450,8 @@
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6
|
||||
|
||||
/* --- Variable definitions ------------------------------------------------ */
|
||||
extern u32 rcc_ppre1_frequency;
|
||||
extern u32 rcc_ppre2_frequency;
|
||||
extern uint32_t rcc_ppre1_frequency;
|
||||
extern uint32_t rcc_ppre2_frequency;
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
@@ -495,19 +495,19 @@ void rcc_css_enable(void);
|
||||
void rcc_css_disable(void);
|
||||
void rcc_osc_bypass_enable(osc_t osc);
|
||||
void rcc_osc_bypass_disable(osc_t osc);
|
||||
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
|
||||
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
|
||||
void rcc_set_sysclk_source(u32 clk);
|
||||
void rcc_set_pll_source(u32 pllsrc);
|
||||
void rcc_set_ppre2(u32 ppre2);
|
||||
void rcc_set_ppre1(u32 ppre1);
|
||||
void rcc_set_hpre(u32 hpre);
|
||||
void rcc_set_rtcpre(u32 rtcpre);
|
||||
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq);
|
||||
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq);
|
||||
u32 rcc_system_clock_source(void);
|
||||
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
|
||||
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
|
||||
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
|
||||
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
|
||||
void rcc_set_sysclk_source(uint32_t clk);
|
||||
void rcc_set_pll_source(uint32_t pllsrc);
|
||||
void rcc_set_ppre2(uint32_t ppre2);
|
||||
void rcc_set_ppre1(uint32_t ppre1);
|
||||
void rcc_set_hpre(uint32_t hpre);
|
||||
void rcc_set_rtcpre(uint32_t rtcpre);
|
||||
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
|
||||
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
|
||||
uint32_t rcc_system_clock_source(void);
|
||||
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
|
||||
void rcc_backupdomain_reset(void);
|
||||
|
||||
|
||||
@@ -791,64 +791,64 @@ injected channels.
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void adc_power_on(u32 adc);
|
||||
void adc_off(u32 adc);
|
||||
void adc_enable_analog_watchdog_regular(u32 adc);
|
||||
void adc_disable_analog_watchdog_regular(u32 adc);
|
||||
void adc_enable_analog_watchdog_injected(u32 adc);
|
||||
void adc_disable_analog_watchdog_injected(u32 adc);
|
||||
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
|
||||
void adc_disable_discontinuous_mode_regular(u32 adc);
|
||||
void adc_enable_discontinuous_mode_injected(u32 adc);
|
||||
void adc_disable_discontinuous_mode_injected(u32 adc);
|
||||
void adc_enable_automatic_injected_group_conversion(u32 adc);
|
||||
void adc_disable_automatic_injected_group_conversion(u32 adc);
|
||||
void adc_enable_analog_watchdog_on_all_channels(u32 adc);
|
||||
void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
|
||||
void adc_enable_scan_mode(u32 adc);
|
||||
void adc_disable_scan_mode(u32 adc);
|
||||
void adc_enable_eoc_interrupt_injected(u32 adc);
|
||||
void adc_disable_eoc_interrupt_injected(u32 adc);
|
||||
void adc_enable_awd_interrupt(u32 adc);
|
||||
void adc_disable_awd_interrupt(u32 adc);
|
||||
void adc_enable_eoc_interrupt(u32 adc);
|
||||
void adc_disable_eoc_interrupt(u32 adc);
|
||||
void adc_start_conversion_regular(u32 adc);
|
||||
void adc_start_conversion_injected(u32 adc);
|
||||
void adc_disable_external_trigger_regular(u32 adc);
|
||||
void adc_disable_external_trigger_injected(u32 adc);
|
||||
void adc_set_left_aligned(u32 adc);
|
||||
void adc_set_right_aligned(u32 adc);
|
||||
void adc_enable_dma(u32 adc);
|
||||
void adc_disable_dma(u32 adc);
|
||||
void adc_set_continuous_conversion_mode(u32 adc);
|
||||
void adc_set_single_conversion_mode(u32 adc);
|
||||
void adc_set_sample_time(u32 adc, u8 channel, u8 time);
|
||||
void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
|
||||
void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
|
||||
void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
|
||||
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
|
||||
void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
|
||||
bool adc_eoc(u32 adc);
|
||||
bool adc_eoc_injected(u32 adc);
|
||||
u32 adc_read_regular(u32 adc);
|
||||
u32 adc_read_injected(u32 adc, u8 reg);
|
||||
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
|
||||
void adc_power_on(uint32_t adc);
|
||||
void adc_off(uint32_t adc);
|
||||
void adc_enable_analog_watchdog_regular(uint32_t adc);
|
||||
void adc_disable_analog_watchdog_regular(uint32_t adc);
|
||||
void adc_enable_analog_watchdog_injected(uint32_t adc);
|
||||
void adc_disable_analog_watchdog_injected(uint32_t adc);
|
||||
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length);
|
||||
void adc_disable_discontinuous_mode_regular(uint32_t adc);
|
||||
void adc_enable_discontinuous_mode_injected(uint32_t adc);
|
||||
void adc_disable_discontinuous_mode_injected(uint32_t adc);
|
||||
void adc_enable_automatic_injected_group_conversion(uint32_t adc);
|
||||
void adc_disable_automatic_injected_group_conversion(uint32_t adc);
|
||||
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
|
||||
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel);
|
||||
void adc_enable_scan_mode(uint32_t adc);
|
||||
void adc_disable_scan_mode(uint32_t adc);
|
||||
void adc_enable_eoc_interrupt_injected(uint32_t adc);
|
||||
void adc_disable_eoc_interrupt_injected(uint32_t adc);
|
||||
void adc_enable_awd_interrupt(uint32_t adc);
|
||||
void adc_disable_awd_interrupt(uint32_t adc);
|
||||
void adc_enable_eoc_interrupt(uint32_t adc);
|
||||
void adc_disable_eoc_interrupt(uint32_t adc);
|
||||
void adc_start_conversion_regular(uint32_t adc);
|
||||
void adc_start_conversion_injected(uint32_t adc);
|
||||
void adc_disable_external_trigger_regular(uint32_t adc);
|
||||
void adc_disable_external_trigger_injected(uint32_t adc);
|
||||
void adc_set_left_aligned(uint32_t adc);
|
||||
void adc_set_right_aligned(uint32_t adc);
|
||||
void adc_enable_dma(uint32_t adc);
|
||||
void adc_disable_dma(uint32_t adc);
|
||||
void adc_set_continuous_conversion_mode(uint32_t adc);
|
||||
void adc_set_single_conversion_mode(uint32_t adc);
|
||||
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time);
|
||||
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time);
|
||||
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold);
|
||||
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold);
|
||||
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
|
||||
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]);
|
||||
bool adc_eoc(uint32_t adc);
|
||||
bool adc_eoc_injected(uint32_t adc);
|
||||
uint32_t adc_read_regular(uint32_t adc);
|
||||
uint32_t adc_read_injected(uint32_t adc, uint8_t reg);
|
||||
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
|
||||
|
||||
void adc_set_clk_prescale(u32 prescaler);
|
||||
void adc_set_multi_mode(u32 mode);
|
||||
void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity);
|
||||
void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity);
|
||||
void adc_set_resolution(u32 adc, u16 resolution);
|
||||
void adc_enable_overrun_interrupt(u32 adc);
|
||||
void adc_disable_overrun_interrupt(u32 adc);
|
||||
bool adc_get_overrun_flag(u32 adc);
|
||||
void adc_clear_overrun_flag(u32 adc);
|
||||
bool adc_awd(u32 adc);
|
||||
void adc_eoc_after_each(u32 adc);
|
||||
void adc_eoc_after_group(u32 adc);
|
||||
void adc_set_dma_continue(u32 adc);
|
||||
void adc_set_dma_terminate(u32 adc);
|
||||
void adc_set_clk_prescale(uint32_t prescaler);
|
||||
void adc_set_multi_mode(uint32_t mode);
|
||||
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity);
|
||||
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity);
|
||||
void adc_set_resolution(uint32_t adc, uint16_t resolution);
|
||||
void adc_enable_overrun_interrupt(uint32_t adc);
|
||||
void adc_disable_overrun_interrupt(uint32_t adc);
|
||||
bool adc_get_overrun_flag(uint32_t adc);
|
||||
void adc_clear_overrun_flag(uint32_t adc);
|
||||
bool adc_awd(uint32_t adc);
|
||||
void adc_eoc_after_each(uint32_t adc);
|
||||
void adc_eoc_after_group(uint32_t adc);
|
||||
void adc_set_dma_continue(uint32_t adc);
|
||||
void adc_set_dma_terminate(uint32_t adc);
|
||||
void adc_enable_temperature_sensor(void);
|
||||
void adc_disable_temperature_sensor(void);
|
||||
|
||||
|
||||
@@ -451,8 +451,8 @@
|
||||
#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6
|
||||
|
||||
/* --- Variable definitions ------------------------------------------------ */
|
||||
extern u32 rcc_ppre1_frequency;
|
||||
extern u32 rcc_ppre2_frequency;
|
||||
extern uint32_t rcc_ppre1_frequency;
|
||||
extern uint32_t rcc_ppre2_frequency;
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
@@ -501,19 +501,19 @@ void rcc_css_enable(void);
|
||||
void rcc_css_disable(void);
|
||||
void rcc_osc_bypass_enable(osc_t osc);
|
||||
void rcc_osc_bypass_disable(osc_t osc);
|
||||
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
|
||||
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
|
||||
void rcc_set_sysclk_source(u32 clk);
|
||||
void rcc_set_pll_source(u32 pllsrc);
|
||||
void rcc_set_ppre2(u32 ppre2);
|
||||
void rcc_set_ppre1(u32 ppre1);
|
||||
void rcc_set_hpre(u32 hpre);
|
||||
void rcc_set_rtcpre(u32 rtcpre);
|
||||
void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq);
|
||||
void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq);
|
||||
u32 rcc_system_clock_source(void);
|
||||
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
|
||||
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
|
||||
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
|
||||
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
|
||||
void rcc_set_sysclk_source(uint32_t clk);
|
||||
void rcc_set_pll_source(uint32_t pllsrc);
|
||||
void rcc_set_ppre2(uint32_t ppre2);
|
||||
void rcc_set_ppre1(uint32_t ppre1);
|
||||
void rcc_set_hpre(uint32_t hpre);
|
||||
void rcc_set_rtcpre(uint32_t rtcpre);
|
||||
void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
|
||||
void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq);
|
||||
uint32_t rcc_system_clock_source(void);
|
||||
void rcc_clock_setup_hse_3v3(const clock_scale_t *clock);
|
||||
void rcc_backupdomain_reset(void);
|
||||
|
||||
|
||||
@@ -69,20 +69,20 @@
|
||||
#define FLASH_PECR_PELOCK (1 << 0)
|
||||
|
||||
/* Power down key register (FLASH_PDKEYR) */
|
||||
#define FLASH_PDKEYR_PDKEY1 ((u32)0x04152637)
|
||||
#define FLASH_PDKEYR_PDKEY2 ((u32)0xFAFBFCFD)
|
||||
#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637)
|
||||
#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xFAFBFCFD)
|
||||
|
||||
/* Program/erase key register (FLASH_PEKEYR) */
|
||||
#define FLASH_PEKEYR_PEKEY1 ((u32)0x89ABCDEF)
|
||||
#define FLASH_PEKEYR_PEKEY2 ((u32)0x02030405)
|
||||
#define FLASH_PEKEYR_PEKEY1 ((uint32_t)0x89ABCDEF)
|
||||
#define FLASH_PEKEYR_PEKEY2 ((uint32_t)0x02030405)
|
||||
|
||||
/* Program memory key register (FLASH_PRGKEYR) */
|
||||
#define FLASH_PRGKEYR_PRGKEY1 ((u32)0x8C9DAEBF)
|
||||
#define FLASH_PRGKEYR_PRGKEY2 ((u32)0x13141516)
|
||||
#define FLASH_PRGKEYR_PRGKEY1 ((uint32_t)0x8C9DAEBF)
|
||||
#define FLASH_PRGKEYR_PRGKEY2 ((uint32_t)0x13141516)
|
||||
|
||||
/* Option byte key register (FLASH_OPTKEYR) */
|
||||
#define FLASH_OPTKEYR_OPTKEY1 ((u32)0xFBEAD9C8)
|
||||
#define FLASH_OPTKEYR_OPTKEY2 ((u32)0x24252627)
|
||||
#define FLASH_OPTKEYR_OPTKEY1 ((uint32_t)0xFBEAD9C8)
|
||||
#define FLASH_OPTKEYR_OPTKEY2 ((uint32_t)0x24252627)
|
||||
|
||||
|
||||
/* --- FLASH_SR values ----------------------------------------------------- */
|
||||
@@ -119,7 +119,7 @@ void flash_64bit_enable(void);
|
||||
void flash_64bit_disable(void);
|
||||
void flash_prefetch_enable(void);
|
||||
void flash_prefetch_disable(void);
|
||||
void flash_set_ws(u32 ws);
|
||||
void flash_set_ws(uint32_t ws);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -251,9 +251,9 @@ BEGIN_DECLS
|
||||
* TODO: this should all really be moved to a "common" gpio header
|
||||
*/
|
||||
|
||||
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
|
||||
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
|
||||
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
|
||||
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios);
|
||||
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios);
|
||||
void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -26,8 +26,8 @@
|
||||
/* --- STM32 specific peripheral definitions ------------------------------- */
|
||||
|
||||
/* Memory map for all busses */
|
||||
#define PERIPH_BASE ((u32)0x40000000)
|
||||
#define INFO_BASE ((u32)0x1ff00000)
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000)
|
||||
#define INFO_BASE ((uint32_t)0x1ff00000)
|
||||
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
|
||||
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
|
||||
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000)
|
||||
|
||||
@@ -412,8 +412,8 @@ extern const clock_scale_t clock_config[CLOCK_CONFIG_END];
|
||||
|
||||
|
||||
/* --- Variable definitions ------------------------------------------------ */
|
||||
extern u32 rcc_ppre1_frequency;
|
||||
extern u32 rcc_ppre2_frequency;
|
||||
extern uint32_t rcc_ppre1_frequency;
|
||||
extern uint32_t rcc_ppre2_frequency;
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
@@ -437,21 +437,21 @@ void rcc_css_enable(void);
|
||||
void rcc_css_disable(void);
|
||||
void rcc_osc_bypass_enable(osc_t osc);
|
||||
void rcc_osc_bypass_disable(osc_t osc);
|
||||
void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en);
|
||||
void rcc_peripheral_reset(volatile u32 *reg, u32 reset);
|
||||
void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset);
|
||||
void rcc_set_sysclk_source(u32 clk);
|
||||
void rcc_set_pll_configuration(u32 source, u32 multiplier, u32 divisor);
|
||||
void rcc_set_pll_source(u32 pllsrc);
|
||||
void rcc_set_adcpre(u32 adcpre);
|
||||
void rcc_set_ppre2(u32 ppre2);
|
||||
void rcc_set_ppre1(u32 ppre1);
|
||||
void rcc_set_hpre(u32 hpre);
|
||||
void rcc_set_usbpre(u32 usbpre);
|
||||
void rcc_set_rtcpre(u32 rtcpre);
|
||||
u32 rcc_system_clock_source(void);
|
||||
void rcc_rtc_select_clock(u32 clock);
|
||||
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
|
||||
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
|
||||
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
|
||||
void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset);
|
||||
void rcc_set_sysclk_source(uint32_t clk);
|
||||
void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, uint32_t divisor);
|
||||
void rcc_set_pll_source(uint32_t pllsrc);
|
||||
void rcc_set_adcpre(uint32_t adcpre);
|
||||
void rcc_set_ppre2(uint32_t ppre2);
|
||||
void rcc_set_ppre1(uint32_t ppre1);
|
||||
void rcc_set_hpre(uint32_t hpre);
|
||||
void rcc_set_usbpre(uint32_t usbpre);
|
||||
void rcc_set_rtcpre(uint32_t rtcpre);
|
||||
uint32_t rcc_system_clock_source(void);
|
||||
void rcc_rtc_select_clock(uint32_t clock);
|
||||
void rcc_clock_setup_msi(const clock_scale_t *clock);
|
||||
void rcc_clock_setup_hsi(const clock_scale_t *clock);
|
||||
void rcc_clock_setup_pll(const clock_scale_t *clock);
|
||||
|
||||
@@ -82,7 +82,7 @@ Trigger 1 Remap
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void timer_set_option(u32 timer_peripheral, u32 option);
|
||||
void timer_set_option(uint32_t timer_peripheral, uint32_t option);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -89,7 +89,7 @@
|
||||
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00)
|
||||
|
||||
/* Data FIFO */
|
||||
#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + \
|
||||
#define OTG_FS_FIFO(x) ((volatile uint32_t*)(USB_OTG_FS_BASE + \
|
||||
(((x) + 1) << 12)))
|
||||
|
||||
/* Global CSRs */
|
||||
|
||||
@@ -145,7 +145,7 @@
|
||||
#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
|
||||
|
||||
/* Data FIFO */
|
||||
#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + \
|
||||
#define OTG_HS_FIFO(x) ((volatile uint32_t*)(USB_OTG_HS_BASE + \
|
||||
OTG_FIFO(x)))
|
||||
|
||||
/* Global CSRs */
|
||||
|
||||
@@ -25,10 +25,10 @@
|
||||
*/
|
||||
|
||||
/* Get register content. */
|
||||
#define GET_REG(REG) ((u16) *REG)
|
||||
#define GET_REG(REG) ((uint16_t) *REG)
|
||||
|
||||
/* Set register content. */
|
||||
#define SET_REG(REG, VAL) (*REG = (u16)VAL)
|
||||
#define SET_REG(REG, VAL) (*REG = (uint16_t)VAL)
|
||||
|
||||
/* Clear register bit. */
|
||||
#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT))
|
||||
@@ -52,8 +52,8 @@
|
||||
*/
|
||||
#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \
|
||||
do { \
|
||||
register u16 toggle_mask = GET_REG(REG) & (MSK); \
|
||||
register u16 bit_selector; \
|
||||
register uint16_t toggle_mask = GET_REG(REG) & (MSK); \
|
||||
register uint16_t bit_selector; \
|
||||
for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \
|
||||
if ((bit_selector & (BIT)) != 0) \
|
||||
toggle_mask ^= bit_selector; \
|
||||
|
||||
Reference in New Issue
Block a user