From 345b20fb9f0d5c4ef5fdef3f2ab7fad5c09df622 Mon Sep 17 00:00:00 2001 From: dragonmux Date: Tue, 26 Sep 2023 21:43:00 +0100 Subject: [PATCH] stm32/timer: Moved the OC4 mode logic into its own function --- lib/stm32/common/timer_common_all.c | 66 +++++++++++++++-------------- 1 file changed, 35 insertions(+), 31 deletions(-) diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c index 3f9129ee..5a2bfa05 100644 --- a/lib/stm32/common/timer_common_all.c +++ b/lib/stm32/common/timer_common_all.c @@ -932,6 +932,40 @@ void timer_set_oc3_mode(uint32_t timer_peripheral, enum tim_oc_mode oc_mode) } } +void timer_set_oc4_mode(uint32_t timer_peripheral, enum tim_oc_mode oc_mode) +{ + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK; + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC4S_OUT; + TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR2(timer_peripheral) |= + TIM_CCMR2_OC4M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2; + break; + } +} + /*---------------------------------------------------------------------------*/ /** @brief Timer Set Output Compare Mode @@ -973,36 +1007,7 @@ void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, timer_set_oc3_mode(timer_peripheral, oc_mode); break; case TIM_OC4: - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK; - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC4S_OUT; - TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK; - switch (oc_mode) { - case TIM_OCM_FROZEN: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN; - break; - case TIM_OCM_ACTIVE: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE; - break; - case TIM_OCM_INACTIVE: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE; - break; - case TIM_OCM_TOGGLE: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE; - break; - case TIM_OCM_FORCE_LOW: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW; - break; - case TIM_OCM_FORCE_HIGH: - TIM_CCMR2(timer_peripheral) |= - TIM_CCMR2_OC4M_FORCE_HIGH; - break; - case TIM_OCM_PWM1: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1; - break; - case TIM_OCM_PWM2: - TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2; - break; - } + timer_set_oc4_mode(timer_peripheral, oc_mode); break; case TIM_OC1N: case TIM_OC2N: @@ -1899,4 +1904,3 @@ void timer_slave_set_extclockmode2(uint32_t timer_peripheral, /* TODO Timer DMA burst */ /**@}*/ -