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gd32: add new chip series f1x0

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GD32F1X0 (X can be 3, 5, 7 and 9) is a series of Cortex-M3 MCUs by
GigaDevice, which features pin-to-pin package compatibility with
STM32F030 MCU line. F150 adds USB support to F130, and F170/F190 adds
CAN support.

Currently the code mainly targets GD32F130 and F150 chips. Some register
are different between F130/150 and F170/190, just like the difference
between STM32F1 Performance line and Connectivity line.

From the perspective of registers and memory map, GD32F1X0 seems like a
mixture between STM32F1 and STM32F0 (because it is designed to be
pin-to-pin compatible with F0, but with Cortex-M3 like F1). A bunch of
code are shared between STM32 and GD32, and these code are specially
processed to include the GD32 headers instead of STM32 headers when meet
GD32F1X0.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Reviewed-by: Karl Palsson <karlp@tweak.net.au>
gd32/rcc.[ch] are forks of stm32f1/rcc
gd32/flash.[ch] are forks of stm32f0/flash
No attempts at deduplicating this have been done at this stage.  We can
see where they move in the future.
This commit is contained in:
Icenowy Zheng
2019-01-30 01:14:06 +08:00
committed by Karl Palsson
parent d109a1ddeb
commit 330d5fd5be
21 changed files with 1873 additions and 0 deletions
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1
Makefile
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@@ -29,6 +29,7 @@ SRCLIBDIR:= $(subst $(space),\$(space),$(realpath lib))
TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \
stm32/l0 stm32/l1 stm32/l4 \
gd32/f1x0 \
lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 \
lm3s lm4f msp432/e4 \
efm32/tg efm32/g efm32/lg efm32/gg efm32/hg efm32/wg \