STM32H7: Implement basic FDCAN support
Add stm32h7 support for FDCAN peripheral. Source level compatibility is provided with stm32g4. Additional features of stm32h7 such as configurable buffers are supported. Implementation offers feature parity with stm32g4 implementation.
This commit is contained in:
Eduard Drusa
committed by
Karl Palsson
Karl Palsson
parent
0d72e6739c
commit
32354846bd
@@ -1,17 +1,7 @@
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/** @defgroup fdcan_defines FDCAN Defines
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@ingroup STM32G_defines
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@brief <b>libopencm3 Defined Constants and Types for STM32 FD-CAN</b>
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@author @htmlonly © @endhtmlonly 2021 Eduard Drusa <ventyl8 at netkosice dot sk>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2021 Eduard Drusa <ventyl86@netkosice.sk>
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* Copyright (C) 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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@@ -27,26 +17,20 @@ LGPL License Terms @ref lgpl_license
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_FDCAN_H
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#define LIBOPENCM3_FDCAN_H
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#pragma once
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/** @{ */
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#if defined(STM32G4)
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# include <libopencm3/stm32/g4/fdcan.h>
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#elif defined(STM32H7)
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# include <libopencm3/stm32/h7/fdcan.h>
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#endif
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/* FDCAN block base addresses. Used in functions to identify FDCAN block being manipulated. */
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/** @defgroup fdcan_block FDCAN block base addresses
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/** @addtogroup fdcan_defines
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* @{
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*/
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#define CAN1 FDCAN1_BASE
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#define CAN2 FDCAN2_BASE
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#define CAN3 FDCAN3_BASE
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/**@}*/
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/** @defgroup fdcan_fifo Named constants for FIFOs
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* @{
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@@ -55,6 +39,7 @@ LGPL License Terms @ref lgpl_license
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#define FDCAN_FIFO1 1
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/**@}*/
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#define FDCAN_BLOCK_ID(can_base) (((can_base) - CAN1)/(CAN2 - CAN1))
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/** @defgroup FDCAN registers file in each FDCAN block. */
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@@ -76,38 +61,29 @@ LGPL License Terms @ref lgpl_license
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#define FDCAN_IE(can_base) MMIO32(can_base + 0x0054)
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#define FDCAN_ILS(can_base) MMIO32(can_base + 0x0058)
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#define FDCAN_ILE(can_base) MMIO32(can_base + 0x005C)
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#define FDCAN_RXGFC(can_base) MMIO32(can_base + 0x0080)
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#define FDCAN_XIDAM(can_base) MMIO32(can_base + 0x0084)
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#define FDCAN_HPMS(can_base) MMIO32(can_base + 0x0088)
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/** Generic access to Rx FIFO status registers.
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* @param can_base FDCAN block base address @ref fdcan_block
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* @param fifo_id ID of FIFO, 0 or 1
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*/
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#define FDCAN_RXFIS(can_base, fifo_id) MMIO32(can_base + 0x0090 + (8 * fifo_id))
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#define FDCAN_RXFIS(can_base, fifo_id) \
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MMIO32(can_base + FDCAN_RXFIS_BASE + (FDCAN_RXFI_OFFSET * fifo_id))
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#define FDCAN_RXF0S(can_base) FDCAN_RXFIS(can_base, 0)
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#define FDCAN_RXF1S(can_base) FDCAN_RXFIS(can_base, 1)
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/** Generic access to Rx FIFO acknowledge registers.
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* @param can_base FDCAN block base address @ref fdcan_block
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* @param fifo_id ID of FIFO, 0 or 1
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*/
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#define FDCAN_RXFIA(can_base, fifo_id) MMIO32(can_base + 0x0094 + (8 * fifo_id))
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#define FDCAN_RXFIA(can_base, fifo_id) MMIO32(can_base + 0x0094 + (FDCAN_RXFI_OFFSET * fifo_id))
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#define FDCAN_RXF0A(can_base) FDCAN_RXFIA(can_base, 0)
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#define FDCAN_RXF1A(can_base) FDCAN_RXFIA(can_base, 1)
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#define FDCAN_TXBC(can_base) MMIO32(can_base + 0x00C0)
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#define FDCAN_TXFQS(can_base) MMIO32(can_base + 0x00C4)
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#define FDCAN_TXBRP(can_base) MMIO32(can_base + 0x00C8)
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#define FDCAN_TXBAR(can_base) MMIO32(can_base + 0x00CC)
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#define FDCAN_TXBCR(can_base) MMIO32(can_base + 0x00D0)
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#define FDCAN_TXBTO(can_base) MMIO32(can_base + 0x00D4)
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#define FDCAN_TXBCF(can_base) MMIO32(can_base + 0x00D8)
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#define FDCAN_TXBTIE(can_base) MMIO32(can_base + 0x00DC)
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#define FDCAN_TXBCIE(can_base) MMIO32(can_base + 0x00E0)
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#define FDCAN_TXEFS(can_base) MMIO32(can_base + 0x00E4)
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#define FDCAN_TXEFA(can_base) MMIO32(can_base + 0x00E8)
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#define FDCAN_CKDIV(can_base) MMIO32(can_base + 0x0100)
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/* DAY[7:0]: FDCAN core revision date */
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#define FDCAN_CREL_DAY_SHIFT 0
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@@ -360,26 +336,6 @@ LGPL License Terms @ref lgpl_license
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#define FDCAN_ILE_INT0 (1 << 0)
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#define FDCAN_ILE_INT1 (1 << 1)
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#define FDCAN_RXGFC_RRFE (1 << 0)
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#define FDCAN_RXGFC_RRFS (1 << 1)
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/* ANFE[1:0]: Accept non-matching frames w/ extended ID */
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#define FDCAN_RXGFC_ANFE_SHIFT 2
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#define FDCAN_RXGFC_ANFE_MASK 0x3
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/* ANFS[1:0]: Accept non-matching frames w/ standard ID */
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#define FDCAN_RXGFC_ANFS_SHIFT 4
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#define FDCAN_RXGFC_ANFS_MASK 0x3
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#define FDCAN_RXGFC_F1OM (1 << 8)
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#define FDCAN_RXGFC_F0OM (1 << 9)
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/* LSS[4:0]: List size of standard ID filters */
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#define FDCAN_RXGFC_LSS_SHIFT 16
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#define FDCAN_RXGFC_LSS_MASK 0x1F
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/* LSE[3:0]: List size of extended ID filters */
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#define FDCAN_RXGFC_LSE_SHIFT 24
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#define FDCAN_RXGFC_LSE_MASK 0xF
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/* EIDM[28:0]: Extended ID mask for filtering */
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#define FDCAN_XIDAM_EIDM_SHIFT 0
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@@ -402,15 +358,12 @@ LGPL License Terms @ref lgpl_license
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/* Fill level of Rx FIFOs */
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#define FDCAN_RXFIFO_FL_SHIFT 0
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#define FDCAN_RXFIFO_FL_MASK 0xF
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/* Get index of Rx FIFOs */
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#define FDCAN_RXFIFO_GI_SHIFT 8
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#define FDCAN_RXFIFO_GI_MASK 0x3
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/* Put index of Rx FIFOs */
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#define FDCAN_RXFIFO_PI_SHIFT 16
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#define FDCAN_RXFIFO_PI_MASK 0x3
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#define FDCAN_RXFIFO_FF (1 << 24)
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#define FDCAN_RXFIFO_RFL (1 << 25)
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@@ -432,7 +385,6 @@ LGPL License Terms @ref lgpl_license
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/* Rx FIFOs acknowledge index */
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#define FDCAN_RXFIFO_AI_SHIFT 0
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#define FDCAN_RXFIFO_AI_MASK 0x7
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/* R0AI[2:0]: Rx FIFO 0 acknowledge index */
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#define FDCAN_RXF0A_R0AI_SHIFT FDCAN_RXFIFO_AI_SHIFT
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@@ -461,17 +413,14 @@ LGPL License Terms @ref lgpl_license
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/* TFFL[2:0]: Tx FIFO free level */
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#define FDCAN_TXFQS_TFFL_SHIFT 0
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#define FDCAN_TXFQS_TFFL_MASK 0x7
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/* TFGI[1:0]: Tx FIFO get index */
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#define FDCAN_TXFQS_TFGI_SHIFT 0
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#define FDCAN_TXFQS_TFGI_MASK 0x3
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#define FDCAN_TXFQS_TFGI_SHIFT 8
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/* TFQPI[1:0]: Tx FIFO put index */
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#define FDCAN_TXFQS_TFQPI_SHIFT 0
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#define FDCAN_TXFQS_TFQPI_MASK 0x3
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#define FDCAN_TXFQS_TFQPI_SHIFT 16
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#define FDCAN_TXFQS_TFQF (1 << 0)
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#define FDCAN_TXFQS_TFQF (1 << 21)
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/** @defgroup fdcan_txbrp FDCAN_TXBRP Transmit request pending bits
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* @{
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@@ -527,7 +476,7 @@ LGPL License Terms @ref lgpl_license
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/** @defgroup fdcan_txbcie FDCAN_TXBCIE Transmit cancelled interrupt enable bits
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*
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* Each bit enables or disables transmit cancelled interrupt for transmit buffer
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* slot.
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* slot.
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* @{
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*/
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#define FDCAN_TXBCIE_CFIE0 (1 << 0)
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@@ -537,15 +486,12 @@ LGPL License Terms @ref lgpl_license
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/* EFFL[2:0]: Event FIFO fill level*/
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#define FDCAN_TXEFS_EFFL_SHIFT 0
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#define FDCAN_TXEFS_EFFL_MASK 0x7
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/* EFG[1:0]: Event FIFO get index */
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#define FDCAN_TXEFS_EFGI_SHIFT 8
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#define FDCAN_TXEFS_EFGI_MASK 0x3
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/* EFPI[1:0]: Event FIFO put index */
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#define FDCAN_TXEFS_EFPI_SHIFT 16
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#define FDCAN_TXEFS_EFPI_MASK 0x3
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#define FDCAN_TXEFS_EFF (1 << 24)
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#define FDCAN_TXEFS_TEF (1 << 25)
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@@ -555,10 +501,6 @@ LGPL License Terms @ref lgpl_license
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#define FDCAN_TXEFA_EFAI_MASK 0x3
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/* PDIV[3:0]: Input clock divider */
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#define FDCAN_CKDIV_PDIV_SHIFT 0
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#define FDCAN_CKDIV_PDIV_MASK 0xF
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/* --- FD-CAN memory block defines------------------------------------------ */
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/** Structure describing standard ID filter.
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@@ -626,12 +568,6 @@ struct fdcan_standard_filter {
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#define FDCAN_SFEC_PRIO_FIFO1 0x6
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/**@}*/
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/** Amount of standard filters allocated in Message RAM
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* This number may vary between devices. 28 is value valid
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* for STM32G4
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**/
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#define FDCAN_SFT_MAX_NR 28
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/* SFEC = 0x7 is unused */
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#define FDCAN_SFID1_SHIFT 16
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@@ -706,7 +642,7 @@ struct fdcan_extended_filter {
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* using id2. */
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#define FDCAN_EFT_ID_MASK 0x2
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/** Similar to @ref FDCAN_EFT_RANGE except of ignoring global mask
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/** Similar to @ref FDCAN_EFT_RANGE except of ignoring global mask
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* set using @ref FDCAN_XIDAM register.
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*/
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#define FDCAN_EFT_RANGE_NOXIDAM 0x3
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@@ -715,12 +651,6 @@ struct fdcan_extended_filter {
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#define FDCAN_EFID2_SHIFT 0
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#define FDCAN_EFID2_MASK 0x1FFFFFFF
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/** Amount of extended filters allocated in Message RAM
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* This number may vary between devices. 8 is value valid
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* for STM32G4
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**/
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#define FDCAN_EFT_MAX_NR 8
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/** Structure describing receive FIFO element.
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* Receive FIFO element consists of 2 32bit values for header
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* and 16 32bit values for message payload.
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@@ -792,29 +722,6 @@ struct fdcan_tx_buffer_element {
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#define FDCAN_FIFO_RXTS_SHIFT 0
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#define FDCAN_FIFO_RXTS_MASK 0xFFFF
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/** Message RAM layout for one FDCAN block.
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* There are as many memory blocks as there are FDCAN blocks
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*/
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struct fdcan_message_ram {
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/* List of standard ID filters */
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struct fdcan_standard_filter lfssa[FDCAN_SFT_MAX_NR];
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/* List of extended ID filters */
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struct fdcan_extended_filter lfesa[FDCAN_EFT_MAX_NR];
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/* Buffer area for two receive FIFOs each having space for three messages */
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struct fdcan_rx_fifo_element rx_fifo[2][3];
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/* Buffer area for transmit event buffers */
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struct fdcan_tx_event_element tx_event[3];
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/* Buffer area for transmitted messages. May act either as FIFO or as queue
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* depending on configuration
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*/
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struct fdcan_tx_buffer_element tx_buffer[3];
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};
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/* --- FD-CAN error returns ------------------------------------------------- */
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/** FDCAN error return values
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@@ -886,7 +793,18 @@ void fdcan_release_fifo(uint32_t canport, uint8_t fifo);
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bool fdcan_available_tx(uint32_t canport);
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bool fdcan_available_rx(uint32_t canport, uint8_t fifo);
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int fdcan_cccr_init_cfg(uint32_t canport, bool set, uint32_t timeout);
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struct fdcan_standard_filter *fdcan_get_flssa_addr(uint32_t canport);
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struct fdcan_extended_filter *fdcan_get_flesa_addr(uint32_t canport);
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struct fdcan_rx_fifo_element *fdcan_get_rxfifo_addr(uint32_t canport,
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unsigned fifo_id, unsigned element_id);
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struct fdcan_tx_event_element *fdcan_get_txevt_addr(uint32_t canport);
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struct fdcan_tx_buffer_element *fdcan_get_txbuf_addr(uint32_t canport, unsigned element_id);
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void fdcan_set_fifo_locked_mode(uint32_t canport, bool locked);
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uint32_t fdcan_length_to_dlc(uint8_t length);
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uint8_t fdcan_dlc_to_length(uint32_t dlc);
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END_DECLS
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#endif
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132
include/libopencm3/stm32/g4/fdcan.h
Normal file
132
include/libopencm3/stm32/g4/fdcan.h
Normal file
@@ -0,0 +1,132 @@
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/** @defgroup fdcan_defines FDCAN Defines
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@ingroup STM32G4xx_defines
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@author @htmlonly © @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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/** @{ */
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/* FDCAN block base addresses. Used in functions to identify FDCAN block being manipulated. */
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/** @defgroup fdcan_block FDCAN block base addresses
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* @{
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*/
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#define CAN1 FDCAN1_BASE
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#define CAN2 FDCAN2_BASE
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#define CAN3 FDCAN3_BASE
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/**@}*/
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#define CAN_MSG_BASE FDCAN1_RAM_BASE
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#define FDCAN_RXFIS_BASE 0x0090
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#define FDCAN_RXFIA_BASE 0x0094
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#define FDCAN_RXFI_OFFSET 0x0008
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#define FDCAN_RXGFC(can_base) MMIO32(can_base + 0x0080)
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#define FDCAN_XIDAM(can_base) MMIO32(can_base + 0x0084)
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#define FDCAN_HPMS(can_base) MMIO32(can_base + 0x0088)
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#define FDCAN_TXBRP(can_base) MMIO32(can_base + 0x00C8)
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#define FDCAN_TXBAR(can_base) MMIO32(can_base + 0x00CC)
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#define FDCAN_TXBCR(can_base) MMIO32(can_base + 0x00D0)
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#define FDCAN_TXBTO(can_base) MMIO32(can_base + 0x00D4)
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#define FDCAN_TXBCF(can_base) MMIO32(can_base + 0x00D8)
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#define FDCAN_TXBTIE(can_base) MMIO32(can_base + 0x00DC)
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#define FDCAN_TXBCIE(can_base) MMIO32(can_base + 0x00E0)
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#define FDCAN_TXEFS(can_base) MMIO32(can_base + 0x00E4)
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#define FDCAN_TXEFA(can_base) MMIO32(can_base + 0x00E8)
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#define FDCAN_CKDIV(can_base) MMIO32(can_base + 0x0100)
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#define FDCAN_RXGFC_RRFE (1 << 0)
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#define FDCAN_RXGFC_RRFS (1 << 1)
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/* ANFE[1:0]: Accept non-matching frames w/ extended ID */
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#define FDCAN_RXGFC_ANFE_SHIFT 2
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#define FDCAN_RXGFC_ANFE_MASK 0x3
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/* ANFS[1:0]: Accept non-matching frames w/ standard ID */
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#define FDCAN_RXGFC_ANFS_SHIFT 4
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#define FDCAN_RXGFC_ANFS_MASK 0x3
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#define FDCAN_RXGFC_F1OM (1 << 8)
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#define FDCAN_RXGFC_F0OM (1 << 9)
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/* LSS[4:0]: List size of standard ID filters */
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#define FDCAN_RXGFC_LSS_SHIFT 16
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#define FDCAN_RXGFC_LSS_MASK 0x1F
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/* LSE[3:0]: List size of extended ID filters */
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#define FDCAN_RXGFC_LSE_SHIFT 24
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#define FDCAN_RXGFC_LSE_MASK 0xF
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#define FDCAN_RXFIFO_FL_MASK 0xF
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#define FDCAN_RXFIFO_GI_MASK 0x3
|
||||
#define FDCAN_RXFIFO_PI_MASK 0x3
|
||||
#define FDCAN_RXFIFO_AI_MASK 0x3
|
||||
|
||||
#define FDCAN_TXFQS_TFFL_MASK 0x7
|
||||
#define FDCAN_TXFQS_TFGI_MASK 0x3
|
||||
#define FDCAN_TXFQS_TFQPI_MASK 0x3
|
||||
|
||||
#define FDCAN_TXEFS_EFFL_MASK 0x7
|
||||
#define FDCAN_TXEFS_EFGI_MASK 0x3
|
||||
#define FDCAN_TXEFS_EFPI_MASK 0x3
|
||||
|
||||
/* PDIV[3:0]: Input clock divider */
|
||||
#define FDCAN_CKDIV_PDIV_SHIFT 0
|
||||
#define FDCAN_CKDIV_PDIV_MASK 0xF
|
||||
|
||||
/** Amount of standard filters allocated in Message RAM
|
||||
* This number may vary between devices. 28 is value valid
|
||||
* for STM32G4
|
||||
**/
|
||||
#define FDCAN_SFT_MAX_NR 28
|
||||
|
||||
/** Amount of extended filters allocated in Message RAM
|
||||
* This number may vary between devices. 8 is value valid
|
||||
* for STM32G4
|
||||
**/
|
||||
#define FDCAN_EFT_MAX_NR 8
|
||||
|
||||
#define FDCAN_LFSSA_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x0000)
|
||||
#define FDCAN_LFESA_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x0070)
|
||||
|
||||
#define FDCAN_RXFIFOS_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x00B0)
|
||||
|
||||
#define FDCAN_RXFIFO_OFFSET(can_base, fifo_id) \
|
||||
(FDCAN_RXFIFOS_OFFSET(can_base) + (0x00D8 * (fifo_id)))
|
||||
|
||||
#define FDCAN_TXEVT_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x0260)
|
||||
|
||||
#define FDCAN_TXBUF_OFFSET(can_base) ((FDCAN_BLOCK_ID(can_base) * 0x0350) + 0x0278)
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
unsigned fdcan_get_fifo_element_size(uint32_t canport, unsigned fifo_id);
|
||||
unsigned fdcan_get_txbuf_element_size(uint32_t canport);
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
257
include/libopencm3/stm32/h7/fdcan.h
Normal file
257
include/libopencm3/stm32/h7/fdcan.h
Normal file
@@ -0,0 +1,257 @@
|
||||
/** @defgroup fdcan_defines FDCAN Defines
|
||||
|
||||
@ingroup STM32H7xx_defines
|
||||
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2021 Eduard Drusa <ventyl86 at netkosice dot sk>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
/** @{ */
|
||||
|
||||
/* FDCAN block base addresses. Used in functions to identify FDCAN block being manipulated. */
|
||||
|
||||
/** @defgroup fdcan_block FDCAN block base addresses
|
||||
* @{
|
||||
*/
|
||||
#define CAN1 FDCAN1_BASE
|
||||
#define CAN2 FDCAN2_BASE
|
||||
/**@}*/
|
||||
|
||||
/* Size of FDCAN peripheral message RAM in bytes */
|
||||
#define CAN_MSG_SIZE 0x2800
|
||||
|
||||
#define FDCAN_GFC(can_base) MMIO32(can_base + 0x0080)
|
||||
|
||||
#define FDCAN_SIDFC(can_base) MMIO32(can_base + 0x0084)
|
||||
#define FDCAN_XIDFC(can_base) MMIO32(can_base + 0x0088)
|
||||
#define FDCAN_XIDAM(can_base) MMIO32(can_base + 0x0090)
|
||||
|
||||
#define FDCAN_HPMS(can_base) MMIO32(can_base + 0x0094)
|
||||
#define FDCAN_NDAT1(can_base) MMIO32(can_base + 0x0098)
|
||||
#define FDCAN_HDAT2(can_base) MMIO32(can_base + 0x009C)
|
||||
|
||||
#define FDCAN_RXFIC_BASE 0x00A0
|
||||
#define FDCAN_RXFI_OFFSET 0x0010
|
||||
|
||||
#define FDCAN_RXFIC(can_base, fifo_id) \
|
||||
MMIO32((can_base) + FDCAN_RXFIC_BASE + (FDCAN_RXFI_OFFSET * (fifo_id)))
|
||||
|
||||
#define FDCAN_RXF0C(can_base) FDCAN_RXFIC(can_base, 0)
|
||||
#define FDCAN_RXF1C(can_base) FDCAN_RXFIC(can_base, 1)
|
||||
|
||||
#define FDCAN_RXFIS_BASE 0x00A4
|
||||
#define FDCAN_RXFIA_BASE 0x00A8
|
||||
|
||||
#define FDCAN_RXBC(can_base) MMIO32(can_base + 0x00AC)
|
||||
|
||||
#define FDCAN_RXESC(can_base) MMIO32(can_base + 0x00BC)
|
||||
#define FDCAN_TXESC(can_base) MMIO32(can_base + 0x00C8)
|
||||
#define FDCAN_TXBRP(can_base) MMIO32(can_base + 0x00CC)
|
||||
#define FDCAN_TXBAR(can_base) MMIO32(can_base + 0x00D0)
|
||||
#define FDCAN_TXBCR(can_base) MMIO32(can_base + 0x00D4)
|
||||
#define FDCAN_TXBTO(can_base) MMIO32(can_base + 0x00D8)
|
||||
#define FDCAN_TXBCF(can_base) MMIO32(can_base + 0x00DC)
|
||||
#define FDCAN_TXBTIE(can_base) MMIO32(can_base + 0x00E0)
|
||||
#define FDCAN_TXBCIE(can_base) MMIO32(can_base + 0x00E4)
|
||||
#define FDCAN_TXEFC(can_base) MMIO32(can_base + 0x00F0)
|
||||
#define FDCAN_TXEFS(can_base) MMIO32(can_base + 0x00F4)
|
||||
#define FDCAN_TXEFA(can_base) MMIO32(can_base + 0x00F8)
|
||||
|
||||
#define FDCAN_TTTMC(can_base) MMIO32(can_base + 0x0100)
|
||||
#define FDCAN_TTRMC(can_base) MMIO32(can_base + 0x0104)
|
||||
#define FDCAN_TTOCF(can_base) MMIO32(can_base + 0x0108)
|
||||
#define FDCAN_TTMLM(can_base) MMIO32(can_base + 0x010C)
|
||||
#define FDCAN_TURCF(can_base) MMIO32(can_base + 0x0110)
|
||||
#define FDCAN_TTOCN(can_base) MMIO32(can_base + 0x0114)
|
||||
#define FDCAN_TTGTP(can_base) MMIO32(can_base + 0x0118)
|
||||
#define FDCAN_TTTMK(can_base) MMIO32(can_base + 0x011C)
|
||||
#define FDCAN_TTTIR(can_base) MMIO32(can_base + 0x0120)
|
||||
#define FDCAN_TTIE(can_base) MMIO32(can_base + 0x0124)
|
||||
#define FDCAN_TTILS(can_base) MMIO32(can_base + 0x0128)
|
||||
#define FDCAN_TTOST(can_base) MMIO32(can_base + 0x012C)
|
||||
#define FDCAN_TURNA(can_base) MMIO32(can_base + 0x0130)
|
||||
#define FDCAN_TTLGT(can_base) MMIO32(can_base + 0x0134)
|
||||
#define FDCAN_TTCTC(can_base) MMIO32(can_base + 0x0138)
|
||||
#define FDCAN_TTCPT(can_base) MMIO32(can_base + 0x013C)
|
||||
#define FDCAN_TTCSM(can_base) MMIO32(can_base + 0x0140)
|
||||
#define FDCAN_TTTS(can_base) MMIO32(can_base + 0x0300)
|
||||
|
||||
#define FDCAN_CCU_CCFG MMIO32(CAN_CCU_BASE + 0x0004)
|
||||
#define FDCAN_CCU_CREL MMIO32(CAN_CCU_BASE + 0x0000)
|
||||
|
||||
#define FDCAN_GFC_RRFE (1 << 0)
|
||||
#define FDCAN_GFC_RRFS (1 << 1)
|
||||
|
||||
/* ANFE[1:0]: Accept non-matching frames w/ extended ID */
|
||||
#define FDCAN_GFC_ANFE_SHIFT 2
|
||||
#define FDCAN_GFC_ANFE_MASK 0x3
|
||||
|
||||
/* ANFS[1:0]: Accept non-matching frames w/ standard ID */
|
||||
#define FDCAN_GFC_ANFS_SHIFT 4
|
||||
#define FDCAN_GFC_ANFS_MASK 0x3
|
||||
|
||||
#define FDCAN_FXS_MASK 0xFF
|
||||
#define FDCAN_FXS_SHIFT 16
|
||||
|
||||
/* Position of start address of relocatable object within register */
|
||||
#define FDCAN_FXSA_MASK 0x3FFF
|
||||
#define FDCAN_FXSA_SHIFT 2
|
||||
|
||||
/* LSS[7:0]: List size of standard ID filters */
|
||||
#define FDCAN_SIDFC_LSS_MASK FDCAN_FXS_MASK
|
||||
#define FDCAN_SIDFC_LSS_SHIFT FDCAN_FXS_SHIFT
|
||||
|
||||
/* LFSSA[13:0]: Filter List standard start address */
|
||||
#define FDCAN_SIDFC_FLSSA_MASK FDCAN_FXSA_MASK
|
||||
#define FDCAN_SIDFC_FLSSA_SHIFT FDCAN_FXSA_SHIFT
|
||||
|
||||
/* LSE[7:0]: List size of extended ID filters */
|
||||
#define FDCAN_XIDFC_LSE_MASK FDCAN_FXS_MASK
|
||||
#define FDCAN_XIDFC_LSE_SHIFT FDCAN_FXS_SHIFT
|
||||
|
||||
/* LFSSA[7:0]: Filter List extended start address */
|
||||
#define FDCAN_XIDFC_FLESA_MASK FDCAN_FXSA_MASK
|
||||
#define FDCAN_XIDFC_FLESA_SHIFT FDCAN_FXSA_SHIFT
|
||||
|
||||
/* TFQS[5:0]: Tx FIFO/Queue size */
|
||||
#define FDCAN_TXBC_TFQS_MASK 0x3F
|
||||
#define FDCAN_TXBC_TFQS_SHIFT 24
|
||||
|
||||
/* TBSA[7:0]: Transmit buffer start address */
|
||||
#define FDCAN_TXBC_TBSA_MASK FDCAN_FXSA_MASK
|
||||
#define FDCAN_TXBC_TBSA_SHIFT FDCAN_FXSA_SHIFT
|
||||
|
||||
#define FDCAN_TXEFC_EFS_MASK 0x3F
|
||||
#define FDCAN_TXEFC_EFS_SHIFT 16
|
||||
|
||||
/* EFSA[7:0]: (Transmit) event FIFO start address */
|
||||
#define FDCAN_TXEFC_EFSA_MASK FDCAN_FXSA_MASK
|
||||
#define FDCAN_TXEFC_EFSA_SHIFT FDCAN_FXSA_SHIFT
|
||||
|
||||
#define FDCAN_RXFIC_FIOM (1 << 31)
|
||||
|
||||
#define FDCAN_RXFIC_FIWM_MASK 0x7F
|
||||
#define FDCAN_RXFIC_FIWM_SHIFT 24
|
||||
|
||||
#define FDCAN_RXFIC_FIS_MASK 0x7F
|
||||
#define FDCAN_RXFIC_FIS_SHIFT 16
|
||||
|
||||
|
||||
#define FDCAN_RXFIC_FISA_MASK FDCAN_FXSA_MASK
|
||||
#define FDCAN_RXFIC_FISA_SHIFT FDCAN_FXSA_SHIFT
|
||||
|
||||
#define FDCAN_RXF0C_F0OM FDCAN_RXFIC_FIOM
|
||||
|
||||
/* F0WM[6:0]: FIFO0 watermark mode */
|
||||
#define FDCAN_RXF0C_F0WM_MASK FDCAN_RXFIC_FIWM_MASK
|
||||
#define FDCAN_RXF0C_F0WM_SHIFT FDCAN_RXFIC_FIWM_SHIFT
|
||||
|
||||
/* F0S[6:0]: FIFO0 size */
|
||||
#define FDCAN_RXF0C_F0S_MASK FDCAN_RXFIC_FIS_MASK
|
||||
#define FDCAN_RXF0C_F0S_SHIFT FDCAN_RXFIC_FIS_SHIFT
|
||||
|
||||
/* F0SA[13:0]: FIFO0 start address */
|
||||
#define FDCAN_RXF0C_F0SA_MASK FDCAN_RXFIC_FISA_MASK
|
||||
#define FDCAN_RXF0C_F0SA_SHIFT FDCAN_RXFIC_FISA_SHIFT
|
||||
|
||||
#define FDCAN_RXF1C_F1OM FDCAN_RXFIC_FIOM
|
||||
|
||||
/* F1WM[6:0]: FIFO1 watermark mode */
|
||||
#define FDCAN_RXF1C_F1WM_MASK FDCAN_RXFIC_FIWM_MASK
|
||||
#define FDCAN_RXF1C_F1WM_SHIFT FDCAN_RXFIC_FIWM_SHIFT
|
||||
|
||||
/* F1S[6:0]: FIFO1 size */
|
||||
#define FDCAN_RXF1C_F1S_MASK FDCAN_RXFIC_FIS_MASK
|
||||
#define FDCAN_RXF1C_F1S_SHIFT FDCAN_RXFIC_FIS_SHIFT
|
||||
|
||||
/* F1SA[13:0]: FIFO1 start address */
|
||||
#define FDCAN_RXF1C_F1SA_MASK FDCAN_RXFIC_FISA_MASK
|
||||
#define FDCAN_RXF1C_F1SA_SHIFT FDCAN_RXFIC_FISA_SHIFT
|
||||
|
||||
/* RBDS[3:0]: RX buffer data field size */
|
||||
#define FDCAN_RXESC_RBDS_MASK 0x7
|
||||
#define FDCAN_RXESC_RBDS_SHIFT 8
|
||||
|
||||
/* F0DS[3:0]: FIFO0 data field size */
|
||||
#define FDCAN_RXESC_F0DS_MASK 0x7
|
||||
#define FDCAN_RXESC_F0DS_SHIFT 0
|
||||
|
||||
/* F1DS[3:0]: FIFO1 data field size */
|
||||
#define FDCAN_RXESC_F1DS_MASK 0x7
|
||||
#define FDCAN_RXESC_F1DS_SHIFT 4
|
||||
|
||||
/* TBDS[3:0]: TX buffer data field size */
|
||||
#define FDCAN_TXESC_TBDS_MASK 0x7
|
||||
#define FDCAN_TXESC_TBDS_SHIFT 0
|
||||
|
||||
#define FDCAN_RXFIFO_FL_MASK 0x7F
|
||||
#define FDCAN_RXFIFO_GI_MASK 0x3F
|
||||
#define FDCAN_RXFIFO_PI_MASK 0x3F
|
||||
|
||||
#define FDCAN_RXFIFO_AI_MASK 0x3F
|
||||
|
||||
#define FDCAN_TXFQS_TFFL_MASK 0x3F
|
||||
#define FDCAN_TXFQS_TFGI_MASK 0x1F
|
||||
#define FDCAN_TXFQS_TFQPI_MASK 0x1F
|
||||
|
||||
#define FDCAN_TXEFS_EFFL_MASK 0x3F
|
||||
#define FDCAN_TXEFS_EFGI_MASK 0x1F
|
||||
#define FDCAN_TXEFS_EFPI_MASK 0x1F
|
||||
|
||||
/* PDIV[3:0]: Input clock divider */
|
||||
#define FDCAN_CCU_CCFG_CDIV_SHIFT 16
|
||||
#define FDCAN_CCU_CCFG_CDIV_MASK 0xF
|
||||
|
||||
|
||||
|
||||
#define FDCAN_LFSSA_OFFSET(can_base) \
|
||||
(FDCAN_SIDFC(can_base) & (FDCAN_SIDFC_FLSSA_MASK << FDCAN_SIDFC_FLSSA_SHIFT))
|
||||
|
||||
#define FDCAN_LFESA_OFFSET(can_base) \
|
||||
(FDCAN_XIDFC(can_base) & (FDCAN_XIDFC_FLESA_MASK << FDCAN_XIDFC_FLESA_SHIFT))
|
||||
|
||||
#define FDCAN_RXFIFO_OFFSET(can_base, fifo_id) \
|
||||
(FDCAN_RXFIC(can_base, fifo_id) & (FDCAN_FXSA_MASK << FDCAN_FXSA_SHIFT))
|
||||
|
||||
#define FDCAN_TXBUF_OFFSET(can_base) \
|
||||
(FDCAN_TXBC(can_base) & (FDCAN_TXBC_TBSA_MASK << FDCAN_TXBC_TBSA_SHIFT))
|
||||
|
||||
#define FDCAN_TXEVT_OFFSET(can_base) \
|
||||
(FDCAN_TXEFC(can_base) & (FDCAN_TXEFC_EFSA_MASK << FDCAN_TXEFC_EFSA_SHIFT))
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void fdcan_init_std_filter_ram(uint32_t canport, uint32_t flssa, uint8_t lss);
|
||||
void fdcan_init_ext_filter_ram(uint32_t canport, uint32_t flesa, uint8_t lse);
|
||||
void fdcan_init_fifo_ram(uint32_t canport, unsigned fifo_id, uint32_t fxsa, uint8_t fxs);
|
||||
void fdcan_init_tx_event_ram(uint32_t canport, uint32_t tesa, uint8_t tes);
|
||||
void fdcan_init_tx_buffer_ram(uint32_t canport, uint32_t tbsa, uint8_t tbs);
|
||||
unsigned fdcan_get_fifo_element_size(uint32_t canport, unsigned fifo_id);
|
||||
unsigned fdcan_get_txbuf_element_size(uint32_t canport);
|
||||
int fdcan_set_rx_element_size(uint32_t canport, uint8_t rxbuf, uint8_t rxfifo0, uint8_t rxfifo1);
|
||||
int fdcan_set_tx_element_size(uint32_t canport, uint8_t txbuf);
|
||||
|
||||
END_DECLS
|
||||
|
||||
Reference in New Issue
Block a user