stm32l4: rcc: Implement PLL helper as seen in other MCU families
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
Vlad Logyin
committed by
Karl Palsson
Karl Palsson
parent
757a0a14eb
commit
3122c0b33f
@@ -39,16 +39,25 @@
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#ifndef LIBOPENCM3_RCC_H
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#define LIBOPENCM3_RCC_H
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/* --- RCC registers ------------------------------------------------------- */
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#include <libopencm3/stm32/pwr.h>
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/** @defgroup rcc_registers RCC Registers
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* @brief Reset / Clock Control Registers
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@{*/
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/** Clock control register */
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#define RCC_CR MMIO32(RCC_BASE + 0x00)
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#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)
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/** Clock Configuration register */
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#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
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/** PLL Configuration register */
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#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c)
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#define RCC_PLLSAI1_CFGR MMIO32(RCC_BASE + 0x10)
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#define RCC_PLLSAI2_CFGR MMIO32(RCC_BASE + 0x14)
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/** Clock interrupt enable register */
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#define RCC_CIER MMIO32(RCC_BASE + 0x18)
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/** Clock interrupt flag resiger */
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#define RCC_CIFR MMIO32(RCC_BASE + 0x1c)
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/** Clock interrupt clear register */
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#define RCC_CICR MMIO32(RCC_BASE + 0x20)
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#define RCC_AHB1RSTR_OFFSET 0x28
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#define RCC_AHB1RSTR MMIO32(RCC_BASE + RCC_AHB1RSTR_OFFSET)
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@@ -87,13 +96,18 @@
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#define RCC_APB2SMENR_OFFSET 0x80
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#define RCC_APB2SMENR MMIO32(RCC_BASE + RCC_APB2SMENR_OFFSET)
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#define RCC_CCIPR MMIO32(RCC_BASE + 0x88)
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/** Backup Domain control register */
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#define RCC_BDCR MMIO32(RCC_BASE + 0x90)
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/** Clock control and status register */
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#define RCC_CSR MMIO32(RCC_BASE + 0x94)
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#define RCC_CRRCR MMIO32(RCC_BASE + 0x98)
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#define RCC_CCIPR2 MMIO32(RCC_BASE + 0x9C)
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/** @}*/
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/* --- RCC_CR values ------------------------------------------------------- */
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/** @defgroup rcc_cr_values RCC_CR values
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* @ingroup rcc_registers
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* @brief Clock Control register values
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@{*/
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#define RCC_CR_PLLSAI2RDY (1 << 29)
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#define RCC_CR_PLLSAI2ON (1 << 28)
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#define RCC_CR_PLLSAI1RDY (1 << 27)
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@@ -108,6 +122,8 @@
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#define RCC_CR_HSIRDY (1 << 10)
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#define RCC_CR_HSIKERON (1 << 9)
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#define RCC_CR_HSION (1 << 8)
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/** @}*/
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/** @defgroup rcc_cr_msirange MSI Range
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* @ingroup STM32L4xx_rcc_defines
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* @brief Range of the MSI oscillator
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@@ -180,36 +196,35 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
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#define RCC_CFGR_STOPWUCK_MSI (0 << 15)
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#define RCC_CFGR_STOPWUCK_HSI16 (1 << 15)
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/* PPRE2: APB high-speed prescaler (APB2) */
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#define RCC_CFGR_PPRE2_NODIV 0x0
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#define RCC_CFGR_PPRE2_DIV2 0x4
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#define RCC_CFGR_PPRE2_DIV4 0x5
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#define RCC_CFGR_PPRE2_DIV8 0x6
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#define RCC_CFGR_PPRE2_DIV16 0x7
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#define RCC_CFGR_PPRE2_MASK 0x7
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#define RCC_CFGR_PPRE2_SHIFT 11
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/* PPRE1: APB low-speed prescaler (APB1) */
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#define RCC_CFGR_PPRE1_NODIV 0x0
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#define RCC_CFGR_PPRE1_DIV2 0x4
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#define RCC_CFGR_PPRE1_DIV4 0x5
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#define RCC_CFGR_PPRE1_DIV8 0x6
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#define RCC_CFGR_PPRE1_DIV16 0x7
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#define RCC_CFGR_PPRE1_MASK 0x7
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#define RCC_CFGR_PPRE1_SHIFT 8
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#define RCC_CFGR_PPRE1_MASK 0x7
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#define RCC_CFGR_PPRE2_SHIFT 11
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#define RCC_CFGR_PPRE2_MASK 0x7
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/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors
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* These can be used for both APB1 and APB2 prescaling
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* @{
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*/
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#define RCC_CFGR_PPRE_NODIV 0x0
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#define RCC_CFGR_PPRE_DIV2 0x4
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#define RCC_CFGR_PPRE_DIV4 0x5
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#define RCC_CFGR_PPRE_DIV8 0x6
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#define RCC_CFGR_PPRE_DIV16 0x7
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/**@}*/
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/* HPRE: AHB prescaler */
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#define RCC_CFGR_HPRE_NODIV 0x0
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#define RCC_CFGR_HPRE_DIV2 0x8
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#define RCC_CFGR_HPRE_DIV4 0x9
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#define RCC_CFGR_HPRE_DIV8 0xa
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#define RCC_CFGR_HPRE_DIV16 0xb
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#define RCC_CFGR_HPRE_DIV64 0xc
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#define RCC_CFGR_HPRE_DIV128 0xd
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#define RCC_CFGR_HPRE_DIV256 0xe
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#define RCC_CFGR_HPRE_DIV512 0xf
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#define RCC_CFGR_HPRE_MASK 0xf
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#define RCC_CFGR_HPRE_SHIFT 4
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#define RCC_CFGR_HPRE_MASK 0xf
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/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale factors
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@{*/
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#define RCC_CFGR_HPRE_NODIV 0x0
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#define RCC_CFGR_HPRE_DIV2 (0x8 + 0)
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#define RCC_CFGR_HPRE_DIV4 (0x8 + 1)
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#define RCC_CFGR_HPRE_DIV8 (0x8 + 2)
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#define RCC_CFGR_HPRE_DIV16 (0x8 + 3)
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#define RCC_CFGR_HPRE_DIV64 (0x8 + 4)
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#define RCC_CFGR_HPRE_DIV128 (0x8 + 5)
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#define RCC_CFGR_HPRE_DIV256 (0x8 + 6)
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#define RCC_CFGR_HPRE_DIV512 (0x8 + 7)
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/**@}*/
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/* SWS: System clock switch status */
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#define RCC_CFGR_SWS_MSI 0x0
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@@ -725,6 +740,30 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
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#define RCC_CSR_LSIRDY (1 << 1)
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#define RCC_CSR_LSION (1 << 0)
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struct rcc_clock_scale {
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uint8_t pllm;
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uint16_t plln;
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uint8_t pllp;
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uint8_t pllq;
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uint8_t pllr;
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uint8_t pll_source;
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uint32_t flash_config;
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uint8_t hpre;
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uint8_t ppre1;
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uint8_t ppre2;
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enum pwr_vos_scale voltage_scale;
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uint32_t ahb_frequency;
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uint32_t apb1_frequency;
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uint32_t apb2_frequency;
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};
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enum rcc_clock_config_entry {
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RCC_CLOCK_VRANGE1_80MHZ,
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RCC_CLOCK_CONFIG_END
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};
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extern const struct rcc_clock_scale rcc_hsi16_configs[RCC_CLOCK_CONFIG_END];
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/* --- Variable definitions ------------------------------------------------ */
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extern uint32_t rcc_ahb_frequency;
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@@ -981,6 +1020,7 @@ void rcc_set_ppre1(uint32_t ppre1);
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void rcc_set_hpre(uint32_t hpre);
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void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr);
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uint32_t rcc_system_clock_source(void);
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void rcc_clock_setup_pll(const struct rcc_clock_scale *clock);
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void rcc_set_msi_range(uint32_t msi_range);
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void rcc_set_msi_range_standby(uint32_t msi_range);
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void rcc_pll_output_enable(uint32_t pllout);
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@@ -38,12 +38,34 @@
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/**@{*/
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#include <libopencm3/cm3/assert.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/flash.h>
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#include <libopencm3/stm32/pwr.h>
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 4000000;
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uint32_t rcc_apb1_frequency = 4000000;
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uint32_t rcc_apb2_frequency = 4000000;
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const struct rcc_clock_scale rcc_hsi16_configs[RCC_CLOCK_CONFIG_END] = {
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{ /* 80MHz PLL from HSI16 VR1 */
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.pllm = 4,
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.plln = 40,
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.pllp = RCC_PLLCFGR_PLLP_DIV7,
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.pllq = RCC_PLLCFGR_PLLQ_DIV6,
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.pllr = RCC_PLLCFGR_PLLR_DIV2,
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.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
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.hpre = RCC_CFGR_HPRE_NODIV,
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.ppre1 = RCC_CFGR_PPRE_NODIV,
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.ppre2 = RCC_CFGR_PPRE_NODIV,
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.voltage_scale = PWR_SCALE1,
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.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
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FLASH_ACR_LATENCY_4WS,
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.ahb_frequency = 80000000,
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.apb1_frequency = 80000000,
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.apb2_frequency = 80000000,
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},
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};
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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@@ -341,6 +363,82 @@ uint32_t rcc_system_clock_source(void)
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return (RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK;
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}
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/**
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* Setup clocks to run from PLL.
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*
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* The arguments provide the pll source, multipliers, dividers, all that's
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* needed to establish a system clock.
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*
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* @param clock clock information structure.
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*/
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void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
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{
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/* Enable internal high-speed oscillator (HSI16). */
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rcc_osc_on(RCC_HSI16);
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rcc_wait_for_osc_ready(RCC_HSI16);
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/* Select HSI16 as SYSCLK source. */
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rcc_set_sysclk_source(RCC_PLLCFGR_PLLSRC_HSI16);
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/* Enable external high-speed oscillator (HSE). */
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if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE) {
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rcc_osc_on(RCC_HSE);
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rcc_wait_for_osc_ready(RCC_HSE);
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}
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/* Set the VOS scale mode */
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rcc_periph_clock_enable(RCC_PWR);
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pwr_set_vos_scale(clock->voltage_scale);
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/*
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* Set prescalers for AHB, ADC, APB1, APB2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(clock->hpre);
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rcc_set_ppre1(clock->ppre1);
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rcc_set_ppre2(clock->ppre2);
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/* Disable PLL oscillator before changing its configuration. */
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rcc_osc_off(RCC_PLL);
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/* Configure the PLL oscillator. */
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rcc_set_main_pll(clock->pll_source, clock->pllm, clock->plln,
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clock->pllp, clock->pllq, clock->pllr);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(RCC_PLL);
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rcc_wait_for_osc_ready(RCC_PLL);
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/* Configure flash settings. */
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if (clock->flash_config & FLASH_ACR_DCEN) {
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flash_dcache_enable();
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} else {
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flash_dcache_disable();
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}
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if (clock->flash_config & FLASH_ACR_ICEN) {
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flash_icache_enable();
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} else {
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flash_icache_disable();
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}
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flash_set_ws(clock->flash_config);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_PLL);
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/* Wait for PLL clock to be selected. */
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rcc_wait_for_sysclk_status(RCC_PLL);
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/* Set the peripheral clock frequencies used. */
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rcc_ahb_frequency = clock->ahb_frequency;
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rcc_apb1_frequency = clock->apb1_frequency;
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rcc_apb2_frequency = clock->apb2_frequency;
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/* Disable internal high-speed oscillator. */
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if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE) {
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rcc_osc_off(RCC_HSI16);
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}
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}
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/**
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* Set the msi run time range.
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* Can only be called when MSI is either OFF, or when MSI is on _and_
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@@ -497,11 +595,11 @@ uint32_t rcc_get_timer_clk_freq(uint32_t timer)
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}
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} else if (timer >= TIM2_BASE && timer <= TIM7_BASE) {
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uint8_t ppre1 = (RCC_CFGR >> RCC_CFGR_PPRE1_SHIFT) & RCC_CFGR_PPRE1_MASK;
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return (ppre1 == RCC_CFGR_PPRE1_NODIV) ? rcc_apb1_frequency
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return (ppre1 == RCC_CFGR_PPRE_NODIV) ? rcc_apb1_frequency
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: 2 * rcc_apb1_frequency;
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} else {
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uint8_t ppre2 = (RCC_CFGR >> RCC_CFGR_PPRE2_SHIFT) & RCC_CFGR_PPRE2_MASK;
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return (ppre2 == RCC_CFGR_PPRE2_NODIV) ? rcc_apb2_frequency
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return (ppre2 == RCC_CFGR_PPRE_NODIV) ? rcc_apb2_frequency
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: 2 * rcc_apb2_frequency;
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}
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cm3_assert_not_reached();
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