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stm32h7: updates to PWR and RCC to support PLL configuration.

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PLL configuration on the H7 is pretty involved, and takes a number of
configurations to make it work. In order to make peripheral drivers a bit
easier to implement, working with a soft clock tree in the rcc module which
stores the clock settings for each clock as they are setup such that users
can request the clock value from the RCC module for configuration. Added
getter for the clock which allows the user to pass the base address of the
peripheral, and get the peripheral clock value for convenience.

Clock configuration is still missing values for setting up all of the kernel
clocks for the peripherals, but this is in work, and there is a framework to
do so.

Have tested to 400MHz without issue. Peripherals that are explicitly supported
are working and the clock tree values appear to follow correctly.

Added LDO settings to allow setting the scaling to support high frequencies.
This commit is contained in:
Brian Viele
2019-12-17 02:07:55 -05:00
committed by Karl Palsson
parent 97688b913e
commit 2ca56f4c21
6 changed files with 916 additions and 63 deletions
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39
lib/stm32/h7/pwr.c
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@@ -1,15 +1,9 @@
/** @defgroup pwr_file PWR peripheral API
*
* @ingroup peripheral_apis
*
/**
* @brief <b>libopencm3 STM32H7xx Power Control</b>
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
* @author @htmlonly &copy; @endhtmlonly 2017 Matthew Lai <m@matthewlai.ca>
*
* @date 12 March 2017
* @date 16 December, 2019
*
* This library supports the power control system for the
* STM32H7 series of ARM Cortex Microcontrollers by ST Microelectronics.
@@ -21,6 +15,7 @@
*
* Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
* Copyright (C) 2017 Matthew Lai <m@matthewlai.ca>
* Copyright (C) 2019 Brian Viele <vielster@allocor.tech>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -37,14 +32,34 @@
*/
#include <libopencm3/stm32/pwr.h>
#include <libopencm3/stm32/rcc.h>
#include <libopencm3/stm32/syscfg.h>
/**@{*/
void pwr_set_mode_ldo(void) {
const uint32_t ldo_mask = (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS);
PWR_CR3 = (PWR_CR3 & ~ldo_mask) | (PWR_CR3_SCUEN | PWR_CR3_LDOEN);
while (!(PWR_CSR1 & PWR_CSR1_ACTVOSRDY));
}
void pwr_set_svos_scale(enum pwr_svos_scale scale)
{
uint32_t pwr_cr1_reg = PWR_CR1;
pwr_cr1_reg = (pwr_cr1_reg & ~PWR_CR1_SVOS_MASK) | scale;
PWR_CR1 = pwr_cr1_reg;
pwr_cr1_reg = (pwr_cr1_reg & ~(PWR_CR1_SVOS_MASK << PWR_CR1_SVOS_SHIFT));
PWR_CR1 = pwr_cr1_reg | scale;
}
/**@}*/
void pwr_set_vos_scale(enum pwr_vos_scale scale) {
rcc_periph_clock_enable(RCC_SYSCFG); /* Ensure we can access ODEN. */
uint32_t d3cr_masked = PWR_D3CR & ~(PWR_D3CR_VOS_MASK << PWR_D3CR_VOS_SHIFT);
/* Per the manual, VOS0 is implemented as VOS1 + ODEN. Handle this case. */
if (scale == PWR_VOS_SCALE_0) {
PWR_D3CR = d3cr_masked | PWR_VOS_SCALE_1;
SYSCFG_PWRCR |= SYSCFG_PWRCR_ODEN;
} else {
SYSCFG_PWRCR &= ~SYSCFG_PWRCR_ODEN;
PWR_D3CR = d3cr_masked | scale;
}
while (!(PWR_D3CR & PWR_D3CR_VOSRDY));
}