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stm32/h7: Implemented support for the HSI48

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dragonmux
2024-04-15 19:03:23 +01:00
committed by Piotr Esden-Tempski
parent 9f8ce70771
commit 2b6eb047e0
2 changed files with 15 additions and 1 deletions
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7
include/libopencm3/stm32/h7/rcc.h
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@@ -770,6 +770,13 @@ BEGIN_DECLS
*/ */
void rcc_clock_setup_pll(const struct rcc_pll_config *config); void rcc_clock_setup_pll(const struct rcc_pll_config *config);
/**
* Setup and bring up the HSI48 for use by the USB controller.
*
* Note: Should be used with the CRS for stability
*/
void rcc_clock_setup_hsi48(void);
/** /**
* Get the clock rate (in Hz) of the specified clock source. There are * Get the clock rate (in Hz) of the specified clock source. There are
* numerous clock sources and configurations on the H7, so rates for each * numerous clock sources and configurations on the H7, so rates for each

9
lib/stm32/h7/rcc.c
View File

@@ -221,11 +221,18 @@ void rcc_clock_setup_pll(const struct rcc_pll_config *config) {
/* Domains dividers are all configured, now we can switchover to PLL. */ /* Domains dividers are all configured, now we can switchover to PLL. */
RCC_CFGR |= RCC_CFGR_SW_PLL1; RCC_CFGR |= RCC_CFGR_SW_PLL1;
uint32_t cfgr_sws = ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK); uint32_t cfgr_sws = ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK);
while(cfgr_sws != RCC_CFGR_SWS_PLL1) { while (cfgr_sws != RCC_CFGR_SWS_PLL1) {
cfgr_sws = ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK); cfgr_sws = ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK);
} }
} }
void rcc_clock_setup_hsi48(void)
{
RCC_CR |= RCC_CR_HSI48ON;
while (!(RCC_CR & RCC_CR_HSI48RDY))
continue;
}
uint32_t rcc_get_bus_clk_freq(enum rcc_clock_source source) { uint32_t rcc_get_bus_clk_freq(enum rcc_clock_source source) {
uint32_t clksel; uint32_t clksel;
switch (source) { switch (source) {