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cm3: scs: drop all duplicate information

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Keeps the best version of the documentation.

Fixes: https://github.com/libopencm3/libopencm3/pull/269
This commit is contained in:
Karl Palsson
2019-10-18 22:38:16 +00:00
parent 833da4b672
commit 2b54119b78
4 changed files with 150 additions and 211 deletions
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55
include/libopencm3/cm3/dwt.h
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@@ -20,25 +20,63 @@
#ifndef LIBOPENCM3_CM3_DWT_H
#define LIBOPENCM3_CM3_DWT_H
/**
* @defgroup cm_fpb Cortex-M Flash Patch and Breakpoint (FPB) unit
* @ingroup CM3_defines
* @{
*/
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/memorymap.h>
/**
* @defgroup cm_dwt Cortex-M Data Watch and Trace unit.
* @ingroup CM3_defines
* System Control Space (SCS) => Data Watchpoint and Trace (DWT).
* See "ARMv7-M Architecture Reference Manual"
* and "ARMv6-M Architecture Reference Manual"
* The DWT is an optional debug unit that provides watchpoints, data tracing,
* and system profiling for the processor.
* @{
*/
/*****************************************************************************/
/* Register definitions */
/*****************************************************************************/
/** DWT Control register
* Purpose Provides configuration and status information for the DWT block, and
* used to control features of the block
* Usage constraints: There are no usage constraints.
* Configurations Always implemented.
*/
#define DWT_CTRL MMIO32(DWT_BASE + 0x00)
/* Those defined only on ARMv7 and above */
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/**
* DWT_CYCCNT register
* Cycle Count Register (Shows or sets the value of the processor cycle
* counter, CYCCNT)
* When enabled, CYCCNT increments on each processor clock cycle. On overflow,
* CYCCNT wraps to zero.
*
* Purpose Shows or sets the value of the processor cycle counter, CYCCNT.
* Usage constraints: The DWT unit suspends CYCCNT counting when the processor
* is in Debug state.
* Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control
* register, DWT_CTRL.
* When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this
* register is UNK/SBZP.
*/
#define DWT_CYCCNT MMIO32(DWT_BASE + 0x04)
/** DWT_CPICNT register
* Purpose Counts additional cycles required to execute multi-cycle
* instructions and instruction fetch stalls.
* Usage constraints: The counter initializes to 0 when software enables its
* counter overflow event by
* setting the DWT_CTRL.CPIEVTENA bit to 1.
* Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control
* register, DWT_CTRL.
* If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not
* include the profiling counters, this register is UNK/SBZP.
*/
#define DWT_CPICNT MMIO32(DWT_BASE + 0x08)
#define DWT_EXCCNT MMIO32(DWT_BASE + 0x0C)
#define DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10)
@@ -99,6 +137,11 @@
#define DWT_CTRL_POSTPRESET_SHIFT 1
#define DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT)
/**
* CYCCNTENA Enables the Cycle counter.
* 0 = Disabled, 1 = Enabled
* This bit is UNK/SBZP if the NOCYCCNT bit is RAO.
*/
#define DWT_CTRL_CYCCNTENA (1 << 0)
#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */