stm32/h7: Implemented support for enabling the RTC clock source and peripheral
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committed by
Piotr Esden-Tempski
parent
bf7929b723
commit
2a6059540d
@@ -843,6 +843,15 @@ uint32_t rcc_get_fdcan_clk_freq(uint32_t fdcan);
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*/
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void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t clksel);
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/**
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* Set the clksel value for the RTC and bring it up
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*
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* NB: This function may only be called on real POR or after BDRST, it will
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* internally turn into a no-op if it detects the RTC clock source has already
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* been defined to protect from misconfiguration
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*/
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void rcc_rtc_clock_enable(uint32_t clksel);
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/**
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* Set the clock select for the FDCAN devices.
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* @param[in] clksel Clock source to configure for, @ref rcc_d2ccip1r_values
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@@ -448,6 +448,19 @@ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
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*reg = regval;
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}
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void rcc_rtc_clock_enable(uint32_t clksel)
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{
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// Make this function a no-op if the RTC has already been set up
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if (RCC_BDCR & (RCC_BDCR_RTCSEL_MASK << RCC_BDCR_RTCSEL_SHIFT))
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return;
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// Start operations by disabling the write protections for the BDCR
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PWR_CR1 |= PWR_CR1_DBP;
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// Now configure the clock bits and bring the RTC up
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RCC_BDCR |= (clksel << RCC_BDCR_RTCSEL_SHIFT) | RCC_BDCR_RTCEN;
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// Protect the BDCR again as we don't need to poke it further
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PWR_CR1 &= ~PWR_CR1_DBP;
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}
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void rcc_set_fdcan_clksel(uint8_t clksel)
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{
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RCC_D2CCIP1R &= ~(RCC_D2CCIP1R_FDCANSEL_MASK << RCC_D2CCIP1R_FDCANSEL_SHIFT);
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