EMTime/libopencm3
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

stm32: rcc: extract osc_bypass functions

Browse Source 
rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time!  There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
This commit is contained in:
Karl Palsson
2017-05-01 22:56:28 +00:00
parent 2547bf66d9
commit 29c712326f
20 changed files with 62 additions and 382 deletions
Download Patch File Download Diff File Expand all files Collapse all files

60
lib/stm32/common/rcc_common_all.c
View File

@@ -197,6 +197,66 @@ void rcc_set_mco(uint32_t mcosrc)
(mcosrc << RCC_CFGR_MCO_SHIFT);
}
/**
* RCC Enable Bypass.
* Enable an external clock to bypass the internal clock (high speed and low
* speed clocks only). The external clock must be enabled (see @ref rcc_osc_on)
* and the internal clock must be disabled (see @ref rcc_osc_off) for this to
* have effect.
* @note The LSE clock is in the backup domain and cannot be bypassed until the
* backup domain write protection has been removed (see @ref
* pwr_disable_backup_domain_write_protect).
* @param[in] osc Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
#ifdef RCC_CSR_LSEBYP
RCC_CSR |= RCC_CSR_LSEBYP;
#else
RCC_BDCR |= RCC_BDCR_LSEBYP;
#endif
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/**
* RCC Disable Bypass.
* Re-enable the internal clock (high speed and low speed clocks only). The
* internal clock must be disabled (see @ref rcc_osc_off) for this to have
* effect.
* @note The LSE clock is in the backup domain and cannot have bypass removed
* until the backup domain write protection has been removed (see @ref
* pwr_disable_backup_domain_write_protect) or the backup domain has been reset
* (see @ref rcc_backupdomain_reset).
* @param[in] osc Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
#ifdef RCC_CSR_LSEBYP
RCC_CSR &= ~RCC_CSR_LSEBYP;
#else
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
#endif
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/**@}*/
#undef _RCC_REG