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stm32: rcc: extract osc_bypass functions

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rcc_osc_bypass_enable and rcc_osc_bypass_disable have been copy/pasted
around for the last time!  There's a compile bit to check for L0/L1, but
otherwise this is just code duplication for no gain.
This commit is contained in:
Karl Palsson
2017-05-01 22:56:28 +00:00
parent 2547bf66d9
commit 29c712326f
20 changed files with 62 additions and 382 deletions
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60
lib/stm32/common/rcc_common_all.c
View File

@@ -197,6 +197,66 @@ void rcc_set_mco(uint32_t mcosrc)
(mcosrc << RCC_CFGR_MCO_SHIFT);
}
/**
* RCC Enable Bypass.
* Enable an external clock to bypass the internal clock (high speed and low
* speed clocks only). The external clock must be enabled (see @ref rcc_osc_on)
* and the internal clock must be disabled (see @ref rcc_osc_off) for this to
* have effect.
* @note The LSE clock is in the backup domain and cannot be bypassed until the
* backup domain write protection has been removed (see @ref
* pwr_disable_backup_domain_write_protect).
* @param[in] osc Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
#ifdef RCC_CSR_LSEBYP
RCC_CSR |= RCC_CSR_LSEBYP;
#else
RCC_BDCR |= RCC_BDCR_LSEBYP;
#endif
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/**
* RCC Disable Bypass.
* Re-enable the internal clock (high speed and low speed clocks only). The
* internal clock must be disabled (see @ref rcc_osc_off) for this to have
* effect.
* @note The LSE clock is in the backup domain and cannot have bypass removed
* until the backup domain write protection has been removed (see @ref
* pwr_disable_backup_domain_write_protect) or the backup domain has been reset
* (see @ref rcc_backupdomain_reset).
* @param[in] osc Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
#ifdef RCC_CSR_LSEBYP
RCC_CSR &= ~RCC_CSR_LSEBYP;
#else
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
#endif
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/**@}*/
#undef _RCC_REG

60
lib/stm32/f0/rcc.c
View File

@@ -323,66 +323,6 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable Bypass.
*
* Enable an external clock to bypass the internal clock (high speed and low
* speed clocks only). The external clock must be enabled (see @ref rcc_osc_on)
* and the internal clock must be disabled (see @ref rcc_osc_off) for this to
* have effect.
*
* @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case RCC_HSI48:
case RCC_HSI14:
case RCC_HSI:
case RCC_LSI:
case RCC_PLL:
/* Do nothing */
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable Bypass.
*
* Re-enable the internal clock (high speed and low speed clocks only). The
* internal clock must be disabled (see @ref rcc_osc_off) for this to have
* effect.
*
*
* @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case RCC_HSI48:
case RCC_HSI14:
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing */
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the Source for the System Clock.
*

66
lib/stm32/f1/rcc.c
View File

@@ -346,72 +346,6 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable Bypass.
Enable an external clock to bypass the internal clock (high speed and low speed
clocks only). The external clock must be enabled (see @ref rcc_osc_on) and the
internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
@note The LSE clock is in the backup domain and cannot be bypassed until the
backup domain write protection has been removed (see @ref
pwr_disable_backup_domain_write_protect).
@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_PLL2:
case RCC_PLL3:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable Bypass.
Re-enable the internal clock (high speed and low speed clocks only). The
internal clock must be disabled (see @ref rcc_osc_off) for this to have effect.
@note The LSE clock is in the backup domain and cannot have bypass removed
until the backup domain write protection has been removed (see @ref
pwr_disable_backup_domain_write_protect) or the backup domain has been reset
(see @ref rcc_backupdomain_reset).
@param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect.
*/
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_PLL2:
case RCC_PLL3:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set the Source for the System Clock.

34
lib/stm32/f2/rcc.c
View File

@@ -255,40 +255,6 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_set_sysclk_source(uint32_t clk)
{
uint32_t reg32;

34
lib/stm32/f3/rcc.c
View File

@@ -277,40 +277,6 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_set_sysclk_source(uint32_t clk)
{
uint32_t reg32;

31
lib/stm32/f4/rcc.c
View File

@@ -532,37 +532,6 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/**
* Set the dividers for the PLLSAI clock outputs
* divider p is only available on F4x9 parts, pass 0 for other parts.

36
lib/stm32/f7/rcc.c
View File

@@ -212,42 +212,6 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_set_sysclk_source(uint32_t clk)
{
uint32_t reg32;

31
lib/stm32/l0/rcc.c
View File

@@ -91,37 +91,6 @@ void rcc_osc_off(enum rcc_osc osc)
}
}
/* TODO easy target for shared code */
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_CSR |= RCC_CSR_LSEBYP;
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/* TODO easy target for shared code */
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_CSR &= ~RCC_CSR_LSEBYP;
break;
default:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Clear the Oscillator Ready Interrupt Flag

36
lib/stm32/l1/rcc.c
View File

@@ -335,42 +335,6 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_CSR |= RCC_CSR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
case RCC_MSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_CSR &= ~RCC_CSR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI:
case RCC_LSI:
case RCC_MSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
/**
* Set the range of the MSI oscillator
* @param range desired range @ref rcc_icscr_msirange

36
lib/stm32/l4/rcc.c
View File

@@ -258,42 +258,6 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON;
}
void rcc_osc_bypass_enable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR |= RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR |= RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI16:
case RCC_MSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_osc_bypass_disable(enum rcc_osc osc)
{
switch (osc) {
case RCC_HSE:
RCC_CR &= ~RCC_CR_HSEBYP;
break;
case RCC_LSE:
RCC_BDCR &= ~RCC_BDCR_LSEBYP;
break;
case RCC_PLL:
case RCC_HSI16:
case RCC_MSI:
case RCC_LSI:
/* Do nothing, only HSE/LSE allowed here. */
break;
}
}
void rcc_set_sysclk_source(uint32_t clk)
{
uint32_t reg32;