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csv contributions from GNU Radio Conference 2012 HackFest. Thanks, David!

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This commit is contained in:
Michael Ossmann
2012-09-27 19:36:41 -06:00
committed by Piotr Esden-Tempski
parent df2ac8bbac
commit 299806bc4e
5 changed files with 290 additions and 0 deletions
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63
scripts/data/lpc43xx/ssp.csv Normal file
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SSP0_CR0,0,4,DSS,Data Size Select,0,rw
SSP0_CR0,4,2,FRF,Frame Format,0,rw
SSP0_CR0,6,1,CPOL,Clock Out Polarity,0,rw
SSP0_CR0,7,1,CPHA,Clock Out Phase,0,rw
SSP0_CR0,8,8,SCR,Serial Clock Rate,0,rw
SSP1_CR0,0,4,DSS,Data Size Select,0,rw
SSP1_CR0,4,2,FRF,Frame Format,0,rw
SSP1_CR0,6,1,CPOL,Clock Out Polarity,0,rw
SSP1_CR0,7,1,CPHA,Clock Out Phase,0,rw
SSP1_CR0,8,8,SCR,Serial Clock Rate,0,rw
SSP0_CR1,0,1,LBM,Loop Back Mode,0,rw
SSP0_CR1,1,1,SSE,SSP Enable,0,rw
SSP0_CR1,2,1,MS,Master/Slave Mode,0,rw
SSP0_CR1,3,1,SOD,Slave Output Disable,0,rw
SSP1_CR1,1,1,SSE,SSP Enable,0,rw
SSP1_CR1,2,1,MS,Master/Slave Mode,0,rw
SSP1_CR1,3,1,SOD,Slave Output Disable,0,rw
SSP0_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw
SSP1_DR,0,16,DATA,"Software can write data to be transmitted to this register, and read data that has been",0,rw
SSP0_SR,0,1,TFE,Transmit FIFO Empty,1,r
SSP0_SR,1,1,TNF,Transmit FIFO Not Full,1,r
SSP0_SR,2,1,RNE,Receive FIFO Not Empty,0,r
SSP0_SR,3,1,RFF,Receive FIFO Full,0,r
SSP0_SR,4,1,BSY,Busy.,0,r
SSP1_SR,0,1,TFE,Transmit FIFO Empty,1,r
SSP1_SR,1,1,TNF,Transmit FIFO Not Full,1,r
SSP1_SR,2,1,RNE,Receive FIFO Not Empty,0,r
SSP1_SR,3,1,RFF,Receive FIFO Full,0,r
SSP1_SR,4,1,BSY,Busy.,0,r
SSP0_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw
SSP1_CPSR,0,8,CPSDVSR,SSP Clock Prescale Register,0,rw
SSP0_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw
SSP0_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw
SSP0_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw
SSP0_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw
SSP1_IMSC,0,1,RORIM,Software should set this bit to enable interrupt when a Receive Overrun occurs,0,rw
SSP1_IMSC,1,1,RTIM,Software should set this bit to enable interrupt when a Receive Time-out condition occurs,0,rw
SSP1_IMSC,2,1,RXIM,Software should set this bit to enable interrupt when the Rx FIFO is at least half full,0,rw
SSP1_IMSC,3,1,TXIM,Software should set this bit to enable interrupt when the Tx FIFO is at least half empty,0,rw
SSP0_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r
SSP0_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r
SSP0_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r
SSP0_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r
SSP1_RIS,0,1,RORRIS,This bit is 1 if another frame was completely received while the RxFIFO was full,0,r
SSP1_RIS,1,1,RTRIS,"This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period",0,r
SSP1_RIS,2,1,RXRIS,This bit is 1 if the Rx FIFO is at least half full,0,r
SSP1_RIS,3,1,TXRIS,This bit is 1 if the Tx FIFO is at least half empty,1,r
SSP0_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r
SSP0_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r
SSP0_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r
SSP0_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r
SSP1_MIS,0,1,RORMIS,"This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled",0,r
SSP1_MIS,1,1,RTMIS,"This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled",0,r
SSP1_MIS,2,1,RXMIS,"This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled",0,r
SSP1_MIS,3,1,TXMIS,"This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled",0,r
SSP0_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w
SSP0_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w
SSP1_ICR,0,1,RORIC,Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt,,w
SSP1_ICR,1,1,RTIC,Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt,,w
SSP0_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw
SSP0_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw
SSP1_DMACR,0,1,RXDMAE,Receive DMA Enable,0,rw
SSP1_DMACR,1,1,TXDMAE,Transmit DMA Enable,0,rw
1 SSP0_CR0 0 4 DSS Data Size Select 0 rw
2 SSP0_CR0 4 2 FRF Frame Format 0 rw
3 SSP0_CR0 6 1 CPOL Clock Out Polarity 0 rw
4 SSP0_CR0 7 1 CPHA Clock Out Phase 0 rw
5 SSP0_CR0 8 8 SCR Serial Clock Rate 0 rw
6 SSP1_CR0 0 4 DSS Data Size Select 0 rw
7 SSP1_CR0 4 2 FRF Frame Format 0 rw
8 SSP1_CR0 6 1 CPOL Clock Out Polarity 0 rw
9 SSP1_CR0 7 1 CPHA Clock Out Phase 0 rw
10 SSP1_CR0 8 8 SCR Serial Clock Rate 0 rw
11 SSP0_CR1 0 1 LBM Loop Back Mode 0 rw
12 SSP0_CR1 1 1 SSE SSP Enable 0 rw
13 SSP0_CR1 2 1 MS Master/Slave Mode 0 rw
14 SSP0_CR1 3 1 SOD Slave Output Disable 0 rw
15 SSP1_CR1 1 1 SSE SSP Enable 0 rw
16 SSP1_CR1 2 1 MS Master/Slave Mode 0 rw
17 SSP1_CR1 3 1 SOD Slave Output Disable 0 rw
18 SSP0_DR 0 16 DATA Software can write data to be transmitted to this register, and read data that has been 0 rw
19 SSP1_DR 0 16 DATA Software can write data to be transmitted to this register, and read data that has been 0 rw
20 SSP0_SR 0 1 TFE Transmit FIFO Empty 1 r
21 SSP0_SR 1 1 TNF Transmit FIFO Not Full 1 r
22 SSP0_SR 2 1 RNE Receive FIFO Not Empty 0 r
23 SSP0_SR 3 1 RFF Receive FIFO Full 0 r
24 SSP0_SR 4 1 BSY Busy. 0 r
25 SSP1_SR 0 1 TFE Transmit FIFO Empty 1 r
26 SSP1_SR 1 1 TNF Transmit FIFO Not Full 1 r
27 SSP1_SR 2 1 RNE Receive FIFO Not Empty 0 r
28 SSP1_SR 3 1 RFF Receive FIFO Full 0 r
29 SSP1_SR 4 1 BSY Busy. 0 r
30 SSP0_CPSR 0 8 CPSDVSR SSP Clock Prescale Register 0 rw
31 SSP1_CPSR 0 8 CPSDVSR SSP Clock Prescale Register 0 rw
32 SSP0_IMSC 0 1 RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs 0 rw
33 SSP0_IMSC 1 1 RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs 0 rw
34 SSP0_IMSC 2 1 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full 0 rw
35 SSP0_IMSC 3 1 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty 0 rw
36 SSP1_IMSC 0 1 RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs 0 rw
37 SSP1_IMSC 1 1 RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs 0 rw
38 SSP1_IMSC 2 1 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full 0 rw
39 SSP1_IMSC 3 1 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty 0 rw
40 SSP0_RIS 0 1 RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full 0 r
41 SSP0_RIS 1 1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period 0 r
42 SSP0_RIS 2 1 RXRIS This bit is 1 if the Rx FIFO is at least half full 0 r
43 SSP0_RIS 3 1 TXRIS This bit is 1 if the Tx FIFO is at least half empty 1 r
44 SSP1_RIS 0 1 RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full 0 r
45 SSP1_RIS 1 1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period 0 r
46 SSP1_RIS 2 1 RXRIS This bit is 1 if the Rx FIFO is at least half full 0 r
47 SSP1_RIS 3 1 TXRIS This bit is 1 if the Tx FIFO is at least half empty 1 r
48 SSP0_MIS 0 1 RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled 0 r
49 SSP0_MIS 1 1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled 0 r
50 SSP0_MIS 2 1 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled 0 r
51 SSP0_MIS 3 1 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled 0 r
52 SSP1_MIS 0 1 RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled 0 r
53 SSP1_MIS 1 1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled 0 r
54 SSP1_MIS 2 1 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled 0 r
55 SSP1_MIS 3 1 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled 0 r
56 SSP0_ICR 0 1 RORIC Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt w
57 SSP0_ICR 1 1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt w
58 SSP1_ICR 0 1 RORIC Writing a 1 to this bit clears the 'frame was received when RxFIFO was full' interrupt w
59 SSP1_ICR 1 1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt w
60 SSP0_DMACR 0 1 RXDMAE Receive DMA Enable 0 rw
61 SSP0_DMACR 1 1 TXDMAE Transmit DMA Enable 0 rw
62 SSP1_DMACR 0 1 RXDMAE Receive DMA Enable 0 rw
63 SSP1_DMACR 1 1 TXDMAE Transmit DMA Enable 0 rw