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csv contributions from GNU Radio Conference 2012 HackFest. Thanks, David!

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This commit is contained in:
Michael Ossmann
2012-09-27 19:36:41 -06:00
committed by Piotr Esden-Tempski
parent df2ac8bbac
commit 299806bc4e
5 changed files with 290 additions and 0 deletions
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scripts/data/lpc43xx/i2s.csv Normal file
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I2S0_DAO,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
I2S0_DAO,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
I2S0_DAO,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
I2S0_DAO,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
I2S0_DAO,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
I2S0_DAO,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
I2S0_DAO,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
I2S1_DAO,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
I2S1_DAO,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
I2S1_DAO,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
I2S1_DAO,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
I2S1_DAO,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
I2S1_DAO,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
I2S1_DAO,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
I2S0_DAI,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
I2S0_DAI,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
I2S0_DAI,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
I2S0_DAI,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
I2S0_DAI,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
I2S0_DAI,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
I2S0_DAI,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
I2S1_DAI,0,2,WORDWIDTH,Selects the number of bytes in data,1,rw
I2S1_DAI,2,1,MONO,"When 1, data is of monaural format. When 0, the data is in stereo format",0,rw
I2S1_DAI,3,1,STOP,"When 1, disables accesses on FIFOs, places the transmit channel in mute mode",0,rw
I2S1_DAI,4,1,RESET,"When 1, asynchronously resets the transmit channel and FIFO",0,rw
I2S1_DAI,5,1,WS_SEL,"When 0, the interface is in master mode. When 1, the interface is in slave mode",1,rw
I2S1_DAI,6,9,WS_HALFPERIOD,"Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",0x1f,rw
I2S1_DAI,15,1,MUTE,"When 1, the transmit channel sends only zeroes",1,rw
I2S0_TXFIFO,0,32,I2STXFIFO,8 x 32-bit transmit FIFO,0,w
I2S1_TXFIFO,0,32,I2STXFIFO,8 x 32-bit transmit FIFO,0,w
I2S0_RXFIFO,0,32,I2SRXFIFO,8 x 32-bit receive FIFO,0,r
I2S1_RXFIFO,0,32,I2SRXFIFO,8 x 32-bit receive FIFO,0,r
I2S0_STATE,0,1,IRQ,This bit reflects the presence of Receive Interrupt or Transmit Interrupt,1,r
I2S0_STATE,1,1,DMAREQ1,This bit reflects the presence of Receive or Transmit DMA Request 1,1,r
I2S0_STATE,2,1,DMAREQ2,This bit reflects the presence of Receive or Transmit DMA Request 2,1,r
I2S0_STATE,8,4,RX_LEVEL,Reflects the current level of the Receive FIFO,0,r
I2S0_STATE,16,4,TX_LEVEL,Reflects the current level of the Transmit FIFO,0,r
I2S1_STATE,0,1,IRQ,This bit reflects the presence of Receive Interrupt or Transmit Interrupt,1,r
I2S1_STATE,1,1,DMAREQ1,This bit reflects the presence of Receive or Transmit DMA Request 1,1,r
I2S1_STATE,2,1,DMAREQ2,This bit reflects the presence of Receive or Transmit DMA Request 2,1,r
I2S1_STATE,8,4,RX_LEVEL,Reflects the current level of the Receive FIFO,0,r
I2S1_STATE,16,4,TX_LEVEL,Reflects the current level of the Transmit FIFO,0,r
I2S0_DMA1,0,1,RX_DMA1_ENABLE,"When 1, enables DMA1 for I2S receive",0,rw
I2S0_DMA1,1,1,TX_DMA1_ENABLE,"When 1, enables DMA1 for I2S transmit",0,rw
I2S0_DMA1,8,4,RX_DEPTH_DMA1,Set the FIFO level that triggers a receive DMA request on DMA1,0,rw
I2S0_DMA1,16,4,TX_DEPTH_DMA1,Set the FIFO level that triggers a transmit DMA request on DMA1,0,rw
I2S1_DMA1,0,1,RX_DMA1_ENABLE,"When 1, enables DMA1 for I2S receive",0,rw
I2S1_DMA1,1,1,TX_DMA1_ENABLE,"When 1, enables DMA1 for I2S transmit",0,rw
I2S1_DMA1,8,4,RX_DEPTH_DMA1,Set the FIFO level that triggers a receive DMA request on DMA1,0,rw
I2S1_DMA1,16,4,TX_DEPTH_DMA1,Set the FIFO level that triggers a transmit DMA request on DMA1,0,rw
I2S0_DMA2,0,1,RX_DMA2_ENABLE,"When 1, enables DMA2 for I2S receive",0,rw
I2S0_DMA2,1,1,TX_DMA2_ENABLE,"When 1, enables DMA2 for I2S transmit",0,rw
I2S0_DMA2,8,4,RX_DEPTH_DMA2,Set the FIFO level that triggers a receive DMA request on DMA2,0,rw
I2S0_DMA2,16,4,TX_DEPTH_DMA2,Set the FIFO level that triggers a transmit DMA request on DMA2,0,rw
I2S1_DMA2,0,1,RX_DMA2_ENABLE,"When 1, enables DMA2 for I2S receive",0,rw
I2S1_DMA2,1,1,TX_DMA2_ENABLE,"When 1, enables DMA2 for I2S transmit",0,rw
I2S1_DMA2,8,4,RX_DEPTH_DMA2,Set the FIFO level that triggers a receive DMA request on DMA2,0,rw
I2S1_DMA2,16,4,TX_DEPTH_DMA2,Set the FIFO level that triggers a transmit DMA request on DMA2,0,rw
I2S0_IRQ,0,1,RX_IRQ_ENABLE,"When 1, enables I2S receive interrupt",0,rw
I2S0_IRQ,1,1,TX_IRQ_ENABLE,"When 1, enables I2S transmit interrupt",0,rw
I2S0_IRQ,8,4,RX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
I2S0_IRQ,16,4,TX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
I2S1_IRQ,0,1,RX_IRQ_ENABLE,"When 1, enables I2S receive interrupt",0,rw
I2S1_IRQ,1,1,TX_IRQ_ENABLE,"When 1, enables I2S transmit interrupt",0,rw
I2S1_IRQ,8,4,RX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
I2S1_IRQ,16,4,TX_DEPTH_IRQ,Set the FIFO level on which to create an irq request.,0,rw
I2S0_TXRATE,0,8,Y_DIVIDER,I2S transmit MCLK rate denominator,0,rw
I2S0_TXRATE,8,8,X_DIVIDER,I2S transmit MCLK rate numerator,0,rw
I2S1_TXRATE,0,8,Y_DIVIDER,I2S transmit MCLK rate denominator,0,rw
I2S1_TXRATE,8,8,X_DIVIDER,I2S transmit MCLK rate numerator,0,rw
I2S0_RXRATE,0,8,Y_DIVIDER,I2S receive MCLK rate denominator,0,rw
I2S0_RXRATE,8,8,X_DIVIDER,I2S receive MCLK rate numerator,0,rw
I2S1_RXRATE,0,8,Y_DIVIDER,I2S receive MCLK rate denominator,0,rw
I2S1_RXRATE,8,8,X_DIVIDER,I2S receive MCLK rate numerator,0,rw
I2S0_TXBITRATE,0,6,TX_BITRATE,I2S transmit bit rate,0,rw
I2S1_TXBITRATE,0,6,TX_BITRATE,I2S transmit bit rate,0,rw
I2S0_RXBITRATE,0,6,RX_BITRATE,I2S receive bit rate,0,rw
I2S1_RXBITRATE,0,6,RX_BITRATE,I2S receive bit rate,0,rw
I2S0_TXMODE,0,2,TXCLKSEL,Clock source selection for the transmit bit clock divider,0,rw
I2S0_TXMODE,2,1,TX4PIN,Transmit 4-pin mode selection,0,rw
I2S0_TXMODE,3,1,TXMCENA,Enable for the TX_MCLK output,0,rw
I2S1_TXMODE,0,2,TXCLKSEL,Clock source selection for the transmit bit clock divider,0,rw
I2S1_TXMODE,2,1,TX4PIN,Transmit 4-pin mode selection,0,rw
I2S1_TXMODE,3,1,TXMCENA,Enable for the TX_MCLK output,0,rw
I2S0_RXMODE,0,2,RXCLKSEL,Clock source selection for the receive bit clock divider,0,rw
I2S0_RXMODE,2,1,RX4PIN,Receive 4-pin mode selection,0,rw
I2S0_RXMODE,3,1,RXMCENA,Enable for the RX_MCLK output,0,rw
I2S1_RXMODE,0,2,RXCLKSEL,Clock source selection for the receive bit clock divider,0,rw
I2S1_RXMODE,2,1,RX4PIN,Receive 4-pin mode selection,0,rw
I2S1_RXMODE,3,1,RXMCENA,Enable for the RX_MCLK output,0,rw
1 I2S0_DAO 0 2 WORDWIDTH Selects the number of bytes in data 1 rw
2 I2S0_DAO 2 1 MONO When 1, data is of monaural format. When 0, the data is in stereo format 0 rw
3 I2S0_DAO 3 1 STOP When 1, disables accesses on FIFOs, places the transmit channel in mute mode 0 rw
4 I2S0_DAO 4 1 RESET When 1, asynchronously resets the transmit channel and FIFO 0 rw
5 I2S0_DAO 5 1 WS_SEL When 0, the interface is in master mode. When 1, the interface is in slave mode 1 rw
6 I2S0_DAO 6 9 WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1f rw
7 I2S0_DAO 15 1 MUTE When 1, the transmit channel sends only zeroes 1 rw
8 I2S1_DAO 0 2 WORDWIDTH Selects the number of bytes in data 1 rw
9 I2S1_DAO 2 1 MONO When 1, data is of monaural format. When 0, the data is in stereo format 0 rw
10 I2S1_DAO 3 1 STOP When 1, disables accesses on FIFOs, places the transmit channel in mute mode 0 rw
11 I2S1_DAO 4 1 RESET When 1, asynchronously resets the transmit channel and FIFO 0 rw
12 I2S1_DAO 5 1 WS_SEL When 0, the interface is in master mode. When 1, the interface is in slave mode 1 rw
13 I2S1_DAO 6 9 WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1f rw
14 I2S1_DAO 15 1 MUTE When 1, the transmit channel sends only zeroes 1 rw
15 I2S0_DAI 0 2 WORDWIDTH Selects the number of bytes in data 1 rw
16 I2S0_DAI 2 1 MONO When 1, data is of monaural format. When 0, the data is in stereo format 0 rw
17 I2S0_DAI 3 1 STOP When 1, disables accesses on FIFOs, places the transmit channel in mute mode 0 rw
18 I2S0_DAI 4 1 RESET When 1, asynchronously resets the transmit channel and FIFO 0 rw
19 I2S0_DAI 5 1 WS_SEL When 0, the interface is in master mode. When 1, the interface is in slave mode 1 rw
20 I2S0_DAI 6 9 WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1f rw
21 I2S0_DAI 15 1 MUTE When 1, the transmit channel sends only zeroes 1 rw
22 I2S1_DAI 0 2 WORDWIDTH Selects the number of bytes in data 1 rw
23 I2S1_DAI 2 1 MONO When 1, data is of monaural format. When 0, the data is in stereo format 0 rw
24 I2S1_DAI 3 1 STOP When 1, disables accesses on FIFOs, places the transmit channel in mute mode 0 rw
25 I2S1_DAI 4 1 RESET When 1, asynchronously resets the transmit channel and FIFO 0 rw
26 I2S1_DAI 5 1 WS_SEL When 0, the interface is in master mode. When 1, the interface is in slave mode 1 rw
27 I2S1_DAI 6 9 WS_HALFPERIOD Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1f rw
28 I2S1_DAI 15 1 MUTE When 1, the transmit channel sends only zeroes 1 rw
29 I2S0_TXFIFO 0 32 I2STXFIFO 8 x 32-bit transmit FIFO 0 w
30 I2S1_TXFIFO 0 32 I2STXFIFO 8 x 32-bit transmit FIFO 0 w
31 I2S0_RXFIFO 0 32 I2SRXFIFO 8 x 32-bit receive FIFO 0 r
32 I2S1_RXFIFO 0 32 I2SRXFIFO 8 x 32-bit receive FIFO 0 r
33 I2S0_STATE 0 1 IRQ This bit reflects the presence of Receive Interrupt or Transmit Interrupt 1 r
34 I2S0_STATE 1 1 DMAREQ1 This bit reflects the presence of Receive or Transmit DMA Request 1 1 r
35 I2S0_STATE 2 1 DMAREQ2 This bit reflects the presence of Receive or Transmit DMA Request 2 1 r
36 I2S0_STATE 8 4 RX_LEVEL Reflects the current level of the Receive FIFO 0 r
37 I2S0_STATE 16 4 TX_LEVEL Reflects the current level of the Transmit FIFO 0 r
38 I2S1_STATE 0 1 IRQ This bit reflects the presence of Receive Interrupt or Transmit Interrupt 1 r
39 I2S1_STATE 1 1 DMAREQ1 This bit reflects the presence of Receive or Transmit DMA Request 1 1 r
40 I2S1_STATE 2 1 DMAREQ2 This bit reflects the presence of Receive or Transmit DMA Request 2 1 r
41 I2S1_STATE 8 4 RX_LEVEL Reflects the current level of the Receive FIFO 0 r
42 I2S1_STATE 16 4 TX_LEVEL Reflects the current level of the Transmit FIFO 0 r
43 I2S0_DMA1 0 1 RX_DMA1_ENABLE When 1, enables DMA1 for I2S receive 0 rw
44 I2S0_DMA1 1 1 TX_DMA1_ENABLE When 1, enables DMA1 for I2S transmit 0 rw
45 I2S0_DMA1 8 4 RX_DEPTH_DMA1 Set the FIFO level that triggers a receive DMA request on DMA1 0 rw
46 I2S0_DMA1 16 4 TX_DEPTH_DMA1 Set the FIFO level that triggers a transmit DMA request on DMA1 0 rw
47 I2S1_DMA1 0 1 RX_DMA1_ENABLE When 1, enables DMA1 for I2S receive 0 rw
48 I2S1_DMA1 1 1 TX_DMA1_ENABLE When 1, enables DMA1 for I2S transmit 0 rw
49 I2S1_DMA1 8 4 RX_DEPTH_DMA1 Set the FIFO level that triggers a receive DMA request on DMA1 0 rw
50 I2S1_DMA1 16 4 TX_DEPTH_DMA1 Set the FIFO level that triggers a transmit DMA request on DMA1 0 rw
51 I2S0_DMA2 0 1 RX_DMA2_ENABLE When 1, enables DMA2 for I2S receive 0 rw
52 I2S0_DMA2 1 1 TX_DMA2_ENABLE When 1, enables DMA2 for I2S transmit 0 rw
53 I2S0_DMA2 8 4 RX_DEPTH_DMA2 Set the FIFO level that triggers a receive DMA request on DMA2 0 rw
54 I2S0_DMA2 16 4 TX_DEPTH_DMA2 Set the FIFO level that triggers a transmit DMA request on DMA2 0 rw
55 I2S1_DMA2 0 1 RX_DMA2_ENABLE When 1, enables DMA2 for I2S receive 0 rw
56 I2S1_DMA2 1 1 TX_DMA2_ENABLE When 1, enables DMA2 for I2S transmit 0 rw
57 I2S1_DMA2 8 4 RX_DEPTH_DMA2 Set the FIFO level that triggers a receive DMA request on DMA2 0 rw
58 I2S1_DMA2 16 4 TX_DEPTH_DMA2 Set the FIFO level that triggers a transmit DMA request on DMA2 0 rw
59 I2S0_IRQ 0 1 RX_IRQ_ENABLE When 1, enables I2S receive interrupt 0 rw
60 I2S0_IRQ 1 1 TX_IRQ_ENABLE When 1, enables I2S transmit interrupt 0 rw
61 I2S0_IRQ 8 4 RX_DEPTH_IRQ Set the FIFO level on which to create an irq request. 0 rw
62 I2S0_IRQ 16 4 TX_DEPTH_IRQ Set the FIFO level on which to create an irq request. 0 rw
63 I2S1_IRQ 0 1 RX_IRQ_ENABLE When 1, enables I2S receive interrupt 0 rw
64 I2S1_IRQ 1 1 TX_IRQ_ENABLE When 1, enables I2S transmit interrupt 0 rw
65 I2S1_IRQ 8 4 RX_DEPTH_IRQ Set the FIFO level on which to create an irq request. 0 rw
66 I2S1_IRQ 16 4 TX_DEPTH_IRQ Set the FIFO level on which to create an irq request. 0 rw
67 I2S0_TXRATE 0 8 Y_DIVIDER I2S transmit MCLK rate denominator 0 rw
68 I2S0_TXRATE 8 8 X_DIVIDER I2S transmit MCLK rate numerator 0 rw
69 I2S1_TXRATE 0 8 Y_DIVIDER I2S transmit MCLK rate denominator 0 rw
70 I2S1_TXRATE 8 8 X_DIVIDER I2S transmit MCLK rate numerator 0 rw
71 I2S0_RXRATE 0 8 Y_DIVIDER I2S receive MCLK rate denominator 0 rw
72 I2S0_RXRATE 8 8 X_DIVIDER I2S receive MCLK rate numerator 0 rw
73 I2S1_RXRATE 0 8 Y_DIVIDER I2S receive MCLK rate denominator 0 rw
74 I2S1_RXRATE 8 8 X_DIVIDER I2S receive MCLK rate numerator 0 rw
75 I2S0_TXBITRATE 0 6 TX_BITRATE I2S transmit bit rate 0 rw
76 I2S1_TXBITRATE 0 6 TX_BITRATE I2S transmit bit rate 0 rw
77 I2S0_RXBITRATE 0 6 RX_BITRATE I2S receive bit rate 0 rw
78 I2S1_RXBITRATE 0 6 RX_BITRATE I2S receive bit rate 0 rw
79 I2S0_TXMODE 0 2 TXCLKSEL Clock source selection for the transmit bit clock divider 0 rw
80 I2S0_TXMODE 2 1 TX4PIN Transmit 4-pin mode selection 0 rw
81 I2S0_TXMODE 3 1 TXMCENA Enable for the TX_MCLK output 0 rw
82 I2S1_TXMODE 0 2 TXCLKSEL Clock source selection for the transmit bit clock divider 0 rw
83 I2S1_TXMODE 2 1 TX4PIN Transmit 4-pin mode selection 0 rw
84 I2S1_TXMODE 3 1 TXMCENA Enable for the TX_MCLK output 0 rw
85 I2S0_RXMODE 0 2 RXCLKSEL Clock source selection for the receive bit clock divider 0 rw
86 I2S0_RXMODE 2 1 RX4PIN Receive 4-pin mode selection 0 rw
87 I2S0_RXMODE 3 1 RXMCENA Enable for the RX_MCLK output 0 rw
88 I2S1_RXMODE 0 2 RXCLKSEL Clock source selection for the receive bit clock divider 0 rw
89 I2S1_RXMODE 2 1 RX4PIN Receive 4-pin mode selection 0 rw
90 I2S1_RXMODE 3 1 RXMCENA Enable for the RX_MCLK output 0 rw