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csv contributions from GNU Radio Conference 2012 HackFest. Thanks, David!

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This commit is contained in:
Michael Ossmann
2012-09-27 19:36:41 -06:00
committed by Piotr Esden-Tempski
parent df2ac8bbac
commit 299806bc4e
5 changed files with 290 additions and 0 deletions
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scripts/data/lpc43xx/adc.csv Normal file
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ADC0_CR,0,8,SEL,Selects which of the ADCn_[7:0] inputs are to be sampled and converted,0,rw
ADC0_CR,8,8,CLKDIV,The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter,0,rw
ADC0_CR,16,1,BURST,Controls Burst mode,0,rw
ADC0_CR,17,3,CLKS,"This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).",0,rw
ADC0_CR,21,1,PDN,Power mode,0,rw
ADC0_CR,24,3,START,Controls the start of an A/D conversion when the BURST bit is 0,0,rw
ADC0_CR,27,1,EDGE,Controls rising or falling edge on the selected signal for the start of a conversion,0,rw
ADC1_CR,0,8,SEL,Selects which of the ADCn_[7:0] inputs are to be sampled and converted,0,rw
ADC1_CR,8,8,CLKDIV,The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter,0,rw
ADC1_CR,16,1,BURST,Controls Burst mode,0,rw
ADC1_CR,17,3,CLKS,"This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits).",0,rw
ADC1_CR,21,1,PDN,Power mode,0,rw
ADC1_CR,24,3,START,Controls the start of an A/D conversion when the BURST bit is 0,0,rw
ADC1_CR,27,1,EDGE,Controls rising or falling edge on the selected signal for the start of a conversion,0,rw
ADC0_GDR,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin",0,r
ADC0_GDR,24,3,CHN,These bits contain the channel from which the LS bits were converted,0,r
ADC0_GDR,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits,0,r
ADC0_GDR,31,1,DONE,This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written,0,r
ADC1_GDR,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin",0,r
ADC1_GDR,24,3,CHN,These bits contain the channel from which the LS bits were converted,0,r
ADC1_GDR,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits,0,r
ADC1_GDR,31,1,DONE,This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written,0,r
ADC0_INTEN,0,8,ADINTEN,These bits allow control over which A/D channels generate interrupts for conversion completion,0,rw
ADC0_INTEN,8,1,ADGINTEN,"When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.",1,rw
ADC1_INTEN,0,8,ADINTEN,These bits allow control over which A/D channels generate interrupts for conversion completion,0,rw
ADC1_INTEN,8,1,ADGINTEN,"When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts.",1,rw
ADC0_DR0,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR0,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR0,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR0,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR0,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR0,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR1,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR1,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR1,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR1,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR1,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR1,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR2,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR2,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR2,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR2,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR2,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR2,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR3,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR3,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR3,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR3,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR3,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR3,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR4,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR4,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR4,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR4,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR4,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR4,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR5,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR5,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR5,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR5,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR5,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR5,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR6,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR6,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR6,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR6,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR6,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR6,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_DR7,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin",0,r
ADC0_DR7,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC0_DR7,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC1_DR7,6,10,V_VREF,"When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin",0,r
ADC1_DR7,30,1,OVERRUN,This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.,0,r
ADC1_DR7,31,1,DONE,This bit is set to 1 when an A/D conversion completes.,0,r
ADC0_STAT,0,8,DONE,These bits mirror the DONE status flags that appear in the result register for each A/D channel.,0,r
ADC0_STAT,8,8,OVERRUN,These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel.,0,r
ADC0_STAT,16,1,ADINT,This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.,0,r
1 ADC0_CR 0 8 SEL Selects which of the ADCn_[7:0] inputs are to be sampled and converted 0 rw
2 ADC0_CR 8 8 CLKDIV The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter 0 rw
3 ADC0_CR 16 1 BURST Controls Burst mode 0 rw
4 ADC0_CR 17 3 CLKS This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). 0 rw
5 ADC0_CR 21 1 PDN Power mode 0 rw
6 ADC0_CR 24 3 START Controls the start of an A/D conversion when the BURST bit is 0 0 rw
7 ADC0_CR 27 1 EDGE Controls rising or falling edge on the selected signal for the start of a conversion 0 rw
8 ADC1_CR 0 8 SEL Selects which of the ADCn_[7:0] inputs are to be sampled and converted 0 rw
9 ADC1_CR 8 8 CLKDIV The ADC clock is divided by the CLKDIV value plus one to produce the clock for the A/D converter 0 rw
10 ADC1_CR 16 1 BURST Controls Burst mode 0 rw
11 ADC1_CR 17 3 CLKS This field selects the number of clocks used for each conversion in Burst mode and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). 0 rw
12 ADC1_CR 21 1 PDN Power mode 0 rw
13 ADC1_CR 24 3 START Controls the start of an A/D conversion when the BURST bit is 0 0 rw
14 ADC1_CR 27 1 EDGE Controls rising or falling edge on the selected signal for the start of a conversion 0 rw
15 ADC0_GDR 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin 0 r
16 ADC0_GDR 24 3 CHN These bits contain the channel from which the LS bits were converted 0 r
17 ADC0_GDR 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits 0 r
18 ADC0_GDR 31 1 DONE This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written 0 r
19 ADC1_GDR 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn pin selected by the SEL field, divided by the reference voltage on the VDDA pin 0 r
20 ADC1_GDR 24 3 CHN These bits contain the channel from which the LS bits were converted 0 r
21 ADC1_GDR 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits 0 r
22 ADC1_GDR 31 1 DONE This bit is set to 1 when an analog-to-digital conversion completes. It is cleared when this register is read and when the AD0/1CR register is written 0 r
23 ADC0_INTEN 0 8 ADINTEN These bits allow control over which A/D channels generate interrupts for conversion completion 0 rw
24 ADC0_INTEN 8 1 ADGINTEN When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. 1 rw
25 ADC1_INTEN 0 8 ADINTEN These bits allow control over which A/D channels generate interrupts for conversion completion 0 rw
26 ADC1_INTEN 8 1 ADGINTEN When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. 1 rw
27 ADC0_DR0 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin 0 r
28 ADC0_DR0 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
29 ADC0_DR0 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
30 ADC1_DR0 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC0 pin divided by the reference voltage on the VDDA pin 0 r
31 ADC1_DR0 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
32 ADC1_DR0 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
33 ADC0_DR1 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin 0 r
34 ADC0_DR1 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
35 ADC0_DR1 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
36 ADC1_DR1 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC1 pin divided by the reference voltage on the VDDA pin 0 r
37 ADC1_DR1 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
38 ADC1_DR1 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
39 ADC0_DR2 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin 0 r
40 ADC0_DR2 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
41 ADC0_DR2 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
42 ADC1_DR2 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC2 pin divided by the reference voltage on the VDDA pin 0 r
43 ADC1_DR2 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
44 ADC1_DR2 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
45 ADC0_DR3 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin 0 r
46 ADC0_DR3 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
47 ADC0_DR3 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
48 ADC1_DR3 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC3 pin divided by the reference voltage on the VDDA pin 0 r
49 ADC1_DR3 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
50 ADC1_DR3 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
51 ADC0_DR4 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin 0 r
52 ADC0_DR4 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
53 ADC0_DR4 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
54 ADC1_DR4 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC4 pin divided by the reference voltage on the VDDA pin 0 r
55 ADC1_DR4 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
56 ADC1_DR4 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
57 ADC0_DR5 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin 0 r
58 ADC0_DR5 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
59 ADC0_DR5 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
60 ADC1_DR5 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC5 pin divided by the reference voltage on the VDDA pin 0 r
61 ADC1_DR5 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
62 ADC1_DR5 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
63 ADC0_DR6 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin 0 r
64 ADC0_DR6 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
65 ADC0_DR6 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
66 ADC1_DR6 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC6 pin divided by the reference voltage on the VDDA pin 0 r
67 ADC1_DR6 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
68 ADC1_DR6 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
69 ADC0_DR7 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin 0 r
70 ADC0_DR7 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
71 ADC0_DR7 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
72 ADC1_DR7 6 10 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADC7 pin divided by the reference voltage on the VDDA pin 0 r
73 ADC1_DR7 30 1 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register. 0 r
74 ADC1_DR7 31 1 DONE This bit is set to 1 when an A/D conversion completes. 0 r
75 ADC0_STAT 0 8 DONE These bits mirror the DONE status flags that appear in the result register for each A/D channel. 0 r
76 ADC0_STAT 8 8 OVERRUN These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. 0 r
77 ADC0_STAT 16 1 ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. 0 r