EMTime/libopencm3
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Merge branch 'master' into efm32

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This commit is contained in:
chrysn
2012-05-01 13:49:34 +02:00
parent 99975d9a05 3596075ee0
commit 282891f8a6
14 changed files with 557 additions and 50 deletions
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35
lib/stm32/f1/libopencm3_stm32f1.ld
View File

@@ -38,36 +38,43 @@ SECTIONS
. = ALIGN(4);
*(.rodata*) /* Read-only data */
. = ALIGN(4);
_etext = .;
} >rom
/* exception index - required due to libgcc.a issuing /0 exceptions */
__exidx_start = .;
/*
* Another section used by C++ stuff, appears when using newlib with
* 64bit (long long) printf support
*/
.ARM.extab : {
*(.ARM.extab*)
} >rom
.ARM.exidx : {
*(.ARM.exidx*)
} > rom
__exidx_end = .;
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >rom
. = ORIGIN(ram);
_etext = .;
.data : {
.data : AT (__exidx_end) {
_data = .;
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
_edata = .;
} >ram AT >rom
} >ram
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
_ebss = .;
} >ram
} >ram AT >rom
/* exception unwind data - required due to libgcc.a issuing /0 exceptions */
.ARM.extab : {
*(.ARM.extab*)
} >ram
/*
* The .eh_frame section appears to be used for C++ exception handling.
* You may need to fix this if you're using C++.
*/
/DISCARD/ : { *(.eh_frame) }
. = ALIGN(4);
end = .;

5
lib/stm32/f1/rtc.c
View File

@@ -99,14 +99,13 @@ void rtc_enter_config_mode(void)
void rtc_exit_config_mode(void)
{
/* u32 reg32; */
u32 reg32;
/* Exit configuration mode. */
RTC_CRL &= ~RTC_CRL_CNF;
/* Wait until the RTOFF bit is 1 (our RTC register write finished). */
/* while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0); */
/* TODO: Unnecessary since we poll the bit on config entry(?) */
while ((reg32 = (RTC_CRL & RTC_CRL_RTOFF)) == 0);
}
void rtc_set_alarm_time(u32 alarm_time)

129
lib/stm32/f1/timer.c
View File

@@ -118,8 +118,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
TIM_SR(timer_peripheral) &= ~flag;
}
void timer_set_mode(u32 timer_peripheral, u8 clock_div,
u8 alignment, u8 direction)
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
u32 alignment, u32 direction)
{
u32 cr1;
@@ -914,3 +914,128 @@ u32 timer_get_counter(u32 timer_peripheral)
{
return TIM_CNT(timer_peripheral);
}
void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt)
{
switch (ic) {
case TIM_IC1:
TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1F_MASK;
TIM_CCMR1(timer) |= flt << 4;
break;
case TIM_IC2:
TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2F_MASK;
TIM_CCMR1(timer) |= flt << 12;
break;
case TIM_IC3:
TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3F_MASK;
TIM_CCMR2(timer) |= flt << 4;
break;
case TIM_IC4:
TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4F_MASK;
TIM_CCMR2(timer) |= flt << 12;
break;
}
}
void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc)
{
switch (ic) {
case TIM_IC1:
TIM_CCMR1(timer) &= ~TIM_CCMR1_IC1PSC_MASK;
TIM_CCMR1(timer) |= psc << 2;
break;
case TIM_IC2:
TIM_CCMR1(timer) &= ~TIM_CCMR1_IC2PSC_MASK;
TIM_CCMR1(timer) |= psc << 10;
break;
case TIM_IC3:
TIM_CCMR2(timer) &= ~TIM_CCMR2_IC3PSC_MASK;
TIM_CCMR2(timer) |= psc << 4;
break;
case TIM_IC4:
TIM_CCMR2(timer) &= ~TIM_CCMR2_IC4PSC_MASK;
TIM_CCMR2(timer) |= psc << 10;
break;
}
}
void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in)
{
in &= 3;
if (((ic == TIM_IC2) || (ic == TIM_IC4)) &&
((in == TIM_IC_IN_TI1) || (in = TIM_IC_IN_TI2))) {
/* Input select bits are flipped for these combinations */
in ^= 3;
}
switch (ic) {
case TIM_IC1:
TIM_CCMR1(timer) &= ~TIM_CCMR1_CC1S_MASK;
TIM_CCMR1(timer) |= in;
break;
case TIM_IC2:
TIM_CCMR1(timer) &= ~TIM_CCMR1_CC2S_MASK;
TIM_CCMR1(timer) |= in << 8;
break;
case TIM_IC3:
TIM_CCMR2(timer) &= ~TIM_CCMR2_CC3S_MASK;
TIM_CCMR2(timer) |= in;
break;
case TIM_IC4:
TIM_CCMR2(timer) &= ~TIM_CCMR2_CC4S_MASK;
TIM_CCMR2(timer) |= in << 8;
break;
}
}
void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol)
{
if (pol)
TIM_CCER(timer) |= (0x2 << (ic * 4));
else
TIM_CCER(timer) &= ~(0x2 << (ic * 4));
}
void timer_ic_enable(u32 timer, enum tim_ic_id ic)
{
TIM_CCER(timer) |= (0x1 << (ic * 4));
}
void timer_ic_disable(u32 timer, enum tim_ic_id ic)
{
TIM_CCER(timer) &= ~(0x1 << (ic * 4));
}
void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt)
{
TIM_SMCR(timer) &= ~TIM_SMCR_ETF_MASK;
TIM_SMCR(timer) |= flt << 8;
}
void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc)
{
TIM_SMCR(timer) &= ~TIM_SMCR_ETPS_MASK;
TIM_SMCR(timer) |= psc << 12;
}
void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol)
{
if (pol)
TIM_SMCR(timer) |= TIM_SMCR_ETP;
else
TIM_SMCR(timer) &= ~TIM_SMCR_ETP;
}
void timer_slave_set_mode(u32 timer, u8 mode)
{
TIM_SMCR(timer) &= ~TIM_SMCR_SMS_MASK;
TIM_SMCR(timer) |= mode;
}
void timer_slave_set_trigger(u32 timer, u8 trigger)
{
TIM_SMCR(timer) &= ~TIM_SMCR_TS_MASK;
TIM_SMCR(timer) |= trigger;
}

4
lib/stm32/f1/vector.c
View File

@@ -20,7 +20,7 @@
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s). */
extern unsigned _etext, _data, _edata, _ebss, _stack;
extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -197,7 +197,7 @@ void reset_handler(void)
__asm__("MSR msp, %0" : : "r"(&_stack));
for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)

35
lib/stm32/f2/libopencm3_stm32f2.ld
View File

@@ -38,36 +38,43 @@ SECTIONS
. = ALIGN(4);
*(.rodata*) /* Read-only data */
. = ALIGN(4);
_etext = .;
} >rom
/* exception index - required due to libgcc.a issuing /0 exceptions */
__exidx_start = .;
/*
* Another section used by C++ stuff, appears when using newlib with
* 64bit (long long) printf support
*/
.ARM.extab : {
*(.ARM.extab*)
} >rom
.ARM.exidx : {
*(.ARM.exidx*)
} > rom
__exidx_end = .;
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
} >rom
. = ORIGIN(ram);
_etext = .;
.data : {
.data : AT (__exidx_end) {
_data = .;
*(.data*) /* Read-write initialized data */
. = ALIGN(4);
_edata = .;
} >ram AT >rom
} >ram
.bss : {
*(.bss*) /* Read-write zero initialized data */
*(COMMON)
. = ALIGN(4);
_ebss = .;
} >ram
} >ram AT >rom
/* exception unwind data - required due to libgcc.a issuing /0 exceptions */
.ARM.extab : {
*(.ARM.extab*)
} >ram
/*
* The .eh_frame section appears to be used for C++ exception handling.
* You may need to fix this if you're using C++.
*/
/DISCARD/ : { *(.eh_frame) }
. = ALIGN(4);
end = .;

4
lib/stm32/f2/timer.c
View File

@@ -119,8 +119,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
TIM_SR(timer_peripheral) &= ~flag;
}
void timer_set_mode(u32 timer_peripheral, u8 clock_div,
u8 alignment, u8 direction)
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
u32 alignment, u32 direction)
{
u32 cr1;

4
lib/stm32/f2/vector.c
View File

@@ -21,7 +21,7 @@
#define WEAK __attribute__ ((weak))
/* Symbols exported by the linker script(s): */
extern unsigned _etext, _data, _edata, _ebss, _stack;
extern unsigned __exidx_end, _data, _edata, _ebss, _stack;
void main(void);
void reset_handler(void);
@@ -224,7 +224,7 @@ void reset_handler(void)
__asm__("MSR msp, %0" : : "r"(&_stack));
for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
for (src = &__exidx_end, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
while (dest < &_ebss)

4
lib/stm32/f4/timer.c
View File

@@ -119,8 +119,8 @@ void timer_clear_flag(u32 timer_peripheral, u32 flag)
TIM_SR(timer_peripheral) &= ~flag;
}
void timer_set_mode(u32 timer_peripheral, u8 clock_div,
u8 alignment, u8 direction)
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
u32 alignment, u32 direction)
{
u32 cr1;