Merge branch 'master' into efm32
This commit is contained in:
chrysn
302
include/libopencm3/stm32/dac.h
Normal file
302
include/libopencm3/stm32/dac.h
Normal file
@@ -0,0 +1,302 @@
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||||
/*
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* This file is part of the libopencm3 project.
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*
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||||
* Copyright (C) 2012 Felix Held <felix-libopencm3@felixheld.de>
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||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
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||||
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||||
#ifndef LIBOPENCM3_DAC_H
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#define LIBOPENCM3_DAC_H
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#include <libopencm3/stm32/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/* --- DAC registers ------------------------------------------------------- */
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/* DAC control register (DAC_CR) */
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#define DAC_CR MMIO32(DAC_BASE + 0x00)
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/* DAC software trigger register (DAC_SWTRIGR) */
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#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04)
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/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */
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#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08)
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/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */
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#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C)
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/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */
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#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10)
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/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */
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#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14)
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/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */
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#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18)
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/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */
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#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C)
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/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */
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#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20)
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||||
/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */
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#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24)
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/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */
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#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28)
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/* DAC channel1 data output register (DAC_DOR1) */
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#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C)
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/* DAC channel2 data output register (DAC_DOR2) */
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#define DAC_DOR2 MMIO32(DAC_BASE + 0x30)
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/* --- DAC_CR values ------------------------------------------------------- */
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/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
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/* doesn't exist in most members of the stm32f1 family */
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#define DAC_CR_DMAUDRIE2 (1 << 29)
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/* DMAEN2: DAC channel2 DMA enable */
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#define DAC_CR_DMAEN2 (1 << 28)
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/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */
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/* DAC_CR_MAMP2_n:
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* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
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*/
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#define DAC_CR_MAMP2_SHIFT 24
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#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
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/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
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/* Legend:
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* DIS: wave generation disabled
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* NOISE: Noise wave generation enabled
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* TRI: Triangle wave generation enabled
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*
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* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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*/
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#define DAC_CR_WAVE2_SHIFT 22
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#define DAC_CR_WAVE2_DIS (0x0 << DAC_CR_WAVE2_SHIFT)
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#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
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#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
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/* TSEL2[2:0]: DAC channel2 trigger selection */
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/* Legend:
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*
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* T6: Timer 6 TRGO event
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* T3: Timer 3 TRGO event
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* T8: Timer 8 TRGO event
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* T7: Timer 7 TRGO event
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* T5: Timer 5 TRGO event
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* T15: Timer 15 TRGO event
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* T2: Timer 2 TRGO event
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* T4: Timer 4 TRGO event
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* E9: External line9
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* SW: Software trigger
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*
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||||
* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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* Note: T3 == T8; T5 == T15; not both present on one device
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||||
* Note: this is *not* valid for the STM32L1 family
|
||||
*/
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#define DAC_CR_TSEL2_SHIFT 19
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#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
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||||
#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
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||||
#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
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||||
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||||
/* TEN2: DAC channel2 trigger enable */
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||||
#define DAC_CR_TEN2 (1 << 18)
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||||
|
||||
/* BOFF2: DAC channel2 output buffer disable */
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||||
#define DAC_CR_BOFF2 (1 << 17)
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||||
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||||
/* EN2: DAC channel2 enable */
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||||
#define DAC_CR_EN2 (1 << 16)
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||||
|
||||
/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
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||||
/* doesn't exist in most members of the stm32f1 family */
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||||
#define DAC_CR_DMAUDRIE1 (1 << 13)
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||||
/* DMAEN1: DAC channel1 DMA enable */
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||||
#define DAC_CR_DMAEN1 (1 << 12)
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||||
/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */
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||||
/* DAC_CR_MAMP1_n:
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* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
|
||||
*/
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||||
#define DAC_CR_MAMP1_SHIFT 8
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#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
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/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
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/* Legend:
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* DIS: wave generation disabled
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* NOISE: Noise wave generation enabled
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* TRI: Triangle wave generation enabled
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*
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* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
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*/
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#define DAC_CR_WAVE1_SHIFT 6
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#define DAC_CR_WAVE1_DIS (0x0 << DAC_CR_WAVE1_SHIFT)
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#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
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#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
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/* TSEL1[2:0]: DAC channel1 trigger selection */
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/* Legend:
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*
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* T6: Timer 6 TRGO event
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* T3: Timer 3 TRGO event in connectivity line devices
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* T8: Timer 8 TRGO event in high-density and XL-density devices
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* T7: Timer 7 TRGO event
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* T5: Timer 5 TRGO event
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* T15: Timer 15 TRGO event
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* T2: Timer 2 TRGO event
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* T4: Timer 4 TRGO event
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* E9: External line9
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* SW: Software trigger
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*
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* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
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* Note: T3 == T8; T5 == T15; not both present on one device
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* Note: this is *not* valid for the STM32L1 family
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*/
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#define DAC_CR_TSEL1_SHIFT 3
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#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
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/* TEN1: DAC channel1 trigger enable */
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#define DAC_CR_TEN1 (1 << 2)
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/* BOFF1: DAC channel1 output buffer disable */
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#define DAC_CR_BOFF1 (1 << 1)
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/* EN1: DAC channel1 enable */
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#define DAC_CR_EN1 (1 << 0)
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/* --- DAC_SWTRIGR values -------------------------------------------------- */
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/* SWTRIG2: DAC channel2 software trigger */
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#define DAC_SWTRIGR_SWTRIG2 (1 << 1)
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/* SWTRIG1: DAC channel1 software trigger */
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#define DAC_SWTRIGR_SWTRIG1 (1 << 0)
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||||
|
||||
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/* --- DAC_DHR12R1 values -------------------------------------------------- */
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#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0)
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#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0)
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||||
|
||||
|
||||
/* --- DAC_DHR12L1 values -------------------------------------------------- */
|
||||
#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4)
|
||||
#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4)
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||||
|
||||
|
||||
/* --- DAC_DHR8R1 values --------------------------------------------------- */
|
||||
#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0)
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||||
#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0)
|
||||
|
||||
|
||||
/* --- DAC_DHR12R2 values -------------------------------------------------- */
|
||||
#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0)
|
||||
#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0)
|
||||
|
||||
|
||||
/* --- DAC_DHR12L2 values -------------------------------------------------- */
|
||||
#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4)
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||||
#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4)
|
||||
|
||||
|
||||
/* --- DAC_DHR8R2 values --------------------------------------------------- */
|
||||
#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0)
|
||||
#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0)
|
||||
|
||||
|
||||
/* --- DAC_DHR12RD values -------------------------------------------------- */
|
||||
#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16)
|
||||
#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16)
|
||||
#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0)
|
||||
#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0)
|
||||
|
||||
|
||||
/* --- DAC_DHR12LD values -------------------------------------------------- */
|
||||
#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16)
|
||||
#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20)
|
||||
#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0)
|
||||
#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4)
|
||||
|
||||
|
||||
/* --- DAC_DHR8RD values --------------------------------------------------- */
|
||||
#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8)
|
||||
#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8)
|
||||
#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0)
|
||||
#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0)
|
||||
|
||||
|
||||
/* --- DAC_DOR1 values ----------------------------------------------------- */
|
||||
#define DAC_DOR1_DACC1DOR_LSB (1 << 0)
|
||||
#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0)
|
||||
|
||||
|
||||
/* --- DAC_DOR2 values ----------------------------------------------------- */
|
||||
#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
|
||||
#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
|
||||
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
|
||||
/* TODO */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -252,14 +252,14 @@
|
||||
#define DMA_CCR_MSIZE_8BIT (0x0 << 10)
|
||||
#define DMA_CCR_MSIZE_16BIT (0x1 << 10)
|
||||
#define DMA_CCR_MSIZE_32BIT (0x2 << 10)
|
||||
#define DMA_CCR_MSIZE_MASK (0x2 << 10)
|
||||
#define DMA_CCR_MSIZE_MASK (0x3 << 10)
|
||||
#define DMA_CCR_MSIZE_SHIFT 10
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
|
||||
#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
|
||||
#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
|
||||
#define DMA_CCR_PSIZE_MASK (0x2 << 8)
|
||||
#define DMA_CCR_PSIZE_MASK (0x3 << 8)
|
||||
#define DMA_CCR_PSIZE_SHIFT 8
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
|
||||
@@ -23,6 +23,7 @@
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
#include <libopencm3/stm32/f1/rcc.h>
|
||||
|
||||
/* --- RTC registers ------------------------------------------------------- */
|
||||
|
||||
|
||||
@@ -533,8 +533,8 @@
|
||||
/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in
|
||||
* TIMx_CCER). */
|
||||
#define TIM_CCMR1_CC1S_OUT (0x0 << 0)
|
||||
#define TIM_CCMR1_CC1S_IN_TI2 (0x1 << 0)
|
||||
#define TIM_CCMR1_CC1S_IN_TI1 (0x2 << 0)
|
||||
#define TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0)
|
||||
#define TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0)
|
||||
#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0)
|
||||
#define TIM_CCMR1_CC1S_MASK (0x3 << 0)
|
||||
|
||||
@@ -851,14 +851,66 @@ enum tim_oc_mode {
|
||||
TIM_OCM_PWM2,
|
||||
};
|
||||
|
||||
/* Input Capture channel designators */
|
||||
enum tim_ic_id {
|
||||
TIM_IC1,
|
||||
TIM_IC2,
|
||||
TIM_IC3,
|
||||
TIM_IC4,
|
||||
};
|
||||
|
||||
/* Input Capture input filter */
|
||||
enum tim_ic_filter {
|
||||
TIM_IC_OFF,
|
||||
TIM_IC_CK_INT_N_2,
|
||||
TIM_IC_CK_INT_N_4,
|
||||
TIM_IC_CK_INT_N_8,
|
||||
TIM_IC_DTF_DIV_2_N_6,
|
||||
TIM_IC_DTF_DIV_2_N_8,
|
||||
TIM_IC_DTF_DIV_4_N_6,
|
||||
TIM_IC_DTF_DIV_4_N_8,
|
||||
TIM_IC_DTF_DIV_8_N_6,
|
||||
TIM_IC_DTF_DIV_8_N_8,
|
||||
TIM_IC_DTF_DIV_16_N_5,
|
||||
TIM_IC_DTF_DIV_16_N_6,
|
||||
TIM_IC_DTF_DIV_16_N_8,
|
||||
TIM_IC_DTF_DIV_32_N_5,
|
||||
TIM_IC_DTF_DIV_32_N_6,
|
||||
TIM_IC_DTF_DIV_32_N_8,
|
||||
};
|
||||
|
||||
/* Input Capture input prescaler */
|
||||
enum tim_ic_psc {
|
||||
TIM_IC_PSC_OFF,
|
||||
TIM_IC_PSC_2,
|
||||
TIM_IC_PSC_4,
|
||||
TIM_IC_PSC_8,
|
||||
};
|
||||
|
||||
/* Input Capture input prescaler */
|
||||
enum tim_ic_input {
|
||||
TIM_IC_OUT = 0,
|
||||
TIM_IC_IN_TI1 = 1,
|
||||
TIM_IC_IN_TI2 = 2,
|
||||
TIM_IC_IN_TRC = 3,
|
||||
TIM_IC_IN_TI3 = 5,
|
||||
TIM_IC_IN_TI4 = 6,
|
||||
};
|
||||
|
||||
/* Input Capture input prescaler */
|
||||
enum tim_ic_pol {
|
||||
TIM_IC_RISING,
|
||||
TIM_IC_FALLING,
|
||||
};
|
||||
|
||||
/* --- TIM functions ------------------------------------------------------- */
|
||||
void timer_reset(u32 timer_peripheral);
|
||||
void timer_enable_irq(u32 timer_peripheral, u32 irq);
|
||||
void timer_disable_irq(u32 timer_peripheral, u32 irq);
|
||||
bool timer_get_flag(u32 timer_peripheral, u32 flag);
|
||||
void timer_clear_flag(u32 timer_peripheral, u32 flag);
|
||||
void timer_set_mode(u32 timer_peripheral, u8 clock_div,
|
||||
u8 alignment, u8 direction);
|
||||
void timer_set_mode(u32 timer_peripheral, u32 clock_div,
|
||||
u32 alignment, u32 direction);
|
||||
void timer_set_clock_division(u32 timer_peripheral, u32 clock_div);
|
||||
void timer_enable_preload(u32 timer_peripheral);
|
||||
void timer_disable_preload(u32 timer_peripheral);
|
||||
@@ -918,4 +970,17 @@ void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
|
||||
void timer_generate_event(u32 timer_peripheral, u32 event);
|
||||
u32 timer_get_counter(u32 timer_peripheral);
|
||||
|
||||
void timer_ic_set_filter(u32 timer, enum tim_ic_id ic, enum tim_ic_filter flt);
|
||||
void timer_ic_set_prescaler(u32 timer, enum tim_ic_id ic, enum tim_ic_psc psc);
|
||||
void timer_ic_set_input(u32 timer, enum tim_ic_id ic, enum tim_ic_input in);
|
||||
void timer_ic_set_polarity(u32 timer, enum tim_ic_id ic, enum tim_ic_pol pol);
|
||||
void timer_ic_enable(u32 timer, enum tim_ic_id ic);
|
||||
void timer_ic_disable(u32 timer, enum tim_ic_id ic);
|
||||
|
||||
void timer_slave_set_filter(u32 timer, enum tim_ic_filter flt);
|
||||
void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc);
|
||||
void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol);
|
||||
void timer_slave_set_mode(u32 timer, u8 mode);
|
||||
void timer_slave_set_trigger(u32 timer, u8 trigger);
|
||||
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user