stm32: unify bulk of adc convenience functions
This unifies stm32f1, l1, and f4 convenience functions for adc. The code should be useable for f2 and f37x as well, but that needs hardware for testing, and there was no existing implementation. This is the reason for the "adc_common_v1.c" name, as trying to put all the different families into the common file name has become too cumbersome. All of the deprecated routines have been dropped, they've been marked deprecated for a very long time now, and porting them seemed unnecessary. This has been tested on f1, l1 and f4 discovery boards, and is based on some existing l1/f1 unification code from https://github.com/karlp/libopencm3/tree/rme_l1_master
This commit is contained in:
Karl Palsson
committed by
Karl Palsson
Karl Palsson
parent
3eaeaf693c
commit
27bc12de61
@@ -36,7 +36,7 @@ CFLAGS = -Os -g \
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
|
||||
OBJS = adc.o can.o gpio.o pwr.o rcc.o rtc.o crypto.o
|
||||
OBJS = adc.o adc_common_v1.o can.o gpio.o pwr.o rcc.o rtc.o crypto.o
|
||||
|
||||
OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
|
||||
gpio_common_all.o gpio_common_f0234.o i2c_common_all.o \
|
||||
|
||||
@@ -86,411 +86,6 @@ LGPL License Terms @ref lgpl_license
|
||||
|
||||
/**@{*/
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Off
|
||||
|
||||
Turn off the ADC to reduce power consumption to a few microamps.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_off(uint32_t adc)
|
||||
{
|
||||
ADC_CR2(adc) &= ~ADC_CR2_ADON;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Analog Watchdog for Regular Conversions
|
||||
|
||||
The analog watchdog allows the monitoring of an analog signal between two
|
||||
threshold levels. The thresholds must be preset. Comparison is done before data
|
||||
alignment takes place, so the thresholds are left-aligned.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_analog_watchdog_regular(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_AWDEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Analog Watchdog for Regular Conversions
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_analog_watchdog_regular(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_AWDEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Analog Watchdog for Injected Conversions
|
||||
|
||||
The analog watchdog allows the monitoring of an analog signal between two
|
||||
threshold levels. The thresholds must be preset. Comparison is done before data
|
||||
alignment takes place, so the thresholds are left-aligned.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_analog_watchdog_injected(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_JAWDEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Analog Watchdog for Injected Conversions
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_analog_watchdog_injected(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_JAWDEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Discontinuous Mode for Regular Conversions
|
||||
|
||||
In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the
|
||||
defined regular channel group. The subgroup is defined by the number of
|
||||
consecutive channels to be converted. After a subgroup has been converted
|
||||
the next trigger will start conversion of the immediately following subgroup
|
||||
of the same length or until the whole group has all been converted. When the
|
||||
the whole group has been converted, the next trigger will restart conversion
|
||||
of the subgroup at the beginning of the whole group.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] length Unsigned int8. Number of channels in the group @ref
|
||||
adc_cr1_discnum
|
||||
*/
|
||||
|
||||
void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length)
|
||||
{
|
||||
if ((length-1) > 7) {
|
||||
return;
|
||||
}
|
||||
ADC_CR1(adc) |= ADC_CR1_DISCEN;
|
||||
ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Discontinuous Mode for Regular Conversions
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_discontinuous_mode_regular(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Discontinuous Mode for Injected Conversions
|
||||
|
||||
In this mode the ADC converts sequentially one channel of the defined group of
|
||||
injected channels, cycling back to the first channel in the group once the
|
||||
entire group has been converted.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_discontinuous_mode_injected(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Discontinuous Mode for Injected Conversions
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_discontinuous_mode_injected(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Automatic Injected Conversions
|
||||
|
||||
The ADC converts a defined injected group of channels immediately after the
|
||||
regular channels have been converted. The external trigger on the injected
|
||||
channels is disabled as required.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_automatic_injected_group_conversion(uint32_t adc)
|
||||
{
|
||||
adc_disable_external_trigger_injected(adc);
|
||||
ADC_CR1(adc) |= ADC_CR1_JAUTO;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Automatic Injected Conversions
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_automatic_injected_group_conversion(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_JAUTO;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels
|
||||
|
||||
The analog watchdog allows the monitoring of an analog signal between two
|
||||
threshold levels. The thresholds must be preset. Comparison is done before data
|
||||
alignment takes place, so the thresholds are left-aligned.
|
||||
|
||||
@note The analog watchdog must be enabled for either or both of the regular or
|
||||
injected channels. If neither are enabled, the analog watchdog feature will be
|
||||
disabled.
|
||||
@ref adc_enable_analog_watchdog_injected, @ref
|
||||
adc_enable_analog_watchdog_regular.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Analog Watchdog for a Selected Channel
|
||||
|
||||
The analog watchdog allows the monitoring of an analog signal between two
|
||||
threshold levels. The thresholds must be preset. Comparison is done before data
|
||||
alignment takes place, so the thresholds are left-aligned.
|
||||
|
||||
@note The analog watchdog must be enabled for either or both of the regular or
|
||||
injected channels. If neither are enabled, the analog watchdog feature will be
|
||||
disabled. If both are enabled, the same channel number is monitored.
|
||||
@ref adc_enable_analog_watchdog_injected, @ref
|
||||
adc_enable_analog_watchdog_regular.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel
|
||||
*/
|
||||
|
||||
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
|
||||
uint8_t channel)
|
||||
{
|
||||
uint32_t reg32;
|
||||
|
||||
reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */
|
||||
if (channel < 18) {
|
||||
reg32 |= channel;
|
||||
}
|
||||
ADC_CR1(adc) = reg32;
|
||||
ADC_CR1(adc) |= ADC_CR1_AWDSGL;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set Scan Mode
|
||||
|
||||
In this mode a conversion consists of a scan of the predefined set of channels,
|
||||
regular and injected, each channel conversion immediately following the
|
||||
previous one. It can use single, continuous or discontinuous mode.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_scan_mode(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_SCAN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Scan Mode
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_scan_mode(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_SCAN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Injected End-Of-Conversion Interrupt
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_eoc_interrupt_injected(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Injected End-Of-Conversion Interrupt
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_eoc_interrupt_injected(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Analog Watchdog Interrupt
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_awd_interrupt(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_AWDIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Analog Watchdog Interrupt
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_awd_interrupt(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_AWDIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Regular End-Of-Conversion Interrupt
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_eoc_interrupt(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_EOCIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable Regular End-Of-Conversion Interrupt
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_eoc_interrupt(uint32_t adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_EOCIE;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Software Triggered Conversion on Regular Channels
|
||||
|
||||
This starts conversion on a set of defined regular channels. It is cleared by
|
||||
hardware once conversion starts.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_start_conversion_regular(uint32_t adc)
|
||||
{
|
||||
/* Start conversion on regular channels. */
|
||||
ADC_CR2(adc) |= ADC_CR2_SWSTART;
|
||||
|
||||
/* Wait until the ADC starts the conversion. */
|
||||
while (ADC_CR2(adc) & ADC_CR2_SWSTART);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Software Triggered Conversion on Injected Channels
|
||||
|
||||
This starts conversion on a set of defined injected channels. It is cleared by
|
||||
hardware once conversion starts.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_start_conversion_injected(uint32_t adc)
|
||||
{
|
||||
/* Start conversion on injected channels. */
|
||||
ADC_CR2(adc) |= ADC_CR2_JSWSTART;
|
||||
|
||||
/* Wait until the ADC starts the conversion. */
|
||||
while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set the Data as Left Aligned
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_set_left_aligned(uint32_t adc)
|
||||
{
|
||||
ADC_CR2(adc) |= ADC_CR2_ALIGN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set the Data as Right Aligned
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_set_right_aligned(uint32_t adc)
|
||||
{
|
||||
ADC_CR2(adc) &= ~ADC_CR2_ALIGN;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable DMA Transfers
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_dma(uint32_t adc)
|
||||
{
|
||||
ADC_CR2(adc) |= ADC_CR2_DMA;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Disable DMA Transfers
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_dma(uint32_t adc)
|
||||
{
|
||||
ADC_CR2(adc) &= ~ADC_CR2_DMA;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Continuous Conversion Mode
|
||||
|
||||
In this mode the ADC starts a new conversion of a single channel or a channel
|
||||
group immediately following completion of the previous channel group conversion.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_set_continuous_conversion_mode(uint32_t adc)
|
||||
{
|
||||
ADC_CR2(adc) |= ADC_CR2_CONT;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Enable Single Conversion Mode
|
||||
|
||||
In this mode the ADC performs a conversion of one channel or a channel group
|
||||
and stops.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_set_single_conversion_mode(uint32_t adc)
|
||||
{
|
||||
ADC_CR2(adc) &= ~ADC_CR2_CONT;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set the Sample Time for a Single Channel
|
||||
|
||||
@@ -500,6 +95,7 @@ The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
|
||||
@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref
|
||||
adc_channel
|
||||
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
|
||||
* NOTE Common with f1, f2 and f37x
|
||||
*/
|
||||
|
||||
void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
|
||||
@@ -527,6 +123,7 @@ for all channels.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
|
||||
* NOTE Common with f1, f2 and f37x
|
||||
*/
|
||||
|
||||
void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
|
||||
@@ -545,218 +142,13 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
|
||||
ADC_SMPR1(adc) = reg32;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set Analog Watchdog Upper Threshold
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] threshold Unsigned int8. Upper threshold value
|
||||
*/
|
||||
|
||||
void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold)
|
||||
{
|
||||
uint32_t reg32 = 0;
|
||||
|
||||
reg32 = (uint32_t)threshold;
|
||||
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
|
||||
ADC_HTR(adc) = reg32;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set Analog Watchdog Lower Threshold
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] threshold Unsigned int8. Lower threshold value
|
||||
*/
|
||||
|
||||
void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold)
|
||||
{
|
||||
uint32_t reg32 = 0;
|
||||
|
||||
reg32 = (uint32_t)threshold;
|
||||
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
|
||||
ADC_LTR(adc) = reg32;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set a Regular Channel Conversion Sequence
|
||||
|
||||
Define a sequence of channels to be converted as a regular group with a length
|
||||
from 1 to 16 channels. If this is called during conversion, the current
|
||||
conversion is reset and conversion begins again with the newly defined group.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] length Unsigned int8. Number of channels in the group.
|
||||
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18.
|
||||
*/
|
||||
|
||||
void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
|
||||
{
|
||||
uint32_t reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
|
||||
uint8_t i = 0;
|
||||
|
||||
/* Maximum sequence length is 16 channels. */
|
||||
if (length > 16) {
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 1; i <= length; i++) {
|
||||
if (i <= 6) {
|
||||
reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
|
||||
}
|
||||
if ((i > 6) & (i <= 12)) {
|
||||
reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
|
||||
}
|
||||
if ((i > 12) & (i <= 16)) {
|
||||
reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
|
||||
}
|
||||
}
|
||||
reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB);
|
||||
|
||||
ADC_SQR1(adc) = reg32_1;
|
||||
ADC_SQR2(adc) = reg32_2;
|
||||
ADC_SQR3(adc) = reg32_3;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set an Injected Channel Conversion Sequence
|
||||
|
||||
Defines a sequence of channels to be converted as an injected group with a
|
||||
length from 1 to 4 channels. If this is called during conversion, the current
|
||||
conversion is reset and conversion begins again with the newly defined group.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] length Unsigned int8. Number of channels in the group.
|
||||
@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18
|
||||
*/
|
||||
|
||||
void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[])
|
||||
{
|
||||
uint32_t reg32 = 0;
|
||||
uint8_t i = 0;
|
||||
|
||||
/* Maximum sequence length is 4 channels. Minimum sequence is 1.*/
|
||||
if ((length - 1) > 3) {
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i < length; i++) {
|
||||
reg32 |= ADC_JSQR_JSQ_VAL(4 - i, channel[length - i - 1]);
|
||||
}
|
||||
|
||||
reg32 |= ADC_JSQR_JL_VAL(length);
|
||||
|
||||
ADC_JSQR(adc) = reg32;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Read the End-of-Conversion Flag
|
||||
|
||||
This flag is set after all channels of a regular or injected group have been
|
||||
converted.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@returns bool. End of conversion flag.
|
||||
*/
|
||||
|
||||
bool adc_eoc(uint32_t adc)
|
||||
{
|
||||
return (ADC_SR(adc) & ADC_SR_EOC) != 0;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
|
||||
|
||||
This flag is set after all channels of an injected group have been converted.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@returns bool. End of conversion flag.
|
||||
*/
|
||||
|
||||
bool adc_eoc_injected(uint32_t adc)
|
||||
{
|
||||
return (ADC_SR(adc) & ADC_SR_JEOC) != 0;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Read from the Regular Conversion Result Register
|
||||
|
||||
The result read back is 12 bits, right or left aligned within the first 16 bits.
|
||||
For ADC1 only, the higher 16 bits will hold the result from ADC2 if
|
||||
an appropriate dual mode has been set @see adc_set_dual_mode.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@returns Unsigned int32 conversion result.
|
||||
*/
|
||||
|
||||
uint32_t adc_read_regular(uint32_t adc)
|
||||
{
|
||||
return ADC_DR(adc);
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Read from an Injected Conversion Result Register
|
||||
|
||||
The result read back from the selected injected result register (one of four)
|
||||
is 12 bits, right or left aligned within the first 16 bits. The result can have
|
||||
a negative value if the injected channel offset has been set @see
|
||||
adc_set_injected_offset.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] reg Unsigned int8. Register number (1 ... 4).
|
||||
@returns Unsigned int32 conversion result.
|
||||
*/
|
||||
|
||||
uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case 1:
|
||||
return ADC_JDR1(adc);
|
||||
case 2:
|
||||
return ADC_JDR2(adc);
|
||||
case 3:
|
||||
return ADC_JDR3(adc);
|
||||
case 4:
|
||||
return ADC_JDR4(adc);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set the Injected Channel Data Offset
|
||||
|
||||
This value is subtracted from the injected channel results after conversion is
|
||||
complete, and can result in negative results. A separate value can be specified
|
||||
for each injected data register.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] reg Unsigned int8. Register number (1 ... 4).
|
||||
@param[in] offset Unsigned int32.
|
||||
*/
|
||||
|
||||
void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
|
||||
{
|
||||
switch (reg) {
|
||||
case 1:
|
||||
ADC_JOFR1(adc) = offset;
|
||||
break;
|
||||
case 2:
|
||||
ADC_JOFR2(adc) = offset;
|
||||
break;
|
||||
case 3:
|
||||
ADC_JOFR3(adc) = offset;
|
||||
break;
|
||||
case 4:
|
||||
ADC_JOFR4(adc) = offset;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/** @brief ADC Power On
|
||||
|
||||
If the ADC is in power-down mode then it is powered up. The application needs
|
||||
to wait a time of about 3 microseconds for stabilization before using the ADC.
|
||||
If the ADC is already on this function call will have no effect.
|
||||
* NOTE Common with L1 and F2
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user