pac55xx: adding memctl for flash/sram access, and clock/pll configuration functions.
Merge-conflict: took _prior_ verision of CCS_MUXSELR_MASK_PIN as bracketing of (pin) seemed more correct!
This commit is contained in:
Kevin Stefanik
committed by
Karl Palsson
Karl Palsson
parent
245761f894
commit
253a091936
@@ -4,6 +4,7 @@
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* @defgroup system_defines Clock Config and System Defines
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* @ingroup PAC55xx_defines
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* @author Brian Viele <vielster@allocor.tech>
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* @author Kevin Stefanik <kevin@allocor.tech>
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* LGPL License Terms @ref lgpl_license
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* @date 1 Dec 2019
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*
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@@ -26,18 +27,95 @@
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_
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#define INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_
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#ifndef LIBOPENCM3_PAC55XX_CCS_H_
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#define LIBOPENCM3_PAC55XX_CCS_H_
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/cm3/memorymap.h>
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#include <libopencm3/pac55xx/memorymap.h>
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#include <libopencm3/pac55xx/memctl.h>
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/**@{*/
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/** Clock Control Registers
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* @defgroup clock_config_regs Clock Config Registers.
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* @{*/
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/** @defgroup ccs_frequencies CCS Frequencies
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@{*/
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/** Ring Oscillator Frequency */
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#define CCS_ROSC_FREQ (16000000U)
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/** Internally generated and trimmed 4MHz clock */
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#define CCS_CLKREF_FREQ ( 4000000U)
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/** Maximum external clock frequency */
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#define CCS_EXTCLK_MAX_FREQ (20000000U)
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/**@}*/
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/** @defgroup ccs_ctl_reg Clock Control Register
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@{*/
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#define CCSCTL MMIO32(SCC_BASE)
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#define CCS_CTL_FRCLKMUXSEL_MASK (0x03)
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#define CCS_CTL_FRCLKMUXSEL(sel) ((sel) & CCS_CTL_FRCLKMUXSEL_MASK)
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#define CCS_CTL_FRCLKMUXSEL_ROSC (0)
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#define CCS_CTL_FRCLKMUXSEL_CLKREF (1)
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#define CCS_CTL_FRCLKMUXSEL_EXTCLK (3)
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#define CCS_CTL_ROSCEN BIT2
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#define CCS_CTL_SCLKMUXSEL BIT4
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#define CCS_CTL_SCLKMUXSEL_FRCLK (0)
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#define CCS_CTL_SCLKMUXSEL_PLLCLK (1)
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#define CCS_CTL_CLKFAILEN BIT5
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#define CCS_CTL_CLKFAILMUXSEL BIT6
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#define CCS_CTL_CLKFAILIF BIT7
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#define CCS_CTL_LDOEN BIT8
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#define CCS_CTL_SWRESET BIT11
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#define CCS_CTL_PCLKEN BIT12
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#define CCS_CTL_ACLKEN BIT13
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#define CCS_CTL_ADCCLKEN BIT14
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#define CCS_CTL_STCLKSLPEN BIT15
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#define CCS_CTL_PCLKDIV_MASK (0x07)
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#define CCS_CTL_PCLKDIV_SHIFT (16)
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/* Supported PCLK divisors: 1-8 */
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#define CCS_CTL_PCLKDIV(div) (((div-1) & CCS_CTL_PCLKDIV_MASK) << CCS_CTL_PCLKDIV_SHIFT)
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#define CCS_CTL_ACLKDIV_MASK (0x07)
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#define CCS_CTL_ACLKDIV_SHIFT (20)
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/* Supported ACLK divisors: 1-8 */
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#define CCS_CTL_ACLKDIV(div) (((div-1) & CCS_CTL_ACLKDIV_MASK) << CCS_CTL_ACLKDIV_SHIFT)
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#define CCS_CTL_HCLKDIV_MASK (0x07)
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#define CCS_CTL_HCLKDIV_SHIFT (24)
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/* Supported HCLK divisors: 1-8 */
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#define CCS_CTL_HCLKDIV(div) (((div-1) & CCS_CTL_HCLKDIV_MASK) << CCS_CTL_HCLKDIV_SHIFT)
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#define CCS_CTL_USAMODE BIT28
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#define CCS_CTL_USBMODE BIT29
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#define CCS_CTL_USCMODE BIT30
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#define CCS_CTL_USDMODE BIT31
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/**@}*/
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/** @defgroup ccs_pllctl_reg CCS PLL Control Register
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@{*/
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#define CCSPLLCTL MMIO32(SCC_BASE + 0x04)
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/** PLL Enable */
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#define CCS_PLLCTL_PLLEN BIT0
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/** PLL Bypass */
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#define CCS_PLLCTL_PLLBP BIT1
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#define CCS_PLLCTL_PLLOUTDIV_MASK (0x03)
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#define CCS_PLLCTL_PLLOUTDIV_SHIFT (2)
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/** PLL Output Divisor */
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#define CCS_PLLCTL_PLLOUTDIV(div) (((div) & CCS_PLLCTL_PLLOUTDIV_MASK) << CCS_PLLCTL_PLLOUTDIV_SHIFT)
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#define CCS_PLLCTL_PLLOUTDIV1 (0)
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#define CCS_PLLCTL_PLLOUTDIV2 (1)
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#define CCS_PLLCTL_PLLOUTDIV4 (2)
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#define CCS_PLLCTL_PLLOUTDIV8 (3)
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#define CCS_PLLCTL_PLLINDIV_MASK (0x0F)
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#define CCS_PLLCTL_PLLINDIV_SHIFT (4)
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/** PLL Input Divisor */
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#define CCS_PLLCTL_PLLINDIV(div) (((div) & CCS_PLLCTL_PLLINDIV_MASK) << CCS_PLLCTL_PLLINDIV_SHIFT)
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#define CCS_PLLCTL_PLLFBDIV_MASK (0x3FFF)
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#define CCS_PLLCTL_PLLFBDIV_SHIFT (8)
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/** PLL Feedback Divisor */
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#define CCS_PLLCTL_PLLFBDIV(div) (((div) & CCS_PLLCTL_PLLFBDIV_MASK) << CCS_PLLCTL_PLLFBDIV_SHIFT)
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/** PLL Lock */
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#define CCS_PLLCTL_PLLLOCK BIT24
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/**@}*/
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/** @defgroup ccs_rosctrim Ring Oscillator Trim Control Register
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@{*/
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#define CCSROSCTRIM_MASK (0x7F)
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#define CCSROSCTRIM MMIO32(SCC_BASE + 0x08)
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/**@}*/
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@@ -136,6 +214,162 @@ typedef enum {
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CCS_DSR_DS_25MA = 0x07,
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} ccs_drive_strength_t;
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/**@}*/
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/**@}*/
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#endif /* INCLUDE_LIBOPENCM3_PAC55XX_CCS_H_ */
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BEGIN_DECLS
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/**
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* @defgroup ccs_api Clock Control System API
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* @ingroup peripheral_apis
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* @brief <b>PAC5xx CCS Driver</b>
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* @author @htmlonly © @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
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* @date March 7, 2020
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*
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* This library supports the CCS module in the PAC55xx SoC from Qorvo.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/**@{*/
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/**
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* Select the source for FRCLK.
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* @param[in] sel one of:
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* - /ref CCS_CTL_FRCLKMUXSEL_ROSC - 16MHz ring oscillator
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* - /ref CCS_CTL_FRCLKMUXSEL_CLKREF - trimmed 4MHz clock
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* - /ref CCS_CTL_FRCLKMUXSEL_EXTCLK
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*/
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void ccs_frclkmux_select(uint32_t sel);
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/** Enable the 16MHz Ring oscillator */
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void ccs_rosc_enable(void);
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/** Disable the 16MHz Ring oscillator */
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void ccs_rosc_disable(void);
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/** Select FRCLK for SCLK */
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void ccs_sclkmux_select_frclk(void);
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/** Select PLLCLK for SCLK */
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void ccs_sclkmux_select_pllclk(void);
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/** Enable Clock Fail Detection */
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void ccs_clkfail_enable(void);
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/** Disable Clock Fail Detection */
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void ccs_clkfail_disable(void);
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/** Select FRCLK for Clock Fail Detection */
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void ccs_clkfailmux_select_frclk(void);
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/** Select PLLCLK for Clock Fail Detection */
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void ccs_clkfailmux_select_pllclk(void);
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/** Enable the LDO */
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void ccs_ldo_enable(void);
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/** Disable the LDO */
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void ccs_ldo_disable(void);
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/** Enable the Peripheral Clock */
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void ccs_pclk_enable(void);
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/** Disable the Peripheral Clock */
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void ccs_pclk_disable(void);
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/** Enable the Auxiliary Clock */
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void ccs_aclk_enable(void);
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/** Disable the Auxiliary Clock */
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void ccs_aclk_disable(void);
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/** Enable the ADC Clock */
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void ccs_adcclk_enable(void);
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/** Disable the ADC Clock */
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void ccs_adcclk_disable(void);
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/** Enable SysTick clock gating in deep sleep mode */
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void ccs_stclk_sleep_enable(void);
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/** Disable SysTick clock gating in deep sleep mode */
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void ccs_stclk_sleep_disable(void);
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/**
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* Set the divisor for the Peripheral Clock.
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* @param[in] div PCLK Divisor: 1-8.
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*/
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void ccs_set_pclkdiv(uint32_t div);
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/**
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* Set the divisor for the Auxiliary Clock.
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* @param[in] div ACLK Divisor: 1-8.
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*/
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void ccs_set_aclkdiv(uint32_t div);
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/**
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* Set the divisor for the AHB Clock.
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* @param[in] div HCLK Divisor: 1-8.
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*/
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void ccs_set_hclkdiv(uint32_t div);
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/** Enable the PLL */
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void ccs_pll_enable(void);
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/** Disable the PLL */
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void ccs_pll_disable(void);
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/** Check if the PLL is locked.
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* @return true if locked.
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*/
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bool ccs_pll_locked(void);
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/** Enable the PLL bypass */
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void ccs_pll_bypass_enable(void);
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/** Disable the PLL bypass */
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void ccs_pll_bypass_disable(void);
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/**
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* Set the output divisor.
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* @param[in] div Output divisor, one of:
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* - /ref CCS_PLLCTL_PLLOUTDIV1
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* - /ref CCS_PLLCTL_PLLOUTDIV2
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* - /ref CCS_PLLCTL_PLLOUTDIV4
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* - /ref CCS_PLLCTL_PLLOUTDIV8
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*/
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void ccs_pll_set_outdiv(uint32_t div);
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/**
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* Set the PLL input divisor.
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* @param[in] div Input divisor, 1-15.
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*/
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void ccs_pll_set_indiv(uint32_t div);
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/**
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* Set the PLL feedback divisor.
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* @param[in] div Feedback divisor, 4-16383.
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*/
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void ccs_pll_set_fbdiv(uint32_t div);
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/**
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* Configure the CCS PLL, enable it, and wait for lock.
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* @param[in] indiv Input divisor, 1-15.
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* @param[in] fbdiv Feedback divisor, 4-16383.
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* @param[in] outdiv Output divisor, one of:
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* - /ref CCS_PLLCTL_PLLOUTDIV1
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* - /ref CCS_PLLCTL_PLLOUTDIV2
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* - /ref CCS_PLLCTL_PLLOUTDIV4
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* - /ref CCS_PLLCTL_PLLOUTDIV8
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*/
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void css_pll_config_enable(uint32_t indiv, uint32_t fbdiv, uint32_t outdiv);
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/**
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* Get the clock rate (in Hz) of the specified peripheral. This will pull the
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* proper sources out of the clock tree and calculate the clock for the
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* peripheral for return to the user, based on current settings.
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* @param[in] periph Peripheral base address to get the clock rate for.
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* @param[in] select Peripheral-controlled clock select value. Set to 0 when not applicable.
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* @return Clock rate in Hz for the specified peripheral. 0 if undefined or error.
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*/
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uint32_t ccs_get_peripheral_clk_freq(uint32_t periph, uint32_t select);
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/** Restores CCSCTL and CCSPLLCTL registers to default/safe values */
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void ccs_reset_clocks(void);
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/** CCS Clock Configuration structure. */
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struct ccs_clk_config {
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uint32_t frclk_source; /**< FRCLK source input selection */
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uint32_t extclk_frequency; /**< EXTCLK frequency, 0 if none. */
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uint32_t sclk_source; /**< SCLK source selection */
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uint32_t pll_indiv; /**< PLL Input Divider 1-15 */
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uint32_t pll_fbdiv; /**< PLL Feedback Divider 4-16383 */
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uint32_t pll_outdiv; /**< PLL Output Divider */
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uint32_t hclkdiv; /**< Divisor from SCLK to HCLK */
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uint32_t aclkdiv; /**< Divisor from SCLK to ACLK */
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uint32_t pclkdiv; /**< Divisor from HCLK to PCLK */
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uint32_t mem_wstate; /**< Number of Flash Read wait states */
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uint32_t mem_mclkdiv; /**< Divisor from HCLK to MCLK */
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bool mem_mclksel; /**< false: ROSCLK, true: HCLK/MCLK */
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bool mem_enable_cache; /**< false: disable cache, true: enable cache */
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};
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/**
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* Setup the PAC55xx clocks with the given struct.
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* @param[in] config CCS Clock configuration struct /ref ccs_clk_config
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*/
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void ccs_configure_clocks(const struct ccs_clk_config *config);
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/**@}*/
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END_DECLS
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#endif /* LIBOPENCM3_PAC55XX_CCS_H_ */
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163
include/libopencm3/pac55xx/memctl.h
Normal file
163
include/libopencm3/pac55xx/memctl.h
Normal file
@@ -0,0 +1,163 @@
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/**
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* @brief Memory Controller definitions for the Qorvo PAC55xx series of microcontrollers
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*
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* @addtogroup PAC55xx_memctl Memory Controller Defines
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* @ingroup PAC55xx_defines
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* @author Kevin Stefanik <kevin@allocor.tech>
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* LGPL License Terms @ref lgpl_license
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* @date 17 Mar 2020
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*
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* Definitions in this file come from the PAC55XX Family User Guide Rev 1.23
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* by Active-Semi dated November 19, 2019.
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2020 Kevin Stefanik <kevin@allocor.tech>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PAC55XX_MEMCTL_H_
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#define LIBOPENCM3_PAC55XX_MEMCTL_H_
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/pac55xx/memorymap.h>
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/**@{*/
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/** @defgroup memctl_reg Memory Controller Configuration Register
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@{*/
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/** Memory Controller Configuration Register */
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#define MEMCTL_MEMCTLR MMIO32(MEMCTL_BASE)
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#define MEMCTL_MEMCTLR_WSTATE_MASK (0xF)
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#define MEMCTL_MEMCTLR_WSTATE(ws) ((ws) & MEMCTL_MEMCTLR_WSTATE_MASK)
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#define MEMCTL_MEMCTLR_MCLKDIV_MASK (0xF)
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#define MEMCTL_MEMCTLR_MCLKDIV_SHIFT 4
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/* Supported MCLK divisors: 1-16 */
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#define MEMCTL_MEMCTLR_MCLKDIV(div) (((div-1) & MEMCTL_MEMCTLR_MCLKDIV_MASK) << MEMCTL_MEMCTLR_MCLKDIV_SHIFT)
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#define MEMCTL_MEMCTLR_WRITEWORDCNT_MASK (0x3)
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#define MEMCTL_MEMCTLR_WRITEWORDCNT_SHIFT 8
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#define MEMCTL_MEMCTLR_WRITEWORDCNT(cnt) (((cnt) & MEMCTL_MEMCTLR_WRITEWORDCNT_MASK) << MEMCTL_MEMCTLR_WRITEWORDCNT_SHIFT)
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#define MEMCTL_MEMCTLR_SEIE BIT16
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#define MEMCTL_MEMCTLR_DEIE BIT17
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#define MEMCTL_MEMCTLR_INVADDRIE BIT18
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#define MEMCTL_MEMCTLR_STBY BIT19
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#define MEMCTL_MEMCTLR_ECCDIS BIT20
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#define MEMCTL_MEMCTLR_CACHEDIS BIT21
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#define MEMCTL_MEMCTLR_MCLKSEL BIT22
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/**@}*/
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/** @defgroup memstatus_reg Memory Controller Status Register
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@{*/
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/** Memory Controller Status Register */
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#define MEMCTL_MEMSTATUS MMIO32(MEMCTL_BASE + 0x0004)
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#define MEMCTL_MEMSTATUS_WBUSY BIT0
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#define MEMCTL_MEMSTATUS_EBUSY BIT1
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_MASK (0x3)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_SHIFT 8
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT ((MEMCTL_MEMSTATUS >> MEMCTL_MEMSTATUS_WRITEWORDCNT_SHIFT) & MEMCTL_MEMSTATUS_WRITEWORDCNT_MASK)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_4BYTES (0)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_8BYTES (1)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_12BYTES (2)
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#define MEMCTL_MEMSTATUS_WRITEWORDCNT_16BYTES (3)
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#define MEMCTL_MEMSTATUS_SE BIT16
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#define MEMCTL_MEMSTATUS_DE BIT17
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#define MEMCTL_MEMSTATUS_INVADDR BIT18
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/**@}*/
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/** @defgroup flashlock_vals Flash Lock/Write Enable Register values
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@{*/
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/** Flash Lock Access Register */
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#define MEMCTL_FLASHLOCK MMIO32(MEMCTL_BASE + 0x0008)
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#define MEMCTL_FLASHLOCK_CLEAR (0)
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#define MEMCTL_FLASHLOCK_ALLOW_FLASH_WRITE (0x43DF140A)
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#define MEMCTL_FLASHLOCK_ALLOW_MEMCTL_WRITE (0xD513B490)
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#define MEMCTL_FLASHLOCK_ALLOW_INFO2_SWDFUSE (0x79B4F762)
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/**@}*/
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/** Flash Page Address Register */
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#define MEMCTL_FLASHPAGE MMIO32(MEMCTL_BASE + 0x000C)
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/** SWD Unlock Register */
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#define MEMCTL_SWDUNLOCK MMIO32(MEMCTL_BASE + 0x0010)
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/** @defgroup flasherase_vals Flash Erase Enable Register values
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@{*/
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/** Flash Erase Enable Register */
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#define MEMCTL_FLASHERASE MMIO32(MEMCTL_BASE + 0x0020)
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#define MEMCTL_FLASHERASE_PAGE_ERASE (0x8C799CA7)
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#define MEMCTL_FLASHERASE_MASS_PAGE_ERASE (0x09EE76C9)
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#define MEMCTL_FLASHERASE_INFO3_ERASE (0x1266FF45)
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/**@}*/
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/**@}*/
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BEGIN_DECLS
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/**
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* @defgroup memctl_api Memory Controller API
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* @ingroup peripheral_apis
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* @brief <b>PAC5xx MEMCTL Driver</b>
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* @author @htmlonly © @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
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* @date March 7, 2020
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*
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* This library supports the MEMCTL module in the PAC55xx SoC from Qorvo.
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*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*@{*/
|
||||
|
||||
/** Set the number of wait states for Flash reads.
|
||||
* @param[in] wstate Wait states: 0-15
|
||||
*/
|
||||
void memctl_flash_set_wstate(uint32_t wstate);
|
||||
/** Set the MCLK divisor.
|
||||
* @param[in] div HCLK to MCLK divisor: 1-16
|
||||
*/
|
||||
void memctl_flash_set_mclkdiv(uint32_t div);
|
||||
/** Set WRITEWORDCOUNT to 0 to reset the Flash write data buffer */
|
||||
void memctl_flash_reset_write_buffer(void);
|
||||
/** Enable Flash Standby Mode */
|
||||
void memctl_flash_standby_mode_enable(void);
|
||||
/** Disable Flash Standby Mode */
|
||||
void memctl_flash_standby_mode_disable(void);
|
||||
/** Enable Flash cache */
|
||||
void memctl_flash_cache_enable(void);
|
||||
/** Disable Flash cache */
|
||||
void memctl_flash_cache_disable(void);
|
||||
/** Select ROSCCLK as input to Flash Memory Controller */
|
||||
void memctl_flash_select_roscclk(void);
|
||||
/** Select MCLK as input to Flash Memory Controller */
|
||||
void memctl_flash_select_mclk(void);
|
||||
/** Enable SRAM ECC */
|
||||
void memctl_sram_ecc_enable(void);
|
||||
/** Disable SRAM ECC */
|
||||
void memctl_sram_ecc_disable(void);
|
||||
/** Enable SRAM ECC Single Bit Detection Interrupt */
|
||||
void memctl_sram_ecc_single_bit_interrupt_enable(void);
|
||||
/** Disable SRAM ECC Single Bit Detection Interrupt */
|
||||
void memctl_sram_ecc_single_bit_interrupt_disable(void);
|
||||
/** Enable SRAM ECC Dual Bit Detection Interrupt */
|
||||
void memctl_sram_ecc_dual_bit_interrupt_enable(void);
|
||||
/** Disable SRAM ECC Dual Bit Detection Interrupt */
|
||||
void memctl_sram_ecc_dual_bit_interrupt_disable(void);
|
||||
/** Enable Invalid Memory Access Interrupt */
|
||||
void memctl_invaddr_interrupt_enable(void);
|
||||
/** Disable Invalid Memory Access Interrupt */
|
||||
void memctl_invaddr_interrupt_disable(void);
|
||||
|
||||
/**@}*/
|
||||
|
||||
END_DECLS
|
||||
|
||||
#endif /* LIBOPENCM3_PAC55XX_MEMCTL_H_ */
|
||||
@@ -36,7 +36,9 @@ TGT_CFLAGS += $(STANDARD_FLAGS)
|
||||
ARFLAGS = rcs
|
||||
|
||||
OBJS += can.o
|
||||
OBJS += ccs.o
|
||||
OBJS += gpio.o
|
||||
OBJS += memctl.o
|
||||
|
||||
VPATH += ../cm3
|
||||
|
||||
|
||||
261
lib/pac55xx/ccs.c
Normal file
261
lib/pac55xx/ccs.c
Normal file
@@ -0,0 +1,261 @@
|
||||
/**
|
||||
* @brief <b>PAC55xxxx CCS Driver</b>
|
||||
* @author @htmlonly © @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
|
||||
* @date March 7, 2020
|
||||
*
|
||||
* This library supports the CCS module in the PAC55xx SoC from Qorvo.
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include <libopencm3/pac55xx/ccs.h>
|
||||
#include <libopencm3/pac55xx/memorymap.h>
|
||||
#include <libopencm3/pac55xx/memctl.h>
|
||||
#include <libopencm3/cm3/assert.h>
|
||||
|
||||
static volatile uint32_t ccs_extclk_frequency = 0;
|
||||
static volatile uint32_t ccs_frclk_frequency = CCS_ROSC_FREQ;
|
||||
static volatile uint32_t ccs_sclk_frequency = CCS_ROSC_FREQ;
|
||||
static volatile uint32_t ccs_pll_clk_frequency = 0;
|
||||
static volatile uint32_t ccs_hclk_frequency = CCS_ROSC_FREQ;
|
||||
static volatile uint32_t ccs_aclk_frequency = CCS_ROSC_FREQ;
|
||||
static volatile uint32_t ccs_pclk_frequency = CCS_ROSC_FREQ;
|
||||
|
||||
void ccs_frclkmux_select(uint32_t sel) {
|
||||
CCSCTL = (CCSCTL & ~CCS_CTL_FRCLKMUXSEL(CCS_CTL_FRCLKMUXSEL_MASK)) | CCS_CTL_FRCLKMUXSEL(sel);
|
||||
}
|
||||
void ccs_rosc_enable(void) {
|
||||
CCSCTL |= CCS_CTL_ROSCEN;
|
||||
}
|
||||
void ccs_rosc_disable(void) {
|
||||
CCSCTL &= ~CCS_CTL_ROSCEN;
|
||||
}
|
||||
void ccs_sclkmux_select_frclk(void) {
|
||||
CCSCTL &= ~CCS_CTL_SCLKMUXSEL;
|
||||
}
|
||||
void ccs_sclkmux_select_pllclk(void) {
|
||||
CCSCTL |= CCS_CTL_SCLKMUXSEL;
|
||||
}
|
||||
void ccs_clkfail_enable(void) {
|
||||
CCSCTL |= CCS_CTL_CLKFAILEN;
|
||||
}
|
||||
void ccs_clkfail_disable(void) {
|
||||
CCSCTL &= ~CCS_CTL_CLKFAILEN;
|
||||
}
|
||||
void ccs_clkfailmux_select_frclk(void) {
|
||||
CCSCTL &= ~CCS_CTL_CLKFAILMUXSEL;
|
||||
}
|
||||
void ccs_clkfailmux_select_pllclk(void) {
|
||||
CCSCTL |= CCS_CTL_CLKFAILMUXSEL;
|
||||
}
|
||||
void ccs_ldo_enable(void) {
|
||||
CCSCTL |= CCS_CTL_LDOEN;
|
||||
}
|
||||
void ccs_ldo_disable(void) {
|
||||
CCSCTL &= ~CCS_CTL_LDOEN;
|
||||
}
|
||||
void ccs_pclk_enable(void) {
|
||||
CCSCTL |= CCS_CTL_PCLKEN;
|
||||
}
|
||||
void ccs_pclk_disable(void) {
|
||||
CCSCTL &= ~CCS_CTL_PCLKEN;
|
||||
}
|
||||
void ccs_aclk_enable(void) {
|
||||
CCSCTL |= CCS_CTL_ACLKEN;
|
||||
}
|
||||
void ccs_aclk_disable(void) {
|
||||
CCSCTL &= ~CCS_CTL_ACLKEN;
|
||||
}
|
||||
void ccs_adcclk_enable(void) {
|
||||
CCSCTL |= CCS_CTL_ADCCLKEN;
|
||||
}
|
||||
void ccs_adcclk_disable(void) {
|
||||
CCSCTL &= ~CCS_CTL_ADCCLKEN;
|
||||
}
|
||||
void ccs_stclk_sleep_enable(void) {
|
||||
CCSCTL |= CCS_CTL_STCLKSLPEN;
|
||||
}
|
||||
void ccs_stclk_sleep_disable(void) {
|
||||
CCSCTL &= ~CCS_CTL_STCLKSLPEN;
|
||||
}
|
||||
void ccs_set_pclkdiv(uint32_t div) {
|
||||
CCSCTL = (CCSCTL & ~CCS_CTL_PCLKDIV(8)) | CCS_CTL_PCLKDIV(div);
|
||||
}
|
||||
void ccs_set_aclkdiv(uint32_t div) {
|
||||
CCSCTL = (CCSCTL & ~CCS_CTL_ACLKDIV(8)) | CCS_CTL_ACLKDIV(div);
|
||||
}
|
||||
void ccs_set_hclkdiv(uint32_t div) {
|
||||
CCSCTL = (CCSCTL & ~CCS_CTL_HCLKDIV(8)) | CCS_CTL_HCLKDIV(div);
|
||||
}
|
||||
void ccs_pll_enable(void) {
|
||||
CCSPLLCTL |= CCS_PLLCTL_PLLEN;
|
||||
}
|
||||
void ccs_pll_disable(void) {
|
||||
CCSPLLCTL &= ~CCS_PLLCTL_PLLEN;
|
||||
}
|
||||
bool ccs_pll_locked(void) {
|
||||
return (CCSPLLCTL & CCS_PLLCTL_PLLLOCK) == CCS_PLLCTL_PLLLOCK;
|
||||
}
|
||||
void ccs_pll_bypass_enable(void) {
|
||||
CCSPLLCTL |= CCS_PLLCTL_PLLBP;
|
||||
}
|
||||
void ccs_pll_bypass_disable(void) {
|
||||
CCSPLLCTL &= ~CCS_PLLCTL_PLLBP;
|
||||
}
|
||||
void ccs_pll_set_outdiv(uint32_t div) {
|
||||
CCSPLLCTL = (CCSPLLCTL & ~CCS_PLLCTL_PLLOUTDIV(CCS_PLLCTL_PLLOUTDIV_MASK)) | CCS_PLLCTL_PLLOUTDIV(div);
|
||||
}
|
||||
void ccs_pll_set_indiv(uint32_t div) {
|
||||
if (div <= 15 && div >= 1) {
|
||||
CCSPLLCTL = (CCSPLLCTL & ~CCS_PLLCTL_PLLINDIV(CCS_PLLCTL_PLLINDIV_MASK)) | CCS_PLLCTL_PLLINDIV(div);
|
||||
} else {
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
}
|
||||
void ccs_pll_set_fbdiv(uint32_t div) {
|
||||
if (div <= 16383 && div >= 4) {
|
||||
CCSPLLCTL = (CCSPLLCTL & ~CCS_PLLCTL_PLLFBDIV(CCS_PLLCTL_PLLFBDIV_MASK)) | CCS_PLLCTL_PLLFBDIV(div);
|
||||
} else {
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
}
|
||||
void css_pll_config_enable(uint32_t indiv, uint32_t fbdiv, uint32_t outdiv) {
|
||||
ccs_pll_disable();
|
||||
ccs_pll_set_fbdiv(fbdiv);
|
||||
ccs_pll_set_outdiv(outdiv);
|
||||
ccs_pll_set_indiv(indiv);
|
||||
ccs_pll_enable();
|
||||
while (!ccs_pll_locked()) ; /* Wait for PLL lock ~500us */
|
||||
}
|
||||
uint32_t ccs_get_peripheral_clk_freq(uint32_t periph, uint32_t select) {
|
||||
switch (periph) {
|
||||
case ADC_BASE:
|
||||
return ccs_sclk_frequency;
|
||||
case I2C_BASE: /* fall through */
|
||||
case USARTA_BASE: /* fall through */
|
||||
case USARTB_BASE: /* fall through */
|
||||
case USARTC_BASE: /* fall through */
|
||||
case USARTD_BASE: /* fall through */
|
||||
case CAN_BASE: /* fall through */
|
||||
case GPTIMERA_BASE: /* fall through */
|
||||
case GPTIMERB_BASE:
|
||||
return ccs_pclk_frequency;
|
||||
case TIMERA_BASE: /* fall through */
|
||||
case TIMERB_BASE: /* fall through */
|
||||
case TIMERC_BASE: /* fall through */
|
||||
case TIMERD_BASE:
|
||||
return (select == 0) ? ccs_pclk_frequency : ccs_aclk_frequency;
|
||||
case MEMCTL_BASE:
|
||||
return (select == 0) ? CCS_ROSC_FREQ : ccs_hclk_frequency;
|
||||
case WWDT_BASE:
|
||||
return (select == 0) ? ccs_frclk_frequency : CCS_ROSC_FREQ;
|
||||
case RTC_BASE:
|
||||
return ccs_frclk_frequency;
|
||||
case CRC_BASE: /* fall through */
|
||||
case SYS_TICK_BASE:
|
||||
return ccs_hclk_frequency;
|
||||
default:
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
}
|
||||
|
||||
void ccs_reset_clocks(void) {
|
||||
CCSCTL = CCS_CTL_LDOEN | CCS_CTL_ROSCEN |
|
||||
CCS_CTL_PCLKEN | CCS_CTL_ACLKEN |
|
||||
CCS_CTL_ADCCLKEN | CCS_CTL_STCLKSLPEN;
|
||||
CCSPLLCTL = 0;
|
||||
}
|
||||
|
||||
void ccs_configure_clocks(const struct ccs_clk_config *config) {
|
||||
MEMCTL_FLASHLOCK = MEMCTL_FLASHLOCK_ALLOW_MEMCTL_WRITE;
|
||||
|
||||
ccs_reset_clocks(); /* set safe defaults */
|
||||
ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_ROSC);
|
||||
ccs_sclkmux_select_frclk();
|
||||
memctl_flash_select_roscclk();
|
||||
|
||||
if (config->mem_enable_cache) {
|
||||
memctl_flash_cache_enable();
|
||||
} else {
|
||||
memctl_flash_cache_disable();
|
||||
}
|
||||
|
||||
ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_CLKREF); /* switch frclk to 4MHz CLKREF */
|
||||
|
||||
switch (config->frclk_source) {
|
||||
case CCS_CTL_FRCLKMUXSEL_ROSC:
|
||||
ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_ROSC);
|
||||
ccs_frclk_frequency = CCS_ROSC_FREQ;
|
||||
break;
|
||||
case CCS_CTL_FRCLKMUXSEL_CLKREF:
|
||||
ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_CLKREF);
|
||||
ccs_frclk_frequency = CCS_CLKREF_FREQ;
|
||||
break;
|
||||
case CCS_CTL_FRCLKMUXSEL_EXTCLK:
|
||||
if (config->extclk_frequency > CCS_EXTCLK_MAX_FREQ
|
||||
|| config->extclk_frequency == 0) {
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
ccs_frclkmux_select(CCS_CTL_FRCLKMUXSEL_EXTCLK);
|
||||
ccs_frclk_frequency = ccs_extclk_frequency = config->extclk_frequency;
|
||||
break;
|
||||
default:
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
|
||||
if (config->sclk_source == CCS_CTL_SCLKMUXSEL_FRCLK) {
|
||||
ccs_set_hclkdiv(config->hclkdiv);
|
||||
ccs_set_aclkdiv(config->aclkdiv);
|
||||
memctl_flash_set_wstate(config->mem_wstate);
|
||||
ccs_sclkmux_select_frclk();
|
||||
memctl_flash_set_mclkdiv(config->mem_mclkdiv);
|
||||
if (config->mem_mclksel == false) {
|
||||
memctl_flash_select_roscclk();
|
||||
} else {
|
||||
memctl_flash_select_mclk();
|
||||
}
|
||||
ccs_sclk_frequency = ccs_frclk_frequency;
|
||||
} else if (config->sclk_source == CCS_CTL_SCLKMUXSEL_PLLCLK) {
|
||||
css_pll_config_enable(config->pll_indiv, config->pll_fbdiv, config->pll_outdiv);
|
||||
ccs_set_hclkdiv(config->hclkdiv);
|
||||
ccs_set_aclkdiv(config->aclkdiv);
|
||||
memctl_flash_set_wstate(config->mem_wstate);
|
||||
ccs_sclkmux_select_pllclk();
|
||||
memctl_flash_set_mclkdiv(config->mem_mclkdiv);
|
||||
if (config->mem_mclksel == false) {
|
||||
memctl_flash_select_roscclk();
|
||||
} else {
|
||||
memctl_flash_select_mclk();
|
||||
}
|
||||
ccs_pll_clk_frequency = ((ccs_frclk_frequency * config->pll_fbdiv) / config->pll_indiv) >> config->pll_outdiv;
|
||||
ccs_sclk_frequency = ccs_pll_clk_frequency;
|
||||
} else {
|
||||
cm3_assert_not_reached();
|
||||
}
|
||||
ccs_set_pclkdiv(config->pclkdiv);
|
||||
ccs_pclk_enable();
|
||||
ccs_aclk_enable();
|
||||
ccs_adcclk_enable();
|
||||
ccs_stclk_sleep_disable();
|
||||
|
||||
ccs_hclk_frequency = ccs_sclk_frequency / config->hclkdiv;
|
||||
ccs_aclk_frequency = ccs_sclk_frequency / config->aclkdiv;
|
||||
ccs_pclk_frequency = ccs_hclk_frequency / config->pclkdiv;
|
||||
|
||||
MEMCTL_FLASHLOCK = MEMCTL_FLASHLOCK_CLEAR;
|
||||
}
|
||||
78
lib/pac55xx/memctl.c
Normal file
78
lib/pac55xx/memctl.c
Normal file
@@ -0,0 +1,78 @@
|
||||
/**
|
||||
* @brief <b>PAC55xxxx Memory Controller Driver</b>
|
||||
* @author @htmlonly © @endhtmlonly 2020 Kevin Stefanik <kevin@allocor.tech>
|
||||
* @date April 1, 2020
|
||||
*
|
||||
* This library supports the Memory Controller in the PAC55xx SoC from Qorvo.
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#include <libopencm3/pac55xx/memctl.h>
|
||||
|
||||
void memctl_flash_set_wstate(uint32_t wstate) {
|
||||
MEMCTL_MEMCTLR = (MEMCTL_MEMCTLR & ~MEMCTL_MEMCTLR_WSTATE(MEMCTL_MEMCTLR_WSTATE_MASK)) | MEMCTL_MEMCTLR_WSTATE(wstate);
|
||||
}
|
||||
void memctl_flash_set_mclkdiv(uint32_t div) {
|
||||
MEMCTL_MEMCTLR = (MEMCTL_MEMCTLR & ~MEMCTL_MEMCTLR_MCLKDIV(16)) | MEMCTL_MEMCTLR_MCLKDIV(div);
|
||||
}
|
||||
void memctl_flash_reset_write_buffer(void) {
|
||||
MEMCTL_MEMCTLR = (MEMCTL_MEMCTLR & ~MEMCTL_MEMCTLR_WRITEWORDCNT(MEMCTL_MEMCTLR_WRITEWORDCNT_MASK));
|
||||
}
|
||||
void memctl_flash_standby_mode_enable(void) {
|
||||
MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_STBY;
|
||||
}
|
||||
void memctl_flash_standby_mode_disable(void) {
|
||||
MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_STBY;
|
||||
}
|
||||
void memctl_flash_cache_enable(void) {
|
||||
MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_CACHEDIS;
|
||||
}
|
||||
void memctl_flash_cache_disable(void) {
|
||||
MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_CACHEDIS;
|
||||
}
|
||||
void memctl_flash_select_roscclk(void) {
|
||||
MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_MCLKSEL;
|
||||
}
|
||||
void memctl_flash_select_mclk(void) {
|
||||
MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_MCLKSEL;
|
||||
}
|
||||
void memctl_sram_ecc_enable(void) {
|
||||
MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_ECCDIS;
|
||||
}
|
||||
void memctl_sram_ecc_disable(void) {
|
||||
MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_ECCDIS;
|
||||
}
|
||||
void memctl_sram_ecc_single_bit_interrupt_enable(void) {
|
||||
MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_SEIE;
|
||||
}
|
||||
void memctl_sram_ecc_single_bit_interrupt_disable(void) {
|
||||
MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_SEIE;
|
||||
}
|
||||
void memctl_sram_ecc_dual_bit_interrupt_enable(void) {
|
||||
MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_DEIE;
|
||||
}
|
||||
void memctl_sram_ecc_dual_bit_interrupt_disable(void) {
|
||||
MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_DEIE;
|
||||
}
|
||||
void memctl_invaddr_interrupt_enable(void) {
|
||||
MEMCTL_MEMCTLR |= MEMCTL_MEMCTLR_INVADDRIE;
|
||||
}
|
||||
void memctl_invaddr_interrupt_disable(void) {
|
||||
MEMCTL_MEMCTLR &= ~MEMCTL_MEMCTLR_INVADDRIE;
|
||||
}
|
||||
Reference in New Issue
Block a user