pac55xx: implemented CAN module interface for qorvo pac55xx.
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Kevin Stefanik
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Karl Palsson
Karl Palsson
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cb83273416
commit
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307
include/libopencm3/pac55xx/can.h
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307
include/libopencm3/pac55xx/can.h
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/**
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* @brief CAN definitions for the Qorvo PAC55xx series of microcontrollers.
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*
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* @addtogroup PAC55xx_can CAN
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* @ingroup PAC55xx_defines
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* @author Kevin Stefanik <kevin@allocor.tech>
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* LGPL License Terms @ref lgpl_license
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* @date February 13, 2020
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*
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* Definitions in this file come from the PAC55XX Family User Guide Rev 1.23
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* by Active-Semi dated November 19, 2019.
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*
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* Note: all memory-mapped writes must be performed using 32-bit registers.
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* Any 8-bit memory-mapped registers below may only be used to read.
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2020 Kevin Stefanik <kevin@allocor.tech>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_PAC55XX_CAN_H_
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#define LIBOPENCM3_PAC55XX_CAN_H_
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#include <libopencm3/pac55xx/memorymap.h>
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#include <libopencm3/cm3/common.h>
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/**@{*/
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/**
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* @defgroup can_isr_sr_cmr_mr CAN ISR/SR/CMR/MR Registers
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* @{*/
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/** This is the 32-bit memory mapped read/write accessor for:
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* - ISR - bits 31:24 - Interrupt Status/ACK Register RW, default 00h
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* - SR - bits 23:16 - Status Register RO, default 00h
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* - CMR - bits 15:8 - Command RW, default 00h
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* - MR - bits 7:0 - Mode RW, default 04h
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* When writing, be sure to use CAN_ISR_SR_CMR_MR_SET and CAN_ISR_SR_CMR_MR_CLEAR
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* so as to avoid inadvertently Acknowledging an ISR bit. Writing '1' to one
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* of the ISR bits when it is triggered/set will ACK/clear the bit.
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*/
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#define CAN_ISR_SR_CMR_MR(can_base) MMIO32((can_base) + 0x0000)
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#define CAN_ISR_SR_CMR_MR_SET(can_base, bits) (CAN_ISR_SR_CMR_MR(can_base) = \
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(CAN_ISR_SR_CMR_MR(can_base) & 0x00FFFFFF) | (bits))
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#define CAN_ISR_SR_CMR_MR_CLEAR(can_base, bits) (CAN_ISR_SR_CMR_MR(can_base) = \
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(CAN_ISR_SR_CMR_MR(can_base) & 0x00FFFFFF) & ~(bits))
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/**@}*/
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/**
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* @defgroup can_btr01_rmc_imr CAN BTR1/BTR0/RMC/IMR Registers
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* @{*/
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/** This is the 32-bit memory mapped read/write accessor for:
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* - BTR1 - bits 31:24 - Bus Timing 1 Register RW, default 00h
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* - BTR0 - bits 23:16 - Bus Timing 0 Register RW, default 00h
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* - RMC - bits 15:8 - Receive Message Counter RO, default 00h
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* - IMR - bits 7:0 - Interrupt Mask Register RW, default 00h
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*/
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#define CAN_BTR1_BTR0_RMC_IMR(can_base) MMIO32((can_base) + 0x0004)
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/**@}*/
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/** CAN Transmit Buffer Register RW, default 00000000h */
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#define CAN_TXBUF(can_base) MMIO32((can_base) + 0x0008)
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/** CAN Receive Buffer Register RO, default 00000000h */
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#define CAN_RXBUF(can_base) MMIO32((can_base) + 0x000C)
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/** CAN Acceptance Code Register RW, default 00000000h */
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#define CAN_ACR(can_base) MMIO32((can_base) + 0x0010)
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/** CAN Acceptance Mask Register RW, default 00000000h */
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#define CAN_AMR(can_base) MMIO32((can_base) + 0x0014)
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/**
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* @defgroup can_alc_txrxerr_ecc CAN ALC/TXERR/RXERR/ECC Registers
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* @{*/
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#define CAN_ALC_TXERR_RXERR_ECC(can_base) MMIO32((can_base) + 0x0018)
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/** CAN Error Code Capture Register RO, default 00h */
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#define CAN_ECC(can_base) (CAN_ALC_TXERR_RXERR_ECC(can_base) & 0xFF)
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/** CAN RX Error Counter Register RO, default 00h */
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#define CAN_RXERR(can_base) ((CAN_ALC_TXERR_RXERR_ECC(can_base) >> 8) & 0xFF)
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/** CAN TX Error Counter Register RO, default 00h */
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#define CAN_TXERR(can_base) ((CAN_ALC_TXERR_RXERR_ECC(can_base) >> 16) & 0xFF)
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/** CAN Arbitration Lost Code Capture Register RO, default 00h */
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#define CAN_ALC(can_base) ((CAN_ALC_TXERR_RXERR_ECC(can_base) >> 24) & 0xFF)
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/**@}*/
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/** CAN Mode Register bit definitions. This register controls high level modes of the CAN peripheral.
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* @defgroup can_mr_bits CAN Mode Register
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* @{*/
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/** AFM: Acceptance Filter Mode */
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#define CAN_MR_AFM BIT0
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/** LOM: Listen only mode */
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#define CAN_MR_LOM BIT1
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/** RM: Reset Mode */
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#define CAN_MR_RM BIT2
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/**@}*/
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/** CAN Command Register. This register commands the CAN peripheral to either transmit or abort.
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* @defgroup can_cmr_bits CAN Command Register
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* @{*/
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/** AT: Abort transmission */
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#define CAN_CMR_AT BIT9
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/** TR: Transmit Request */
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#define CAN_CMR_TR BIT10
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/**@}*/
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/** CAN Status Register. This register provides read-only status of the CAN peripheral.
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* @defgroup can_sr_bits CAN Status Register
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* @{*/
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/** BS: Bus Off Status */
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#define CAN_SR_BS BIT16
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/** ES: Error Status */
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#define CAN_SR_ES BIT17
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/** TS: Transmit Status */
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#define CAN_SR_TS BIT18
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/** RS: Receive Status */
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#define CAN_SR_RS BIT19
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/** TBS: Transmit Buffer Status */
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#define CAN_SR_TBS BIT21
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/** DSO: Data Overrun Status */
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#define CAN_SR_DSO BIT22
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/** RBS: Receive Buffer Status */
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#define CAN_SR_RBS BIT23
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/**@}*/
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/** CAN Interrupt Status Register bit definitions.
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* - 1: interrupt triggered
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* - 0: no interrupt
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* - Writing a 1 to a triggered interrupt clears the bit.
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* @defgroup can_isr_bits CAN Interrupt Status Register
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* @{*/
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/** DOI: Data Overflow Interrupt */
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#define CAN_ISR_DOI BIT24
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/** BEI: Bus Error Interrupt */
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#define CAN_ISR_BEI BIT25
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/** TI: Transmit Interrupt */
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#define CAN_ISR_TI BIT26
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/** RI: Receive Interrupt */
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#define CAN_ISR_RI BIT27
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/** EPI: Error Passive Interrupt */
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#define CAN_ISR_EPI BIT28
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/** EWI: Error Warning Interrupt */
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#define CAN_ISR_EWI BIT29
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/** ALI: Arbitration Lost Interrupt */
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#define CAN_ISR_ALI BIT30
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/** This is a helper to acknowledge an ISR */
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#define CAN_ISR_ACKNOWLEDGE(can_base, isr) CAN_ISR_SR_CMR_MR_SET(can_base, ((isr) & 0x7F000000))
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/**@}*/
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/** CAN Interrupt Mask Register bit definitions.
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* 0: disables/masks interrupt
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* 1: enables interrupt
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* @defgroup can_imr_bits CAN Mask Register
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* @{*/
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/** DOIM: DOI Interrupt Mask */
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#define CAN_IMR_DOIM BIT0
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/** BEIM: BEI Interrupt Mask */
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#define CAN_IMR_BEIM BIT1
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/** TIM: TI Interrupt Mask */
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#define CAN_IMR_TIM BIT2
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/** RIM: RI Interrupt Mask */
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#define CAN_IMR_RIM BIT3
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/** EPIM: EPI Interrupt Mask */
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#define CAN_IMR_EPIM BIT4
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/** EWIM: EWI Interrupt Mask */
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#define CAN_IMR_EWIM BIT5
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/** ALIM: ALI Interrupt Mask */
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#define CAN_IMR_ALIM BIT6
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/**@}*/
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/** CAN Receive Message Counter Register bit definitions.
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* @defgroup can_rmc_bits CAN Receive Message Counter Register.
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* @{*/
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#define CAN_RMC(can_base) ((CAN_BTR1_BTR0_RMC_IMR(can_base) >> 8) & 0x1F)
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/**@}*/
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/** CAN Bus Timing 0 Register bit definitions.
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* @defgroup can_btr0_bits CAN Bus Timing 0 Register.
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* @{*/
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#define CAN_BTR0_BRP_MASK (0x3F)
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#define CAN_BTR0_BRP_SHIFT 16
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#define CAN_BTR0_BRP(val) (((val) & CAN_BTR0_BRP_MASK) << CAN_BTR0_BRP_SHIFT)
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#define CAN_BTR0_SJW_MASK (0x03)
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#define CAN_BTR0_SJW_SHIFT 22
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#define CAN_BTR0_SJW(val) (((val) & CAN_BTR0_SJW_MASK) << CAN_BTR0_SJW_SHIFT)
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/**@}*/
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/** CAN Bus Timing 1 Register bit definitions.
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* @defgroup can_btr1_bits CAN Bus Timing 1 Register
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* @{*/
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#define CAN_BTR1_TSEG1_MASK (0x0F)
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#define CAN_BTR1_TSEG1_SHIFT 24
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#define CAN_BTR1_TSEG1(val) (((val) & CAN_BTR1_TSEG1_MASK) << CAN_BTR1_TSEG1_SHIFT)
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#define CAN_BTR1_TSEG2_MASK (0x07)
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#define CAN_BTR1_TSEG2_SHIFT 28
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#define CAN_BTR1_TSEG2(val) (((val) & CAN_BTR1_TSEG2_MASK) << CAN_BTR1_TSEG2_SHIFT)
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#define CAN_BTR1_SAM BIT31
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/**@}*/
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/** CAN Error Code Capture Register bit definitions.
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* @defgroup can_ecc_bits CAN Error Code Capture Register
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* @{*/
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/** BER: Bit error ocurred */
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#define CAN_ECC_BER BIT0
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/** STFER: Stuff error occurred */
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#define CAN_ECC_STFER BIT1
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/** CRCER: CRC error occurred */
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#define CAN_ECC_CRCER BIT2
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/** FRMER: Form error occurred */
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#define CAN_ECC_FRMER BIT3
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/** ACKER: ACK error occurred */
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#define CAN_ECC_ACKER BIT4
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/** EDIR: Direction of transfer 0:TX, 1:RX */
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#define CAN_ECC_EDIR BIT5
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/** TXWRN: set when CAN_TXERR >= 96 */
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#define CAN_ECC_TXWRN BIT6
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/** RXWRN: set when CAN_RXERR >= 96 */
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#define CAN_ECC_RXWRN BIT7
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/**@}*/
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/** CAN Acceptance Code/Mask Register. This is used for filtering messages.
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* Mask value of 1 ignores the bit. Mask value of 0 checks the bit.
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* @defgroup can_acr_bits CAN Acceptance Code Register
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* @{*/
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#define CAN_ACR_DUAL_DB_UPPER 0x000F0000U /* 19:16 */
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#define CAN_ACR_DUAL_DB_LOWER 0x0000000FU /* 3:0 */
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#define CAN_ACR_DUAL_ID1 0xFFE00000U /* 31:21 */
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#define CAN_ACR_DUAL_ID2 0x0000FFE0U /* 15:5 */
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#define CAN_ACR_DUAL_RTR1 0x00100000U /* 20 */
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#define CAN_ACR_DUAL_RTR2 0x00000010U /* 4 */
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#define CAN_ACR_SINGLE_STD_ID 0xFFE00000U /* 31:21 */
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#define CAN_ACR_SINGLE_STD_RTR 0x00100000U /* 20 */
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#define CAN_ACR_SINGLE_STD_DB1 0x0000FF00U /* 15:8 */
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#define CAN_ACR_SINGLE_STD_DB2 0x000000FFU /* 7:0 */
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#define CAN_ACR_SINGLE_EXT_ID 0xFFFFFFF8U /* 31:3 */
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#define CAN_ACR_SINGLE_EXT_RTR 0x00000004U /* 2 */
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/**@}*/
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/**
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* @defgroup can_bit_masks CAN Miscellaneous Bit Masks
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* @{*/
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#define CAN_BITS_2_0 (0x07)
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#define CAN_BITS_3_0 (0x0F)
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#define CAN_BITS_4_0 (0x1F)
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#define CAN_BITS_7_3 (0xF8)
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#define CAN_BITS_10_3 (0x07F8)
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#define CAN_BITS_12_5 (0x00001FE0U)
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#define CAN_BITS_20_13 (0x001FE000U)
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#define CAN_BITS_28_21 (0x1FE00000U)
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#define CAN_BITS_15_8 (0x0000FF00U)
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#define CAN_BITS_23_16 (0x00FF0000U)
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#define CAN_BITS_31_24 (0xFF000000U)
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#define CAN_BITS_23_21 (0x00E00000U)
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/**@}*/
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/**@}*/
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BEGIN_DECLS
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/** CAN Application Programming Interface.
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* @addtogroup can_api CAN Peripheral API
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* @ingroup peripheral_apis
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@{*/
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void can_enable(uint32_t canport);
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void can_disable(uint32_t canport);
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void can_init(uint32_t canport, bool listen_only, uint32_t sjw,
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uint32_t tseg1, uint32_t tseg2,
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bool sam3, uint32_t brp);
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void can_filter_clear(uint32_t canport);
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void can_filter_dual(uint32_t canport, uint32_t id1, uint32_t id1_mask,
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uint32_t id2, uint32_t id2_mask,
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uint8_t db, uint8_t db_mask);
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void can_filter_single_std(uint32_t canport, uint32_t id, uint32_t id_mask,
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uint8_t db1, uint8_t db1_mask,
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uint8_t db2, uint8_t db2_mask);
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void can_filter_single_std_rtr(uint32_t canport, uint32_t id, uint32_t id_mask,
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uint8_t db1, uint8_t db1_mask,
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uint8_t db2, uint8_t db2_mask);
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void can_filter_single_ext(uint32_t canport, uint32_t id, uint32_t id_mask);
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void can_filter_single_ext_rtr(uint32_t canport, uint32_t id, uint32_t id_mask);
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void can_enable_irq(uint32_t canport, uint8_t imr);
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void can_disable_irq(uint32_t canport, uint8_t imr);
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bool can_transmit_std(uint32_t canport, uint32_t id, bool rtr, uint8_t length,
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const uint8_t *data);
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bool can_transmit_ext(uint32_t canport, uint32_t id, bool rtr, uint8_t length,
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const uint8_t *data);
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void can_abort_transmit(uint32_t canport);
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void can_receive(uint32_t canport, uint32_t *id, bool *ext, bool *rtr, uint8_t *length,
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uint8_t *data);
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/**@}*/
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END_DECLS
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#endif /* LIBOPENCM3_PAC55XX_CAN_H_ */
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