EMTime/libopencm3
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

stm32: f247: flash: use common code.

Browse Source 
This shows what is _actually_ different for f7.  A couple of option
bits, and a renaming of bit 7 of the status register, from Program
Sequence Error to Erase Sequence Error.

We keep the separate implementation of wait_for_last_operation, to meet
the "suggestions" of the reference manual to insert a DSB instruction.

Keeping the renamed bit/functions also requires us to keep separate
implementations of the flag clearing functions
This commit is contained in:
Karl Palsson
2018-07-24 22:30:07 +00:00
parent 46d4103c1d
commit 231f21296f
9 changed files with 84 additions and 387 deletions
Download Patch File Download Diff File Expand all files Collapse all files

89
include/libopencm3/stm32/f7/flash.h
View File

@@ -34,22 +34,13 @@
#include <libopencm3/stm32/common/flash_common_all.h>
#include <libopencm3/stm32/common/flash_common_f.h>
/*
* For details see:
* PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming
* September 2011, Doc ID 018520 Rev 1
* https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf
*/
#include <libopencm3/stm32/common/flash_common_f24.h>
/*
* Differences between F7 and F4:
* 1. icache and dcache are now combined into a unified ART cache. The CPU has
* its own d/i-caches, but those are unrelated to this. They are on the
* AXIM bus.
* 2. There's an OPTCR1 is now used for boot addresses. Write protect bits
* are in OPTCR. Why does F4 have 2 copies of nWRP?
* 3. Latency field in FLASH_ACR is now 4 bits. Some CPU frequencies supported
* by F7 require more than 7 wait states.
* 4. FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR (
* erase sequence error).
* 6. There are now two watchdogs - IWDG (independent watchdog) and WWDG (
@@ -57,66 +48,18 @@
*/
/**@{*/
/* --- FLASH registers ----------------------------------------------------- */
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
#define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
/* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEYR_KEY1 0x45670123UL
#define FLASH_KEYR_KEY2 0xcdef89abUL
#define FLASH_OPTKEYR_KEY1 0x08192a3bUL
#define FLASH_OPTKEYR_KEY2 0x4c5d6e7fUL
/* --- FLASH_ACR values ---------------------------------------------------- */
/** @addtogroup flash_acr_values FLASH_ACR_VALUES
* @ingroup flash_registers
@{*/
#define FLASH_ACR_ARTRST (1 << 11)
#define FLASH_ACR_ARTEN (1 << 9)
#define FLASH_ACR_PRFTEN (1 << 8)
/*@}*/
#define FLASH_ACR_LATENCY_SHIFT 0
#define FLASH_ACR_LATENCY_MASK 0x0f
/* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_SR_BSY (1 << 16)
#define FLASH_SR_ERSERR (1 << 7)
#define FLASH_SR_PGPERR (1 << 6)
#define FLASH_SR_PGAERR (1 << 5)
#define FLASH_SR_WRPERR (1 << 4)
#define FLASH_SR_OPERR (1 << 1)
#define FLASH_SR_EOP (1 << 0)
/* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_CR_LOCK (1 << 31)
#define FLASH_CR_ERRIE (1 << 25)
#define FLASH_CR_EOPIE (1 << 24)
#define FLASH_CR_STRT (1 << 16)
#define FLASH_CR_PROGRAM_MASK 0x3
#define FLASH_CR_PROGRAM_SHIFT 8
/** @defgroup flash_cr_program_width Flash programming width
@ingroup flash_group
@{*/
#define FLASH_CR_PROGRAM_X8 0
#define FLASH_CR_PROGRAM_X16 1
#define FLASH_CR_PROGRAM_X32 2
#define FLASH_CR_PROGRAM_X64 3
/**@}*/
#define FLASH_CR_SNB_SHIFT 3
#define FLASH_CR_SNB_MASK 0x1f
#define FLASH_CR_MER (1 << 2)
#define FLASH_CR_SER (1 << 1)
#define FLASH_CR_PG (1 << 0)
/* --- FLASH_OPTCR values -------------------------------------------------- */
@@ -129,18 +72,9 @@
#define FLASH_OPTCR_RDP_SHIFT 8
#define FLASH_OPTCR_RDP_MASK 0xff
#define FLASH_OPTCR_NRST_STDBY (1 << 7)
#define FLASH_OPTCR_NRST_STOP (1 << 6)
#define FLASH_OPTCR_IWDG_SW (1 << 5)
#define FLASH_OPTCR_WWDG_SW (1 << 4)
#define FLASH_OPTCR_BOR_LEV_MASK 3
#define FLASH_OPTCR_BOR_LEV_SHIFT 2
#define FLASH_OPTCR_BOR_LEV_3 0x00
#define FLASH_OPTCR_BOR_LEV_2 0x01
#define FLASH_OPTCR_BOR_LEV_1 0x02
#define FLASH_OPTCR_BOR_OFF 0x03
#define FLASH_OPTCR_OPTSTRT (1 << 1)
#define FLASH_OPTCR_OPTLOCK (1 << 0)
@@ -154,23 +88,10 @@
BEGIN_DECLS
void flash_clear_pgperr_flag(void);
void flash_lock_option_bytes(void);
void flash_clear_erserr_flag(void);
void flash_clear_wrperr_flag(void);
void flash_clear_pgaerr_flag(void);
void flash_art_enable(void);
void flash_art_disable(void);
void flash_art_reset(void);
void flash_erase_all_sectors(uint32_t program_size);
void flash_erase_sector(uint8_t sector, uint32_t program_size);
void flash_program_double_word(uint32_t address, uint64_t data);
void flash_program_word(uint32_t address, uint32_t data);
void flash_program_half_word(uint32_t address, uint16_t data);
void flash_program_byte(uint32_t address, uint8_t data);
void flash_program(uint32_t address, uint8_t *data, uint32_t len);
void flash_program_option_bytes(uint32_t data);
END_DECLS
/**@}*/