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[Style] Fixed all style errors in the efm32.

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This commit is contained in:
Piotr Esden-Tempski
2015-12-13 23:03:49 +01:00
parent 77354cb371
commit 1f6fd11dd9
24 changed files with 2293 additions and 2121 deletions
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3
lib/efm32/lg/adc.c
View File

@@ -87,7 +87,8 @@ void adc_disable_tailgating(uint32_t adc)
*/
void adc_set_warm_up_mode(uint32_t adc, uint32_t warmupmode)
{
ADC_CTRL(adc) = (ADC_CTRL(adc) & ~ADC_CTRL_WARMUPMODE_MASK) | warmupmode;
ADC_CTRL(adc) = (ADC_CTRL(adc) & ~ADC_CTRL_WARMUPMODE_MASK)
| warmupmode;
}
/**

33
lib/efm32/lg/cmu.c
View File

@@ -56,7 +56,8 @@ bool cmu_get_lock_flag(void)
*
* @param[in] periph enum cmu_periph_clken Peripheral Name
*
* For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for example)
* For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for
* example)
*/
void cmu_periph_clock_enable(enum cmu_periph_clken clken)
@@ -70,7 +71,8 @@ void cmu_periph_clock_enable(enum cmu_periph_clken clken)
*
* @param[in] periph enum cmu_periph_clken Peripheral Name
*
* For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for example)
* For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for
* example)
*/
void cmu_periph_clock_disable(enum cmu_periph_clken clken)
@@ -203,7 +205,7 @@ void cmu_wait_for_osc_ready(enum cmu_osc osc)
*/
void cmu_set_hfclk_source(enum cmu_osc osc)
{
switch(osc) {
switch (osc) {
case HFXO:
CMU_CMD = CMU_CMD_HFCLKSEL_HFXO;
break;
@@ -225,13 +227,13 @@ void cmu_set_hfclk_source(enum cmu_osc osc)
enum cmu_osc cmu_get_hfclk_source(void)
{
uint32_t status = CMU_STATUS;
if(status & CMU_STATUS_LFXOSEL) {
if (status & CMU_STATUS_LFXOSEL) {
return LFXO;
} else if(status & CMU_STATUS_LFRCOSEL) {
} else if (status & CMU_STATUS_LFRCOSEL) {
return LFRCO;
} else if(status & CMU_STATUS_HFXOSEL) {
} else if (status & CMU_STATUS_HFXOSEL) {
return HFXO;
} else if(status & CMU_STATUS_HFRCOSEL) {
} else if (status & CMU_STATUS_HFRCOSEL) {
return HFRCO;
}
@@ -245,11 +247,12 @@ enum cmu_osc cmu_get_hfclk_source(void)
void cmu_clock_setup_in_hfxo_out_48mhz(void)
{
/* configure HFXO and prescaler */
CMU_HFCORECLKDIV = CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV |
CMU_HFCORECLKDIV_HFCORECLKLEDIV;
CMU_CTRL = (CMU_CTRL &
~(CMU_CTRL_HFCLKDIV_MASK | CMU_CTRL_HFXOBUFCUR_MASK)) |
(CMU_CTRL_HFCLKDIV_NODIV | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ);
CMU_HFCORECLKDIV = CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV
| CMU_HFCORECLKDIV_HFCORECLKLEDIV;
CMU_CTRL = (CMU_CTRL
& ~(CMU_CTRL_HFCLKDIV_MASK | CMU_CTRL_HFXOBUFCUR_MASK))
| (CMU_CTRL_HFCLKDIV_NODIV
| CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ);
/* enable HFXO */
cmu_osc_on(HFXO);
@@ -258,12 +261,12 @@ void cmu_clock_setup_in_hfxo_out_48mhz(void)
cmu_wait_for_osc_ready(HFXO);
/* set flash wait state */
MSC_READCTRL = (MSC_READCTRL & ~MSC_READCTRL_MODE_MASK) |
MSC_READCTRL_MODE_WS2;
MSC_READCTRL = (MSC_READCTRL & ~MSC_READCTRL_MODE_MASK)
| MSC_READCTRL_MODE_WS2;
/* switch to HFXO */
cmu_set_hfclk_source(HFXO);
/* wait till HFXO not selected */
while(cmu_get_hfclk_source() != HFXO);
while (cmu_get_hfclk_source() != HFXO);
}

3
lib/efm32/lg/dac.c
View File

@@ -98,7 +98,8 @@ void dac_disable_sine(uint32_t dac)
* @param[in] dac_ch DAC Channel (use DAC_CHx)
* @param[in] prs_ch PRS Channel (use PRS_CHx)
*/
void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan, enum prs_ch prs_chan)
void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan,
enum prs_ch prs_chan)
{
uint32_t ch_ctrl = DAC_CHx_CTRL(dac, dac_chan);
ch_ctrl &= DAC_CH_CTRL_PRSSEL_MASK;

108
lib/efm32/lg/dma.c
View File

@@ -307,7 +307,8 @@ void dma_disable_done_interrupt(enum dma_ch ch)
*/
void dma_set_source(enum dma_ch ch, uint32_t source)
{
DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SOURCESEL_MASK) | source;
DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SOURCESEL_MASK)
| source;
}
/**
@@ -317,7 +318,8 @@ void dma_set_source(enum dma_ch ch, uint32_t source)
*/
void dma_set_signal(enum dma_ch ch, uint32_t signal)
{
DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SIGSEL_MASK) | signal;
DMA_CHx_CTRL(ch) = (DMA_CHx_CTRL(ch) & ~DMA_CH_CTRL_SIGSEL_MASK)
| signal;
}
/**
@@ -335,7 +337,7 @@ void dma_channel_reset(enum dma_ch ch)
/* clear channel interrupt */
DMA_IFC = DMA_IFC_CHxDONE(ch);
/* disable loop */
if(CHANNEL_SUPPORT_LOOP(ch)) {
if (CHANNEL_SUPPORT_LOOP(ch)) {
DMA_LOOPx(ch) = 0;
}
/* reset signal {source, select} */
@@ -350,11 +352,12 @@ void dma_channel_reset(enum dma_ch ch)
*/
void dma_set_loop_count(enum dma_ch ch, uint16_t count)
{
if(!CHANNEL_SUPPORT_LOOP(ch)) {
if (!CHANNEL_SUPPORT_LOOP(ch)) {
return;
}
DMA_LOOPx(ch) = (DMA_LOOPx(ch) & ~DMA_LOOP_WIDTH_MASK) | DMA_LOOP_WIDTH(count - 1);
DMA_LOOPx(ch) = (DMA_LOOPx(ch) & ~DMA_LOOP_WIDTH_MASK)
| DMA_LOOP_WIDTH(count - 1);
}
/**
@@ -363,7 +366,7 @@ void dma_set_loop_count(enum dma_ch ch, uint16_t count)
*/
void dma_enable_loop(enum dma_ch ch)
{
if(!CHANNEL_SUPPORT_LOOP(ch)) {
if (!CHANNEL_SUPPORT_LOOP(ch)) {
return;
}
@@ -376,7 +379,7 @@ void dma_enable_loop(enum dma_ch ch)
*/
void dma_disable_loop(enum dma_ch ch)
{
if(!CHANNEL_SUPPORT_LOOP(ch)) {
if (!CHANNEL_SUPPORT_LOOP(ch)) {
return;
}
@@ -385,11 +388,13 @@ void dma_disable_loop(enum dma_ch ch)
/**
* Set desination size
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] size Size (use DMA_MEM_*)
*/
void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem size)
void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch,
enum dma_mem size)
{
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
cfg &= ~DMA_DESC_CH_CFG_DEST_SIZE_MASK;
@@ -399,11 +404,13 @@ void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem siz
/**
* Set destination increment
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] inc Increment (use DMA_MEM_*)
*/
void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc)
void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch,
enum dma_mem inc)
{
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
cfg &= ~DMA_DESC_CH_CFG_DEST_INC_MASK;
@@ -413,11 +420,13 @@ void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc)
/**
* Set source size
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] size Size (use DMA_MEM_*)
*/
void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem size)
void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch,
enum dma_mem size)
{
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
cfg &= ~DMA_DESC_CH_CFG_SRC_SIZE_MASK;
@@ -427,7 +436,8 @@ void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch, enum dma_mem size
/**
* Set source increment
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] inc Increment (use DMA_MEM_*)
*/
@@ -442,11 +452,13 @@ void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch, enum dma_mem inc)
/**
* Set R Power
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] r_power R Power (Use DMA_R_POWER_*)
*/
void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch, enum dma_r_power r_power)
void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch,
enum dma_r_power r_power)
{
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
cfg &= ~DMA_DESC_CH_CFG_R_POWER_MASK;
@@ -456,7 +468,8 @@ void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch, enum dma_r_power r
/**
* Enable next useburst
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
*/
void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch)
@@ -466,7 +479,8 @@ void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch)
/**
* Disable next useburst
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
*/
void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch)
@@ -476,7 +490,8 @@ void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch)
/**
* Set number (count) of transfer to be performed
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] count Count
*/
@@ -490,18 +505,21 @@ void dma_desc_set_count(uint32_t desc_base, enum dma_ch ch, uint16_t count)
/**
* Store user data field in channel descriptor
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] user_data User data
*/
void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch, uint32_t user_data)
void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch,
uint32_t user_data)
{
DMA_DESC_CHx_USER_DATA(desc_base, ch) = user_data;
}
/**
* Extract user data field from channel descriptor
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @return user data
*/
@@ -522,7 +540,8 @@ uint32_t dma_desc_get_user_data(uint32_t desc_base, enum dma_ch ch)
* @return the calculate end address
* @note can be used to calculate {source, destination} end address
*/
inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc, uint16_t n_minus_1)
inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc,
uint16_t n_minus_1)
{
switch (inc) {
case DMA_MEM_BYTE:
@@ -540,49 +559,56 @@ inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc, uint16_t n_
/**
* Assign Source address to DMA Channel
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] src_start Source data start address
* @param[in] this function use dma_desc_set_count() and dma_desc_set_src_inc() set value
* to calculate the src data end address from @a src_start
* @param[in] this function use dma_desc_set_count() and dma_desc_set_src_inc()
* set value to calculate the src data end address from @a src_start
* @note dma_desc_set_count() should be called first.
* @note dma_desc_set_src_inc() should be called first.
*/
void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch, uint32_t src_start)
void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch,
uint32_t src_start)
{
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
uint8_t inc = (cfg & DMA_DESC_CH_CFG_SRC_INC_MASK) >>
DMA_DESC_CH_CFG_SRC_INC_SHIFT;
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK) >>
DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
uint8_t inc = (cfg & DMA_DESC_CH_CFG_SRC_INC_MASK)
>> DMA_DESC_CH_CFG_SRC_INC_SHIFT;
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK)
>> DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
uint32_t src_end = dma_calc_end_from_start(src_start, inc, n_minus_1);
DMA_DESC_CHx_SRC_DATA_END_PTR(desc_base, ch) = src_end;
}
/**
* Assign Destination address to DMA Channel
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] dest_start Destination data start address
* @param[in] this function use dma_desc_set_count() and dma_desc_set_dest_inc() set value
* to calculate the dest data end address from @a dest_start
* @param[in] this function use dma_desc_set_count() and
* dma_desc_set_dest_inc() set value to calculate the dest data end
* address from @a dest_start
* @note dma_desc_set_count() should be called first.
* @note dma_desc_set_dest_inc() should be called first.
*/
void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch, uint32_t dest_start)
void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch,
uint32_t dest_start)
{
uint32_t cfg = DMA_DESC_CHx_CFG(desc_base, ch);
uint8_t inc = (cfg & DMA_DESC_CH_CFG_DEST_INC_MASK) >>
DMA_DESC_CH_CFG_DEST_INC_SHIFT;
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK) >>
DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
uint32_t dest_end = dma_calc_end_from_start(dest_start, inc, n_minus_1);
uint8_t inc = (cfg & DMA_DESC_CH_CFG_DEST_INC_MASK)
>> DMA_DESC_CH_CFG_DEST_INC_SHIFT;
uint16_t n_minus_1 = (cfg & DMA_DESC_CH_CFG_N_MINUS_1_MASK)
>> DMA_DESC_CH_CFG_N_MINUS_1_SHIFT;
uint32_t dest_end = dma_calc_end_from_start(dest_start, inc,
n_minus_1);
DMA_DESC_CHx_DEST_DATA_END_PTR(desc_base, ch) = dest_end;
}
/**
* Set the channel mode ("Cycle control")
* @param[in] desc_base start of memory location that contain channel descriptor
* @param[in] desc_base start of memory location that contain channel
* descriptor
* @param[in] ch Channel (use DMA_CHx)
* @param[in] mode Mode (use DMA_MODE_*)
*/

14
lib/efm32/lg/gpio.c
View File

@@ -48,7 +48,8 @@ void gpio_disable_lock(void)
*/
bool gpio_get_lock_flag(void)
{
return (GPIO_LOCK & GPIO_LOCK_LOCKKEY_MASK) == GPIO_LOCK_LOCKKEY_LOCKED;
return (GPIO_LOCK & GPIO_LOCK_LOCKKEY_MASK)
== GPIO_LOCK_LOCKKEY_LOCKED;
}
/**
@@ -56,7 +57,8 @@ bool gpio_get_lock_flag(void)
* @param[in] gpio_port GPIO Port (use GPIO* ex. GPIOA, GPIOB, ....)
* @param[in] drive_stength Driver Stength (use GPIO_STENGTH_*)
*/
void gpio_set_drive_strength(uint32_t gpio_port, enum gpio_drive_strength drive_stength)
void gpio_set_drive_strength(uint32_t gpio_port,
enum gpio_drive_strength drive_stength)
{
GPIO_P_CTRL(gpio_port) = GPIO_P_CTRL_DRIVEMODE(drive_stength);
}
@@ -122,7 +124,7 @@ void gpio_clear(uint32_t gpio_port, uint16_t gpios)
*/
uint16_t gpio_get(uint32_t gpio_port, uint16_t gpios)
{
return (GPIO_P_DIN(gpio_port) & gpios);
return GPIO_P_DIN(gpio_port) & gpios;
}
/**
@@ -159,9 +161,9 @@ void gpio_port_write(uint32_t gpio_port, uint16_t data)
/**
* @brief Lock the Configuration of a Group of Pins
*
* The configuration of one or more pins of the given GPIO port is locked. There
* is no mechanism to unlock these via software. Unlocking occurs at the next
* reset.
* The configuration of one or more pins of the given GPIO port is locked.
* There is no mechanism to unlock these via software. Unlocking occurs at the
* next reset.
*
* @param[in] gpio_port GPIO Port (use GPIO* ex. GPIOA, GPIOB, ....)
* @param[in] gpios (pins mask (use GPIO* ex . GPIO0, GPIO1 .... GPIO_ALL,

6
lib/efm32/lg/prs.c
View File

@@ -123,7 +123,8 @@ void prs_set_edge(enum prs_ch ch, uint32_t edge)
*/
void prs_set_source(enum prs_ch ch, uint32_t source)
{
PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SOURCESEL_MASK) | source;
PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SOURCESEL_MASK)
| source;
}
/**
@@ -134,5 +135,6 @@ void prs_set_source(enum prs_ch ch, uint32_t source)
*/
void prs_set_signal(enum prs_ch ch, uint32_t signal)
{
PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SIGSEL_MASK) | signal;
PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SIGSEL_MASK)
| signal;
}

3
lib/efm32/lg/timer.c
View File

@@ -46,7 +46,8 @@ void timer_stop(uint32_t timer)
*/
void timer_set_clock_prescaler(uint32_t timer, uint32_t presc)
{
TIMER_CTRL(timer) = (TIMER_CTRL(timer) & ~TIMER_CTRL_PRESC_MASK) | presc;
TIMER_CTRL(timer) = (TIMER_CTRL(timer) & ~TIMER_CTRL_PRESC_MASK)
| presc;
}
/**