From 1e9a2e641cbf1f8d50870f3b30fa7c97a5eb97cc Mon Sep 17 00:00:00 2001 From: Chuck McManis Date: Fri, 2 Mar 2018 11:26:29 -0800 Subject: [PATCH] stm32F4: LTDC - bit defines without semantics The LTDC include file was defined with combined bit semantics and bit position. As a result instead of LTDC_GCR_VSPOL which is the bit which defines vertical sync polarity, this had been defined to be LTDC_GCR_VSPOL_LOW (0) and LTDC_GCR_VSPOL_HIGH (non zero). This sort of define makes it impossible to know ahead of time what operation would set or reset the bit (some are negative logic, others are postive logic, so affirmative defines could mean either "set the bit" or "reset the bit" I've added the non-semantic bit define so that it is clear in my code if the bit is being set or reset. Discussion took place at https://github.com/libopencm3/libopencm3/pull/889 --- include/libopencm3/stm32/f4/ltdc.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/libopencm3/stm32/f4/ltdc.h b/include/libopencm3/stm32/f4/ltdc.h index adf54d01..9a3abc07 100644 --- a/include/libopencm3/stm32/f4/ltdc.h +++ b/include/libopencm3/stm32/f4/ltdc.h @@ -153,6 +153,14 @@ #define LTDC_GCR_HSPOL_ACTIVE_LOW (0<<31) #define LTDC_GCR_HSPOL_ACTIVE_HIGH (1<<31) +/* GCR - register bit defines (no semantics) */ +#define LTDC_GCR_HSPOL (1 << 31) +#define LTDC_GCR_VSPOL (1 << 30) +#define LTDC_GCR_DEPOL (1 << 29) +#define LTDC_GCR_PCPOL (1 << 28) +#define LTDC_GCR_DITHER (1 << 16) +#define LTDC_GCR_LTDCEN (1 << 0) + /* --- LTDC_SRCR values ---------------------------------------------------- */ /* Vertical Blanking Reload */