From 1adc418f9afaa5b99c34f3eea797dc4c1155c056 Mon Sep 17 00:00:00 2001
From: Alfred Klomp <alfred@ampyxpower.com>
Date: Mon, 12 Nov 2018 17:06:59 +0100
Subject: [PATCH] stm32f42/f43: rcc: add 180 MHz clock options

---
 include/libopencm3/stm32/f4/rcc.h |  1 +
 lib/stm32/f4/rcc.c                | 64 +++++++++++++++++++++++++++++++
 2 files changed, 65 insertions(+)

diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index 60366b69..4e195f00 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -770,6 +770,7 @@ enum rcc_clock_3v3 {
 	RCC_CLOCK_3V3_84MHZ,
 	RCC_CLOCK_3V3_120MHZ,
 	RCC_CLOCK_3V3_168MHZ,
+	RCC_CLOCK_3V3_180MHZ,
 	RCC_CLOCK_3V3_END
 };
 
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index 7e3c0da3..8a92ec40 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -114,6 +114,22 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
+	{ /* 180MHz */
+		.pllm = 8,
+		.plln = 360,
+		.pllp = 2,
+		.pllq = 8,
+		.pllr = 0,
+		.hpre = RCC_CFGR_HPRE_DIV_NONE,
+		.ppre1 = RCC_CFGR_PPRE_DIV_4,
+		.ppre2 = RCC_CFGR_PPRE_DIV_2,
+		.voltage_scale = PWR_SCALE1,
+		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
+	},
 };
 
 const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
@@ -181,6 +197,22 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
+	{ /* 180MHz */
+		.pllm = 12,
+		.plln = 360,
+		.pllp = 2,
+		.pllq = 8,
+		.pllr = 0,
+		.hpre = RCC_CFGR_HPRE_DIV_NONE,
+		.ppre1 = RCC_CFGR_PPRE_DIV_4,
+		.ppre2 = RCC_CFGR_PPRE_DIV_2,
+		.voltage_scale = PWR_SCALE1,
+		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
+	},
 };
 
 const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
@@ -248,6 +280,22 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
+	{ /* 180MHz */
+		.pllm = 16,
+		.plln = 360,
+		.pllp = 2,
+		.pllq = 8,
+		.pllr = 0,
+		.hpre = RCC_CFGR_HPRE_DIV_NONE,
+		.ppre1 = RCC_CFGR_PPRE_DIV_4,
+		.ppre2 = RCC_CFGR_PPRE_DIV_2,
+		.voltage_scale = PWR_SCALE1,
+		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
+	},
 };
 
 const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
@@ -315,6 +363,22 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
+	{ /* 180MHz */
+		.pllm = 25,
+		.plln = 360,
+		.pllp = 2,
+		.pllq = 8,
+		.pllr = 0,
+		.hpre = RCC_CFGR_HPRE_DIV_NONE,
+		.ppre1 = RCC_CFGR_PPRE_DIV_4,
+		.ppre2 = RCC_CFGR_PPRE_DIV_2,
+		.voltage_scale = PWR_SCALE1,
+		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
+	},
 };
 
 void rcc_osc_ready_int_clear(enum rcc_osc osc)