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stm32f7: flash: doxygenize existing comments.

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Just putting it in a different place and it all gets included in the
output nicely.
This commit is contained in:
Karl Palsson
2020-12-10 22:26:05 +00:00
parent 97d5e9a403
commit 1abb945dcd
1 changed files with 9 additions and 11 deletions
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20
include/libopencm3/stm32/f7/flash.h
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@@ -9,6 +9,15 @@
* @author @htmlonly © @endhtmlonly 2010 * @author @htmlonly © @endhtmlonly 2010
* Mark Butler <mbutler@physics.otago.ac.nz> * Mark Butler <mbutler@physics.otago.ac.nz>
* *
* Differences between F7 and F4:
* 1. icache and dcache are now combined into a unified ART cache. The CPU has
* its own d/i-caches, but those are unrelated to this. They are on the
* AXIM bus.
* 4. FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR (
* erase sequence error).
* 6. There are now two watchdogs - IWDG (independent watchdog) and WWDG (
* window watchdog).
*
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
@@ -38,17 +47,6 @@
#include <libopencm3/stm32/common/flash_common_f.h> #include <libopencm3/stm32/common/flash_common_f.h>
#include <libopencm3/stm32/common/flash_common_f24.h> #include <libopencm3/stm32/common/flash_common_f24.h>
/*
* Differences between F7 and F4:
* 1. icache and dcache are now combined into a unified ART cache. The CPU has
* its own d/i-caches, but those are unrelated to this. They are on the
* AXIM bus.
* 4. FLASH_SR_PGSERR (programming sequence error) is now FLASH_SR_ERSERR (
* erase sequence error).
* 6. There are now two watchdogs - IWDG (independent watchdog) and WWDG (
* window watchdog).
*/
/**@{*/ /**@{*/
/* --- FLASH_ACR values ---------------------------------------------------- */ /* --- FLASH_ACR values ---------------------------------------------------- */