diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c
index dc0d1db9..3f9129ee 100644
--- a/lib/stm32/common/timer_common_all.c
+++ b/lib/stm32/common/timer_common_all.c
@@ -898,6 +898,40 @@ void timer_set_oc2_mode(uint32_t timer_peripheral, enum tim_oc_mode oc_mode)
 	}
 }
 
+void timer_set_oc3_mode(uint32_t timer_peripheral, enum tim_oc_mode oc_mode)
+{
+	TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
+	TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
+	TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK;
+	switch (oc_mode) {
+	case TIM_OCM_FROZEN:
+		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN;
+		break;
+	case TIM_OCM_ACTIVE:
+		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
+		break;
+	case TIM_OCM_INACTIVE:
+		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE;
+		break;
+	case TIM_OCM_TOGGLE:
+		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE;
+		break;
+	case TIM_OCM_FORCE_LOW:
+		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
+		break;
+	case TIM_OCM_FORCE_HIGH:
+		TIM_CCMR2(timer_peripheral) |=
+			TIM_CCMR2_OC3M_FORCE_HIGH;
+		break;
+	case TIM_OCM_PWM1:
+		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
+		break;
+	case TIM_OCM_PWM2:
+		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2;
+		break;
+	}
+}
+
 /*---------------------------------------------------------------------------*/
 /** @brief Timer Set Output Compare Mode
 
@@ -936,36 +970,7 @@ void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
 		timer_set_oc2_mode(timer_peripheral, oc_mode);
 		break;
 	case TIM_OC3:
-		TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
-		TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
-		TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK;
-		switch (oc_mode) {
-		case TIM_OCM_FROZEN:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN;
-			break;
-		case TIM_OCM_ACTIVE:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
-			break;
-		case TIM_OCM_INACTIVE:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE;
-			break;
-		case TIM_OCM_TOGGLE:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE;
-			break;
-		case TIM_OCM_FORCE_LOW:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
-			break;
-		case TIM_OCM_FORCE_HIGH:
-			TIM_CCMR2(timer_peripheral) |=
-			    TIM_CCMR2_OC3M_FORCE_HIGH;
-			break;
-		case TIM_OCM_PWM1:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
-			break;
-		case TIM_OCM_PWM2:
-			TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2;
-			break;
-		}
+		timer_set_oc3_mode(timer_peripheral, oc_mode);
 		break;
 	case TIM_OC4:
 		TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;