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stm32f3: rcc: Set prescalers properly.

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Copypasta from f4 rcc code was only modified to shift the result, but not clear
the existing settings properly. Add mask/shift definitions and use them
properly.
This commit is contained in:
Karl Palsson
2015-10-22 22:34:29 +00:00
parent ce9dab2a92
commit 10ef294e5d
2 changed files with 9 additions and 6 deletions
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12
lib/stm32/f3/rcc.c
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@@ -343,8 +343,8 @@ void rcc_set_ppre2(uint32_t ppre2)
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15));
RCC_CFGR = (reg32 | (ppre2 << 11));
reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
}
void rcc_set_ppre1(uint32_t ppre1)
@@ -352,8 +352,8 @@ void rcc_set_ppre1(uint32_t ppre1)
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12));
RCC_CFGR = (reg32 | (ppre1 << 8));
reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
}
void rcc_set_hpre(uint32_t hpre)
@@ -361,8 +361,8 @@ void rcc_set_hpre(uint32_t hpre)
uint32_t reg32;
reg32 = RCC_CFGR;
reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7));
RCC_CFGR = (reg32 | (hpre << 4));
reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
}