Initial documentation for SPI, I2C and CRC
(no code changes)
This commit is contained in:
Ken Sarkies
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
c4b7e2a76a
commit
0c779512d6
408
lib/stm32/spi.c
408
lib/stm32/spi.c
@@ -1,3 +1,43 @@
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/** @defgroup spi_file SPI
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@ingroup STM32F_files
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@brief <b>libopencm3 STM32Fxxx SPI</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
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@date 15 October 2012
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Devices can have up to three SPI peripherals. The common 4-wire full-duplex
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mode of operation is supported, along with 3-wire variants using unidirectional
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communication modes or half-duplex bidirectional communication. A variety of
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options allows many of the SPI variants to be supported. Multimaster operation
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is also supported. A CRC can be generated and checked in hardware.
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@note Some JTAG pins need to be remapped if SPI is to be used.
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@note The I2S protocol shares the SPI hardware so the two protocols cannot be
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used at the same time on the same peripheral.
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Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words,
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LSB first.
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@code
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spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
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SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT,
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SPI_CR1_LSBFIRST);
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spi_write(SPI1, 0x55); // 8-bit write
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spi_write(SPI1, 0xaa88); // 16-bit write
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reg8 = spi_read(SPI1); // 8-bit read
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reg16 = spi_read(SPI1); // 16-bit read
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@endcode
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@todo need additional functions to aid ISRs in retrieving status
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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@@ -41,6 +81,17 @@
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* reg16 = spi_read(SPI1); // 16-bit read
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*/
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/**@{*/
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Reset.
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The SPI peripheral and all its associated configuration registers are placed in the
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reset condition. The reset is effected via the RCC peripheral reset system.
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@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_reset(u32 spi_peripheral)
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{
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switch (spi_peripheral) {
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@@ -59,6 +110,25 @@ void spi_reset(u32 spi_peripheral)
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}
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief Configure the SPI as Master.
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The SPI peripheral is configured as a master with communication parameters
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baudrate, data format 8/16 bits, frame format lsb/msb first, clock polarity
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and phase. The SPI enable, CRC enable and CRC next controls are not affected.
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These must be controlled separately.
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@todo NSS pin handling.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] br Unsigned int32. Baudrate @ref spi_baudrate.
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@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol.
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@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha.
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@param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff.
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@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst.
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@returns int. Error code.
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*/
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int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
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{
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u32 reg32 = SPI_CR1(spi);
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@@ -82,28 +152,66 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst)
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}
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/* TODO: Error handling? */
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Enable.
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The SPI peripheral is enabled.
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@todo Error handling?
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_enable(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_SPE; /* Enable SPI. */
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}
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/* TODO: Error handling? */
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Disable.
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The SPI peripheral is disabled.
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@todo Follow procedure from section 23.3.8 in the TRM.
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(possibly create a "clean disable" function separately)
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_disable(u32 spi)
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{
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u32 reg32;
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/* TODO: Follow procedure from section 23.3.8 in the TRM. */
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reg32 = SPI_CR1(spi);
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reg32 &= ~(SPI_CR1_SPE); /* Disable SPI. */
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SPI_CR1(spi) = reg32;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Data Write.
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Data is written to the SPI interface.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] data Unsigned int16. 8 or 16 bit data to be written.
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*/
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void spi_write(u32 spi, u16 data)
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{
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/* Write data (8 or 16 bits, depending on DFF) into DR. */
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SPI_DR(spi) = data;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Data Write with Blocking.
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Data is written to the SPI interface after the previous write transfer has finished.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] data Unsigned int16. 8 or 16 bit data to be written.
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*/
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void spi_send(u32 spi, u16 data)
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{
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/* Wait for transfer finished. */
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@@ -114,6 +222,15 @@ void spi_send(u32 spi, u16 data)
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SPI_DR(spi) = data;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Data Read.
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Data is read from the SPI interface after the incoming transfer has finished.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@returns data Unsigned int16. 8 or 16 bit data.
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*/
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u16 spi_read(u32 spi)
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{
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/* Wait for transfer finished. */
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@@ -124,6 +241,17 @@ u16 spi_read(u32 spi)
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return SPI_DR(spi);
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Data Write and Read Exchange.
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Data is written to the SPI interface, then a read is done after the incoming transfer
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has finished.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] data Unsigned int16. 8 or 16 bit data to be written.
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@returns data Unsigned int16. 8 or 16 bit data.
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*/
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u16 spi_xfer(u32 spi, u16 data)
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{
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spi_write(spi, data);
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@@ -136,98 +264,251 @@ u16 spi_xfer(u32 spi, u16 data)
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return SPI_DR(spi);
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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(using a clock wire and a bidirectional data wire).
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_bidirectional_mode(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Unidirectional Mode.
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The SPI peripheral is set for unidirectional transfers. This is used in full duplex
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mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a
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unidirectional data wire.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_unidirectional_mode(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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(using a clock wire and a bidirectional data wire), and is placed in a receive state.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_bidirectional_receive_only_mode(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
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SPI_CR1(spi) &= ~SPI_CR1_BIDIOE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Bidirectional Simplex Receive Only Mode.
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The SPI peripheral is set for bidirectional transfers in two-wire simplex mode
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(using a clock wire and a bidirectional data wire), and is placed in a transmit state.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_bidirectional_transmit_only_mode(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_BIDIMODE;
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SPI_CR1(spi) |= SPI_CR1_BIDIOE;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Enable the CRC.
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The SPI peripheral is set to use a CRC field for transmit and receive.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_enable_crc(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_CRCEN;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Disable the CRC.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_disable_crc(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_CRCEN;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Next Transmit is a Data Word
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The next transmission to take place is a data word from the transmit buffer.
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This must be called before transmission to distinguish between sending
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of a data or CRC word.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_next_tx_from_buffer(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Next Transmit is a CRC Word
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The next transmission to take place is a crc word from the hardware crc unit.
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This must be called before transmission to distinguish between sending
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of a data or CRC word.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_next_tx_from_crc(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_CRCNEXT;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Data Frame Format to 8 bits
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_dff_8bit(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_DFF;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Data Frame Format to 16 bits
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_dff_16bit(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_DFF;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Full Duplex (3-wire) Mode
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_full_duplex_mode(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_RXONLY;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_receive_only_mode(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_RXONLY;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Enable Slave Management by Hardware
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In slave mode the NSS hardware input is used as a select enable for the slave.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_disable_software_slave_management(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_SSM;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Enable Slave Management by Software
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In slave mode the NSS hardware input is replaced by an internal software
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enable/disable of the slave (@ref spi_set_nss_high).
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_enable_software_slave_management(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_SSM;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set the Software NSS Signal High
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In slave mode, and only when software slave management is used, this replaces
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the NSS signal with a slave select enable signal.
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@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_nss_high(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_SSI;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set the Software NSS Signal Low
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In slave mode, and only when software slave management is used, this replaces
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the NSS signal with a slave select disable signal.
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_nss_low(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_SSI;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set to Send LSB First
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_send_lsb_first(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_LSBFIRST;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set to Send MSB First
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_send_msb_first(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set the Baudrate Prescaler
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@todo Why is this specification different to the spi_init_master baudrate values?
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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@param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre.
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*/
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void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
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{
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u32 reg32;
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@@ -240,92 +521,217 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate)
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SPI_CR1(spi) = reg32;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set to Master Mode
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_master_mode(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_MSTR;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set to Slave Mode
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_slave_mode(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_MSTR;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set the Clock Polarity to High when Idle
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_clock_polarity_1(u32 spi)
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{
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SPI_CR1(spi) |= SPI_CR1_CPOL;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief SPI Set the Clock Polarity to Low when Idle
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@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
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*/
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void spi_set_clock_polarity_0(u32 spi)
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{
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SPI_CR1(spi) &= ~SPI_CR1_CPOL;
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}
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/*-----------------------------------------------------------------------------*/
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||||
/** @brief SPI Set the Clock Phase to Capture on Trailing Edge
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_set_clock_phase_1(u32 spi)
|
||||
{
|
||||
SPI_CR1(spi) |= SPI_CR1_CPHA;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the Clock Phase to Capture on Leading Edge
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_set_clock_phase_0(u32 spi)
|
||||
{
|
||||
SPI_CR1(spi) &= ~SPI_CR1_CPHA;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable the Transmit Buffer Empty Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_enable_tx_buffer_empty_interrupt(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) |= SPI_CR2_TXEIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable the Transmit Buffer Empty Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_disable_tx_buffer_empty_interrupt(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) &= ~SPI_CR2_TXEIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable the Receive Buffer Ready Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_enable_rx_buffer_not_empty_interrupt(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) |= SPI_CR2_RXNEIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable the Receive Buffer Ready Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_disable_rx_buffer_not_empty_interrupt(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) &= ~SPI_CR2_RXNEIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable the Error Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_enable_error_interrupt(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) |= SPI_CR2_ERRIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable the Error Interrupt
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_disable_error_interrupt(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) &= ~SPI_CR2_ERRIE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the NSS Pin as an Output
|
||||
|
||||
Normally used in master mode to allows the master to place all devices on the
|
||||
SPI bus into slave mode. Multimaster mode is not possible.
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_enable_ss_output(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) |= SPI_CR2_SSOE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Set the NSS Pin as an Input
|
||||
|
||||
In master mode this allows the master to sense the presence of other masters. If
|
||||
NSS is then pulled low the master is placed into slave mode. In slave mode NSS
|
||||
becomes a slave enable.
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_disable_ss_output(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) &= ~SPI_CR2_SSOE;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable Transmit Transfers via DMA
|
||||
|
||||
This allows transmissions to proceed unattended using DMA to move data to the
|
||||
transmit buffer as it becomes available. The DMA channels provided for each
|
||||
SPI peripheral are given in the Technical Manual DMA section.
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_enable_tx_dma(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) |= SPI_CR2_TXDMAEN;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable Transmit Transfers via DMA
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_disable_tx_dma(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Enable Receive Transfers via DMA
|
||||
|
||||
This allows received data streams to proceed unattended using DMA to move data from
|
||||
the receive buffer as data becomes available. The DMA channels provided for each
|
||||
SPI peripheral are given in the Technical Manual DMA section.
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_enable_rx_dma(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) |= SPI_CR2_RXDMAEN;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief SPI Disable Receive Transfers via DMA
|
||||
|
||||
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
|
||||
*/
|
||||
|
||||
void spi_disable_rx_dma(u32 spi)
|
||||
{
|
||||
SPI_CR2(spi) &= ~SPI_CR2_RXDMAEN;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
|
||||
Reference in New Issue
Block a user