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Initial documentation for SPI, I2C and CRC

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(no code changes)
This commit is contained in:
Ken Sarkies
2012-10-15 14:34:33 +10:30
committed by Piotr Esden-Tempski
parent c4b7e2a76a
commit 0c779512d6
6 changed files with 730 additions and 3 deletions
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14
include/libopencm3/stm32/crc.h
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@@ -1,3 +1,17 @@
/** @defgroup crc_defines CRC Defines
@brief <b>libopencm3 Defined Constants and Types for the STM32F CRC Generator </b>
@ingroup STM32F_defines
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@date 18 August 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*

38
include/libopencm3/stm32/i2c.h
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@@ -1,3 +1,19 @@
/** @defgroup i2c_defines I2C Defines
@ingroup STM32F_defines
@brief <b>libopencm3 Defined Constants and Types for the STM32 I2C </b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 12 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -23,11 +39,19 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* --- Convenience macros -------------------------------------------------- */
/* I2C register base adresses (for convenience) */
/****************************************************************************/
/** @defgroup i2c_reg_base I2C register base address
@ingroup i2c_defines
@{*/
#define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE
/**@}*/
/* --- I2C registers ------------------------------------------------------- */
@@ -146,6 +170,11 @@
/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */
/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz) */
/****************************************************************************/
/** @defgroup i2c_clock I2C clock frequency settings
@ingroup i2c_defines
@{*/
#define I2C_CR2_FREQ_2MHZ 0x02
#define I2C_CR2_FREQ_3MHZ 0x03
#define I2C_CR2_FREQ_4MHZ 0x04
@@ -181,6 +210,7 @@
#define I2C_CR2_FREQ_34MHZ 0x22
#define I2C_CR2_FREQ_35MHZ 0x23
#define I2C_CR2_FREQ_36MHZ 0x24
/**@}*/
/* --- I2Cx_OAR1 values ---------------------------------------------------- */
@@ -311,8 +341,14 @@
/* --- I2C const definitions ----------------------------------------------- */
/****************************************************************************/
/** @defgroup i2c_rw I2C Read/Write bit
@ingroup i2c_defines
@{*/
#define I2C_WRITE 0
#define I2C_READ 1
/**@}*/
/* --- I2C funtion prototypes----------------------------------------------- */
@@ -336,3 +372,5 @@ void i2c_send_data(u32 i2c, u8 data);
END_DECLS
#endif
/**@}*/

62
include/libopencm3/stm32/spi.h
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@@ -1,3 +1,19 @@
/** @defgroup spi_defines SPI Defines
@ingroup STM32F_defines
@brief <b>libopencm3 Defined Constants and Types for the STM32 SPI </b>
@version 1.0.0
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
@date 12 October 2012
LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
@@ -23,13 +39,21 @@
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* Registers can be accessed as 16bit or 32bit values. */
/* --- Convenience macros -------------------------------------------------- */
/****************************************************************************/
/** @defgroup spi_reg_base SPI Register base address
@ingroup spi_defines
@{*/
#define SPI1 SPI1_BASE
#define SPI2 SPI2_I2S_BASE
#define SPI3 SPI3_I2S_BASE
/**@}*/
/* --- SPI registers ------------------------------------------------------- */
@@ -110,8 +134,14 @@
#define SPI_CR1_CRCNEXT (1 << 12)
/* DFF: Data frame format */
/****************************************************************************/
/** @defgroup spi_dff SPI data frame format
@ingroup spi_defines
@{*/
#define SPI_CR1_DFF_8BIT (0 << 11)
#define SPI_CR1_DFF_16BIT (1 << 11)
/**@}*/
#define SPI_CR1_DFF (1 << 11)
/* RXONLY: Receive only */
@@ -124,13 +154,24 @@
#define SPI_CR1_SSI (1 << 8)
/* LSBFIRST: Frame format */
/****************************************************************************/
/** @defgroup spi_lsbfirst SPI lsb/msb first
@ingroup spi_defines
@{*/
#define SPI_CR1_MSBFIRST (0 << 7)
#define SPI_CR1_LSBFIRST (1 << 7)
/**@}*/
/* SPE: SPI enable */
#define SPI_CR1_SPE (1 << 6)
/* BR[2:0]: Baud rate control */
/****************************************************************************/
/** @defgroup spi_baudrate SPI peripheral baud rates
@ingroup spi_defines
@{*/
#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3)
@@ -139,6 +180,12 @@
#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3)
#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3)
/**@}*/
/****************************************************************************/
/** @defgroup spi_br_pre SPI peripheral baud rate prescale values
@ingroup spi_defines
@{*/
#define SPI_CR1_BR_FPCLK_DIV_2 0x0
#define SPI_CR1_BR_FPCLK_DIV_4 0x1
#define SPI_CR1_BR_FPCLK_DIV_8 0x2
@@ -147,18 +194,31 @@
#define SPI_CR1_BR_FPCLK_DIV_64 0x5
#define SPI_CR1_BR_FPCLK_DIV_128 0x6
#define SPI_CR1_BR_FPCLK_DIV_256 0x7
/**@}*/
/* MSTR: Master selection */
#define SPI_CR1_MSTR (1 << 2)
/* CPOL: Clock polarity */
/****************************************************************************/
/** @defgroup spi_cpol SPI clock polarity
@ingroup spi_defines
@{*/
#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1)
#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1)
/**@}*/
#define SPI_CR1_CPOL (1 << 1)
/* CPHA: Clock phase */
/****************************************************************************/
/** @defgroup spi_cpha SPI clock phase
@ingroup spi_defines
@{*/
#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0)
#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0)
/**@}*/
#define SPI_CR1_CPHA (1 << 0)
/* --- SPI_CR2 values ------------------------------------------------------ */
@@ -347,4 +407,6 @@ void spi_disable_rx_dma(u32 spi);
END_DECLS
/**@}*/
#endif