Deduplication of flash code for STM32F0 and F1.
Extension of code for STM32F1 to allow for dual bank series XL. Small changes to documentation for F2, F4 and L1 to add a parameter reference. Tested with STM32F103RBT6 (note: tests show that the PG bit must be cleared after programming, otherwise a subsequent erase attempt fails. This has been added to flash_program_half_word for F0 and F1 only. A fix for the other families is not included in this PR.)
This commit is contained in:
Ken Sarkies
committed by
Frantisek Burian
Frantisek Burian
parent
a4d9a41093
commit
0af6d06eda
@@ -39,7 +39,7 @@ OBJS = flash.o rcc.o usart.o dma.o rtc.o comparator.o crc.o \
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OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o \
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pwr_common_all.o iwdg_common_all.o rtc_common_l1f024.o \
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dma_common_l1f013.o exti_common_all.o spi_common_all.o \
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spi_common_f03.o
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spi_common_f03.o flash_common_f01.o
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VPATH += ../../usb:../:../../cm3:../common
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@@ -14,6 +14,16 @@
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* For the STM32F05x, accessing FLASH memory is described in
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* section 3 of the STM32F05x Reference Manual.
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*
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* FLASH memory may be used for data storage as well as code, and may be
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* programmatically modified. Note that for firmware upload the STM32F1xx
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* provides a built-in bootloader in system memory that can be entered from a
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* running program.
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*
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* FLASH must first be unlocked before programming. In this module a write to
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* FLASH is a blocking operation until the end-of-operation flag is asserted.
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*
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* @note: don't forget to lock it again when all operations are complete.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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@@ -41,87 +51,35 @@
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#include <libopencm3/stm32/flash.h>
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/*---------------------------------------------------------------------------*/
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/** @brief Enable the FLASH Prefetch Buffer
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/** @brief Clear All Status Flags
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This buffer is used for instruction fetches and is enabled by default after
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reset.
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Note carefully the clock restrictions under which the prefetch buffer may be
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enabled or disabled. Changes are normally made while the clock is running in
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the power-on low frequency mode before being set to a higher speed mode.
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See the reference manual for details.
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Program error, end of operation, write protect error, busy.
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*/
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void flash_prefetch_buffer_enable(void)
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void flash_clear_status_flags(void)
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{
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FLASH_ACR |= FLASH_ACR_PRFTBE;
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flash_clear_pgerr_flag();
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flash_clear_eop_flag();
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flash_clear_wrprterr_flag();
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flash_clear_bsy_flag();
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Disable the FLASH Prefetch Buffer
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/** @brief Read All Status Flags
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Note carefully the clock restrictions under which the prefetch buffer may be
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set to disabled. See the reference manual for details.
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The programming error, end of operation, write protect error and busy flags
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are returned in the order of appearance in the status register.
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@returns uint32_t. bit 0: busy, bit 2: programming error, bit 4: write protect
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error, bit 5: end of operation.
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*/
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void flash_prefetch_buffer_disable(void)
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uint32_t flash_get_status_flags(void)
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{
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FLASH_ACR &= ~FLASH_ACR_PRFTBE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Set the Number of Wait States
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Used to match the system clock to the FLASH memory access time. See the
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reference manual for more information on clock speed ranges for each wait state.
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The latency must be changed to the appropriate value <b>before</b> any increase
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in clock speed, or <b>after</b> any decrease in clock speed.
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@param[in] uint32_t ws: values 0 or 1 only.
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*/
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void flash_set_ws(uint32_t ws)
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{
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FLASH_ACR = (FLASH_ACR & ~FLASH_ACR_LATENCY) | ws;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Wait for Busy Flag
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This loops indefinitely until the busy flag is clear.
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*/
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void flash_wait_busy(void)
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{
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while ((FLASH_SR & FLASH_SR_BSY) != 0);
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}
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/*---------------------------------------------------------------------------*/
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/** @brief Program a 32 bit Word to FLASH
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This performs all operations necessary to program a 32 bit word to FLASH memory.
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The program error flag should be checked separately for the event that memory
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was not properly erased.
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@param[in] uint32_t address. Full address of flash word to be programmed.
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@param[in] uint32_t data.
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*/
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void flash_program_u32(uint32_t address, uint32_t data)
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{
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flash_wait_busy();
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FLASH_CR |= FLASH_CR_PG;
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MMIO16(address) = (uint16_t)data;
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flash_wait_busy();
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MMIO16(address + 2) = data >> 16;
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flash_wait_busy();
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FLASH_CR &= ~FLASH_CR_PG;
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return (FLASH_SR & (FLASH_SR_PGERR |
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FLASH_SR_EOP |
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FLASH_SR_WRPRTERR |
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FLASH_SR_BSY));
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}
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/*---------------------------------------------------------------------------*/
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@@ -131,19 +89,21 @@ This performs all operations necessary to program a 16 bit word to FLASH memory.
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The program error flag should be checked separately for the event that memory
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was not properly erased.
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@param[in] uint32_t address Full address of flash half word to be programmed.
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Status bit polling is used to detect end of operation.
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@param[in] uint32_t address. Full address of flash half word to be programmed.
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@param[in] uint16_t data.
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*/
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void flash_program_u16(uint32_t address, uint16_t data)
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void flash_program_half_word(uint32_t address, uint16_t data)
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{
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flash_wait_busy();
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flash_wait_for_last_operation();
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FLASH_CR |= FLASH_CR_PG;
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MMIO16(address) = data;
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flash_wait_busy();
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_CR_PG;
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}
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@@ -163,13 +123,14 @@ the FLASH programming manual for details.
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void flash_erase_page(uint32_t page_address)
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{
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flash_wait_busy();
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flash_wait_for_last_operation();
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FLASH_CR |= FLASH_CR_PER;
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FLASH_AR = page_address;
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FLASH_CR |= FLASH_CR_STRT;
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flash_wait_busy();
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_CR_PER;
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}
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@@ -182,13 +143,15 @@ memory. The information block is unaffected.
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void flash_erase_all_pages(void)
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{
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flash_wait_busy();
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flash_wait_for_last_operation();
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FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
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FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
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flash_wait_busy();
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
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}
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/**@}*/
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