Merge branch 'master' into efm32
Conflicts: Makefile
This commit is contained in:
chrysn
138
include/libopencm3/lpc17xx/gpio.h
Normal file
138
include/libopencm3/lpc17xx/gpio.h
Normal file
@@ -0,0 +1,138 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC17XX_GPIO_H
|
||||
#define LPC17XX_GPIO_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/lpc17xx/memorymap.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* GPIO port base addresses (for convenience) */
|
||||
#define GPIO0 GPIO_PIO0_BASE
|
||||
#define GPIO1 GPIO_PIO1_BASE
|
||||
#define GPIO2 GPIO_PIO2_BASE
|
||||
#define GPIO3 GPIO_PIO3_BASE
|
||||
#define GPIO4 GPIO_PIO4_BASE
|
||||
|
||||
/* GPIO number definitions (for convenience) */
|
||||
#define GPIOPIN0 (1 << 0)
|
||||
#define GPIOPIN1 (1 << 1)
|
||||
#define GPIOPIN2 (1 << 2)
|
||||
#define GPIOPIN3 (1 << 3)
|
||||
#define GPIOPIN4 (1 << 4)
|
||||
#define GPIOPIN5 (1 << 5)
|
||||
#define GPIOPIN6 (1 << 6)
|
||||
#define GPIOPIN7 (1 << 7)
|
||||
#define GPIOPIN8 (1 << 8)
|
||||
#define GPIOPIN9 (1 << 9)
|
||||
#define GPIOPIN10 (1 << 10)
|
||||
#define GPIOPIN11 (1 << 11)
|
||||
#define GPIOPIN12 (1 << 12)
|
||||
#define GPIOPIN13 (1 << 13)
|
||||
#define GPIOPIN14 (1 << 14)
|
||||
#define GPIOPIN15 (1 << 15)
|
||||
#define GPIOPIN16 (1 << 16)
|
||||
#define GPIOPIN17 (1 << 17)
|
||||
#define GPIOPIN18 (1 << 18)
|
||||
#define GPIOPIN19 (1 << 19)
|
||||
#define GPIOPIN20 (1 << 20)
|
||||
#define GPIOPIN21 (1 << 21)
|
||||
#define GPIOPIN22 (1 << 22)
|
||||
#define GPIOPIN23 (1 << 23)
|
||||
#define GPIOPIN24 (1 << 24)
|
||||
#define GPIOPIN25 (1 << 25)
|
||||
#define GPIOPIN26 (1 << 26)
|
||||
#define GPIOPIN27 (1 << 27)
|
||||
#define GPIOPIN28 (1 << 28)
|
||||
#define GPIOPIN29 (1 << 29)
|
||||
#define GPIOPIN30 (1 << 30)
|
||||
#define GPIOPIN31 (1 << 31)
|
||||
|
||||
/* --- GPIO registers ------------------------------------------------------ */
|
||||
|
||||
/* GPIO data direction register (GPIOn_DIR) */
|
||||
#define GPIO_DIR(port) MMIO32(port + 0x00)
|
||||
#define GPIO0_DIR GPIO_DIR(GPIO0)
|
||||
#define GPIO1_DIR GPIO_DIR(GPIO1)
|
||||
#define GPIO2_DIR GPIO_DIR(GPIO2)
|
||||
#define GPIO3_DIR GPIO_DIR(GPIO3)
|
||||
#define GPIO4_DIR GPIO_DIR(GPIO4)
|
||||
|
||||
/* GPIO fast mask register (GPIOn_DIR) */
|
||||
#define GPIO_MASK(port) MMIO32(port + 0x10)
|
||||
#define GPIO0_MASK GPIO_MASK(GPIO0)
|
||||
#define GPIO1_MASK GPIO_MASK(GPIO1)
|
||||
#define GPIO2_MASK GPIO_MASK(GPIO2)
|
||||
#define GPIO3_MASK GPIO_MASK(GPIO3)
|
||||
#define GPIO4_MASK GPIO_MASK(GPIO4)
|
||||
|
||||
/* GPIO port pin value register (GPIOn_PIN) */
|
||||
#define GPIO_PIN(port) MMIO32(port + 0x14)
|
||||
#define GPIO0_PIN GPIO_PIN(GPIO0)
|
||||
#define GPIO1_PIN GPIO_PIN(GPIO1)
|
||||
#define GPIO2_PIN GPIO_PIN(GPIO2)
|
||||
#define GPIO3_PIN GPIO_PIN(GPIO3)
|
||||
#define GPIO4_PIN GPIO_PIN(GPIO4)
|
||||
|
||||
/* GPIO port output set register (GPIOn_SET) */
|
||||
#define GPIO_SET(port) MMIO32(port + 0x18)
|
||||
#define GPIO0_SET GPIO_SET(GPIO0)
|
||||
#define GPIO1_SET GPIO_SET(GPIO1)
|
||||
#define GPIO2_SET GPIO_SET(GPIO2)
|
||||
#define GPIO3_SET GPIO_SET(GPIO3)
|
||||
#define GPIO4_SET GPIO_SET(GPIO4)
|
||||
|
||||
/* GPIO port output clear register (GPIOn_CLR) */
|
||||
#define GPIO_CLR(port) MMIO32(port + 0x1C)
|
||||
#define GPIO0_CLR GPIO_CLR(GPIO0)
|
||||
#define GPIO1_CLR GPIO_CLR(GPIO1)
|
||||
#define GPIO2_CLR GPIO_CLR(GPIO2)
|
||||
#define GPIO3_CLR GPIO_CLR(GPIO3)
|
||||
#define GPIO4_CLR GPIO_CLR(GPIO4)
|
||||
|
||||
/* GPIO interrupt register map */
|
||||
/* Interrupt enable rising edge */
|
||||
#define GPIO0_IER MMIO32(GPIOINTERRPUT_BASE + 0x90)
|
||||
#define GPIO2_IER MMIO32(GPIOINTERRPUT_BASE + 0xB0)
|
||||
|
||||
/* Interrupt enable falling edge */
|
||||
#define GPIO0_IEF MMIO32(GPIOINTERRPUT_BASE + 0x94)
|
||||
#define GPIO2_IEF MMIO32(GPIOINTERRPUT_BASE + 0xB4)
|
||||
|
||||
/* Interrupt status rising edge */
|
||||
#define GPIO0_ISR MMIO32(GPIOINTERRPUT_BASE + 0x84)
|
||||
#define GPIO2_ISR MMIO32(GPIOINTERRPUT_BASE + 0xA4)
|
||||
|
||||
/* Interrupt status falling edge */
|
||||
#define GPIO0_ISF MMIO32(GPIOINTERRPUT_BASE + 0x88)
|
||||
#define GPIO2_ISF MMIO32(GPIOINTERRPUT_BASE + 0xA8)
|
||||
|
||||
/* Interrupt clear */
|
||||
#define GPIO0_IC MMIO32(GPIOINTERRPUT_BASE + 0x8C)
|
||||
#define GPIO1_IC MMIO32(GPIOINTERRPUT_BASE + 0xAC)
|
||||
|
||||
/* Overall interrupt status */
|
||||
#define GPIO_IS MMIO32(GPIOINTERRPUT_BASE + 0x80)
|
||||
|
||||
void gpio_set(u32 gpioport, u32 gpios);
|
||||
void gpio_clear(u32 gpioport, u32 gpios);
|
||||
|
||||
#endif
|
||||
65
include/libopencm3/lpc17xx/memorymap.h
Normal file
65
include/libopencm3/lpc17xx/memorymap.h
Normal file
@@ -0,0 +1,65 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LPC17XX_MEMORYMAP_H
|
||||
#define LPC17XX_MEMORYMAP_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/* --- LPC17XX specific peripheral definitions ----------------------------- */
|
||||
|
||||
/* Memory map for all busses */
|
||||
#define PERIPH_BASE_APB0 0x40000000
|
||||
#define PERIPH_BASE_APB1 0x40080000
|
||||
#define PERIPH_BASE_AHB 0x20000000
|
||||
|
||||
/* Register boundary addresses */
|
||||
|
||||
/* APB0 */
|
||||
#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000)
|
||||
#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000)
|
||||
#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000)
|
||||
#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000)
|
||||
#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000)
|
||||
/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */
|
||||
#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000)
|
||||
#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000)
|
||||
#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000)
|
||||
#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000)
|
||||
#define GPIOINTERRPUT_BASE (PERIPH_BASE_APB0 + 0x28000)
|
||||
#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000)
|
||||
#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000)
|
||||
#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000)
|
||||
#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000)
|
||||
#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000)
|
||||
#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000)
|
||||
#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000)
|
||||
#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000)
|
||||
/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */
|
||||
#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000)
|
||||
/* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */
|
||||
|
||||
/* AHB */
|
||||
#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000)
|
||||
#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020)
|
||||
#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040)
|
||||
#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060)
|
||||
#define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080)
|
||||
|
||||
#endif
|
||||
@@ -150,77 +150,194 @@
|
||||
|
||||
/* --- ADC_CR1 values ------------------------------------------------------ */
|
||||
|
||||
/* AWDEN: Analog watchdog enable on regular channels */
|
||||
#define ADC_CR1_AWDEN (1 << 23)
|
||||
|
||||
/* JAWDEN: Analog watchdog enable on injected channels */
|
||||
#define ADC_CR1_JAWDEN (1 << 22)
|
||||
#define ADC_CR1_DUALMOD_LSB 16
|
||||
#define ADC_CR1_DUALMOD_MSK (0xf << ADC_DUALMOD_LSB) /* ADC1 only */
|
||||
#define ADC_CR1_DISCNUM_LSB 13
|
||||
#define ADC_CR1_DISCNUM_MSK (0x7 << ADC_DISCNUM_LSB)
|
||||
|
||||
/* Note: Bits [21:20] are reserved, and must be kept at reset value. */
|
||||
|
||||
/* DUALMOD[3:0]: Dual mode selection. (ADC1 only) */
|
||||
/* Legend:
|
||||
* IND: Independent mode.
|
||||
* CRSISM: Combined regular simultaneous + injected simultaneous mode.
|
||||
* CRSATM: Combined regular simultaneous + alternate trigger mode.
|
||||
* CISFIM: Combined injected simultaneous + fast interleaved mode.
|
||||
* CISSIM: Combined injected simultaneous + slow interleaved mode.
|
||||
* ISM: Injected simultaneous mode only.
|
||||
* RSM: Regular simultaneous mode only.
|
||||
* FIM: Fast interleaved mode only.
|
||||
* SIM: Slow interleaved mode only.
|
||||
* ATM: Alternate trigger mode only.
|
||||
*/
|
||||
#define ADC_CR1_DUALMOD_IND (0x0 << 16)
|
||||
#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16)
|
||||
#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16)
|
||||
#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16)
|
||||
#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16)
|
||||
#define ADC_CR1_DUALMOD_ISM (0x5 << 16)
|
||||
#define ADC_CR1_DUALMOD_RSM (0x6 << 16)
|
||||
#define ADC_CR1_DUALMOD_FIM (0x7 << 16)
|
||||
#define ADC_CR1_DUALMOD_SIM (0x8 << 16)
|
||||
#define ADC_CR1_DUALMOD_ATM (0x9 << 16)
|
||||
#define ADC_CR1_DUALMOD_MASK (0xF << 16)
|
||||
#define ADC_CR1_DUALMOD_SHIFT 16
|
||||
|
||||
/* DISCNUM[2:0]: Discontinous mode channel count. */
|
||||
#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13)
|
||||
#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13)
|
||||
#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13)
|
||||
#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13)
|
||||
#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13)
|
||||
#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13)
|
||||
#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13)
|
||||
#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13)
|
||||
#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
|
||||
#define ADC_CR1_DISCNUM_SHIFT 13
|
||||
|
||||
/* JDISCEN: Discontinous mode on injected channels. */
|
||||
#define ADC_CR1_JDISCEN (1 << 12)
|
||||
|
||||
/* DISCEN: Discontinous mode on regular channels. */
|
||||
#define ADC_CR1_DISCEN (1 << 11)
|
||||
|
||||
/* JAUTO: Automatic Injection Group conversion. */
|
||||
#define ADC_CR1_JAUTO (1 << 10)
|
||||
|
||||
/* AWDSGL: Enable the watchdog on a single channel in scan mode. */
|
||||
#define ADC_CR1_AWDSGL (1 << 9)
|
||||
|
||||
/* SCAN: Scan mode. */
|
||||
#define ADC_CR1_SCAN (1 << 8)
|
||||
|
||||
/* JEOCIE: Interrupt enable for injected channels. */
|
||||
#define ADC_CR1_JEOCIE (1 << 7)
|
||||
|
||||
/* AWDIE: Analog watchdog interrupt enable. */
|
||||
#define ADC_CR1_AWDIE (1 << 6)
|
||||
|
||||
/* EOCIE: Interrupt enable EOC. */
|
||||
#define ADC_CR1_EOCIE (1 << 5)
|
||||
#define ADC_CR1_AWDCH_LSB 0
|
||||
#define ADC_CR1_AWDCH_MSK (0x1f << ADC_AWDCH_LSB)
|
||||
|
||||
/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */
|
||||
/* Notes:
|
||||
* ADC1: Analog channel 16 and 17 are internally connected to the temperature
|
||||
* sensor and V_REFINT, respectively.
|
||||
* ADC2: Analog channel 16 and 17 are internally connected to V_SS.
|
||||
* ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS.
|
||||
*/
|
||||
#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0)
|
||||
#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0)
|
||||
#define ADC_CR1_AWDCH_MASK (0x1F << 0)
|
||||
#define ADC_CR1_AWDCH_SHIFT 0
|
||||
|
||||
/* --- ADC_CR2 values ------------------------------------------------------ */
|
||||
|
||||
#define ADC_CR2_TSVREFE (1 << 23) /* ADC1 only! */
|
||||
/* TSVREFE: Temperature sensor and V_REFINT enable. (ADC1 only!) */
|
||||
#define ADC_CR2_TSVREFE (1 << 23)
|
||||
|
||||
/* SWSTART: Start conversion of regular channels. */
|
||||
#define ADC_CR2_SWSTART (1 << 22)
|
||||
|
||||
/* JSWSTART: Start conversion of injected channels. */
|
||||
#define ADC_CR2_JSWSTART (1 << 21)
|
||||
|
||||
/* EXTTRIG: External trigger conversion mode for regular channels. */
|
||||
#define ADC_CR2_EXTTRIG (1 << 20)
|
||||
#define ADC_CR2_EXTSEL_LSB 17
|
||||
#define ADC_CR2_EXTSEL_MSK (0x7 << ADC_EXTSEL_LSB)
|
||||
|
||||
/* EXTSEL[2:0]: External event select for regular group. */
|
||||
/* The following are only valid for ADC1 and ADC2. */
|
||||
#define ADC_CR2_EXTSEL_TIM1_CC1 0x0
|
||||
#define ADC_CR2_EXTSEL_TIM1_CC2 0x1
|
||||
#define ADC_CR2_EXTSEL_TIM1_CC3 0x2
|
||||
#define ADC_CR2_EXTSEL_TIM2_CC2 0x3
|
||||
#define ADC_CR2_EXTSEL_TIM3_TRGO 0x4
|
||||
#define ADC_CR2_EXTSEL_TIM4_CC4 0x5
|
||||
#define ADC_CR2_EXTSEL_EXTI11 0x6
|
||||
#define ADC_CR2_EXTSEL_SWSTART 0x7
|
||||
#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17)
|
||||
#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17)
|
||||
#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17)
|
||||
|
||||
/* The following are only valid for ADC3 */
|
||||
#define ADC_CR2_EXTSEL_TIM3_CC1 0x0
|
||||
#define ADC_CR2_EXTSEL_TIM2_CC3 0x1
|
||||
#define ADC_CR2_EXTSEL_TIM8_CC1 0x3
|
||||
#define ADC_CR2_EXTSEL_TIM8_TRGO 0x4
|
||||
#define ADC_CR2_EXTSEL_TIM5_CC1 0x5
|
||||
#define ADC_CR2_EXTSEL_TIM5_CC3 0x6
|
||||
#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17)
|
||||
#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17)
|
||||
|
||||
/* Bit 16: reserved, must be kept cleared */
|
||||
#define ADC_CR2_EXTSEL_MASK (0x7 << 17)
|
||||
#define ADC_CR2_EXTSEL_SHIFT 17
|
||||
|
||||
/* Note: Bit 16 is reserved, must be kept at reset value. */
|
||||
|
||||
/* JEXTTRIG: External trigger conversion mode for injected channels. */
|
||||
#define ADC_CR2_JEXTTRIG (1 << 15)
|
||||
#define ADC_CR2_JEXTSEL_LSB 12
|
||||
#define ADC_CR2_JEXTSEL_MSK (0x7 << ADC_JEXTSEL_LSB)
|
||||
|
||||
/* JEXTSEL[2:0]: External event selection for injected group. */
|
||||
/* The following are only valid for ADC1 and ADC2. */
|
||||
#define ADC_CR2_JEXTSEL_TIM1_TRGO 0x0
|
||||
#define ADC_CR2_JEXTSEL_TIM1_CC4 0x1
|
||||
#define ADC_CR2_JEXTSEL_TIM2_TRGO 0x2
|
||||
#define ADC_CR2_JEXTSEL_TIM2_CC1 0x3
|
||||
#define ADC_CR2_JEXTSEL_TIM3_CC4 0x4
|
||||
#define ADC_CR2_JEXTSEL_TIM4_TRGO 0x5
|
||||
#define ADC_CR2_JEXTSEL_EXTI15 0x6
|
||||
#define ADC_CR2_JEXTSEL_JSWSTART 0x7
|
||||
#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12)
|
||||
#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12)
|
||||
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
|
||||
|
||||
/* The following are the different meanings for ADC3 only. */
|
||||
#define ADC_CR2_JEXTSEL_TIM4_CC3 0x2
|
||||
#define ADC_CR2_JEXTSEL_TIM8_CC2 0x3
|
||||
#define ADC_CR2_JEXTSEL_TIM8_CC4 0x4
|
||||
#define ADC_CR2_JEXTSEL_TIM5_TRGO 0x5
|
||||
#define ADC_CR2_JEXTSEL_TIM5_CC4 0x6
|
||||
#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
|
||||
#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
|
||||
|
||||
#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
|
||||
#define ADC_CR2_JEXTSEL_SHIFT 12
|
||||
|
||||
/* ALIGN: Data alignement. */
|
||||
#define ADC_CR2_ALIGN_RIGHT (0 << 11)
|
||||
#define ADC_CR2_ALIGN_LEFT (1 << 11)
|
||||
#define ADC_CR2_ALIGN (1 << 11)
|
||||
#define ADC_CR2_DMA (1 << 8) /* ADC 1 & 3 only! */
|
||||
/* Bits [7:4] have to be kept 0. */
|
||||
|
||||
/* Note: Bits [10:9] are reserved and must be kept at reset value. */
|
||||
|
||||
/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */
|
||||
#define ADC_CR2_DMA (1 << 8)
|
||||
|
||||
/* Note: Bits [7:4] are reserved and must be kept at reset value. */
|
||||
|
||||
/* RSTCAL: Reset calibration. */
|
||||
#define ADC_CR2_RSTCAL (1 << 3)
|
||||
|
||||
/* CAL: A/D Calibration. */
|
||||
#define ADC_CR2_CAL (1 << 2)
|
||||
|
||||
/* CONT: Continous conversion. */
|
||||
#define ADC_CR2_CONT (1 << 1)
|
||||
#define ADC_CR2_ADON (1 << 0) /* Must be separately written. */
|
||||
|
||||
/* ADON: A/D converter On/Off. */
|
||||
/* Note: If any other bit in this register apart from ADON is changed at the
|
||||
* same time, then conversion is not triggered. This is to prevent triggering
|
||||
* an erroneous conversion.
|
||||
* Conclusion: Must be separately written.
|
||||
*/
|
||||
#define ADC_CR2_ADON (1 << 0)
|
||||
|
||||
/* --- ADC_SMPR1 values ---------------------------------------------------- */
|
||||
|
||||
@@ -394,9 +511,9 @@ void adc_enable_temperature_sensor(u32 adc);
|
||||
void adc_disable_temperature_sensor(u32 adc);
|
||||
void adc_start_conversion_regular(u32 adc);
|
||||
void adc_start_conversion_injected(u32 adc);
|
||||
void adc_enable_external_trigger_regular(u32 adc, u8 trigger);
|
||||
void adc_enable_external_trigger_regular(u32 adc, u32 trigger);
|
||||
void adc_disable_external_trigger_regular(u32 adc);
|
||||
void adc_enable_external_trigger_injected(u32 adc, u8 trigger);
|
||||
void adc_enable_external_trigger_injected(u32 adc, u32 trigger);
|
||||
void adc_disable_external_trigger_injected(u32 adc);
|
||||
void adc_set_left_aligned(u32 adc);
|
||||
void adc_set_right_aligned(u32 adc);
|
||||
|
||||
@@ -127,7 +127,7 @@
|
||||
|
||||
/* TEIF: Transfer error interrupt flag */
|
||||
#define DMA_ISR_TEIF_BIT (1 << 3)
|
||||
#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (4 * (channel) -1))
|
||||
#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (4 * ((channel) -1)))
|
||||
|
||||
#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1)
|
||||
#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2)
|
||||
@@ -139,7 +139,7 @@
|
||||
|
||||
/* HTIF: Half transfer interrupt flag */
|
||||
#define DMA_ISR_HTIF_BIT (1 << 2)
|
||||
#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (4 * (channel) -1))
|
||||
#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (4 * ((channel) -1)))
|
||||
|
||||
#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1)
|
||||
#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2)
|
||||
@@ -151,7 +151,7 @@
|
||||
|
||||
/* TCIF: Transfer complete interrupt flag */
|
||||
#define DMA_ISR_TCIF_BIT (1 << 1)
|
||||
#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (4 * (channel) -1))
|
||||
#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (4 * ((channel) -1)))
|
||||
|
||||
#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1)
|
||||
#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2)
|
||||
@@ -163,7 +163,7 @@
|
||||
|
||||
/* GIF: Global interrupt flag */
|
||||
#define DMA_ISR_GIF_BIT (1 << 0)
|
||||
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (4 * (channel) -1))
|
||||
#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (4 * ((channel) -1)))
|
||||
|
||||
#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1)
|
||||
#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2)
|
||||
@@ -177,7 +177,7 @@
|
||||
|
||||
/* CTEIF: Transfer error clear */
|
||||
#define DMA_IFCR_CTEIF_BIT (1 << 3)
|
||||
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * (channel) -1))
|
||||
#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (4 * ((channel) -1)))
|
||||
|
||||
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2)
|
||||
@@ -189,7 +189,7 @@
|
||||
|
||||
/* CHTIF: Half transfer clear */
|
||||
#define DMA_IFCR_CHTIF_BIT (1 << 2)
|
||||
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * (channel) -1))
|
||||
#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (4 * ((channel) -1)))
|
||||
|
||||
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2)
|
||||
@@ -201,7 +201,7 @@
|
||||
|
||||
/* CTCIF: Transfer complete clear */
|
||||
#define DMA_IFCR_CTCIF_BIT (1 << 1)
|
||||
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * (channel) -1))
|
||||
#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (4 * ((channel) -1)))
|
||||
|
||||
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2)
|
||||
@@ -213,7 +213,7 @@
|
||||
|
||||
/* CGIF: Global interrupt clear */
|
||||
#define DMA_IFCR_CGIF_BIT (1 << 0)
|
||||
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * (channel) -1))
|
||||
#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (4 * ((channel) -1)))
|
||||
|
||||
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1)
|
||||
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2)
|
||||
@@ -256,10 +256,10 @@
|
||||
#define DMA_CCR_MSIZE_SHIFT 10
|
||||
|
||||
/* PSIZE[9:8]: Peripheral size */
|
||||
#define DMA_CCR_PSIZE_8BIT (0x0 << 10)
|
||||
#define DMA_CCR_PSIZE_16BIT (0x1 << 10)
|
||||
#define DMA_CCR_PSIZE_32BIT (0x2 << 10)
|
||||
#define DMA_CCR_PSIZE_MASK (0x2 << 10)
|
||||
#define DMA_CCR_PSIZE_8BIT (0x0 << 8)
|
||||
#define DMA_CCR_PSIZE_16BIT (0x1 << 8)
|
||||
#define DMA_CCR_PSIZE_32BIT (0x2 << 8)
|
||||
#define DMA_CCR_PSIZE_MASK (0x2 << 8)
|
||||
#define DMA_CCR_PSIZE_SHIFT 8
|
||||
|
||||
/* MINC: Memory increment mode */
|
||||
|
||||
@@ -701,6 +701,7 @@
|
||||
/* 27 reserved */
|
||||
|
||||
/* SWJ_CFG[2:0]: Serial wire JTAG configuration */
|
||||
#define AFIO_MAPR_SWJ_MASK (0x7 << 24)
|
||||
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24)
|
||||
#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24)
|
||||
#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24)
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
/* --- STM32 specific peripheral definitions ------------------------------- */
|
||||
|
||||
/* Memory map for all busses */
|
||||
#define PERIPH_BASE 0x40000000
|
||||
#define PERIPH_BASE ((u32)0x40000000)
|
||||
#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000)
|
||||
#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000)
|
||||
#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000)
|
||||
|
||||
@@ -232,7 +232,7 @@
|
||||
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
|
||||
|
||||
#define GPIO_AFR(n, af) (af << ((n) * 4))
|
||||
#define GPIO_AFR_MASK(n) ~(0xf << ((n) * 4))
|
||||
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
|
||||
#define GPIO_AF0 0x0
|
||||
#define GPIO_AF1 0x1
|
||||
#define GPIO_AF2 0x2
|
||||
|
||||
@@ -232,7 +232,7 @@
|
||||
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
|
||||
|
||||
#define GPIO_AFR(n, af) (af << ((n) * 4))
|
||||
#define GPIO_AFR_MASK(n) ~(0xf << ((n) * 4))
|
||||
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4))
|
||||
#define GPIO_AF0 0x0
|
||||
#define GPIO_AF1 0x1
|
||||
#define GPIO_AF2 0x2
|
||||
|
||||
@@ -25,9 +25,6 @@
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
/* TODO: Move to memorymap.h? */
|
||||
#define FSMC_BASE 0xa0000000
|
||||
|
||||
#define FSMC_BANK1_BASE 0x60000000 /* NOR / PSRAM */
|
||||
#define FSMC_BANK2_BASE 0x70000000 /* NAND flash */
|
||||
#define FSMC_BANK3_BASE 0x80000000 /* NAND flash */
|
||||
@@ -142,26 +139,39 @@
|
||||
|
||||
/* Bits [31:30]: Reserved. */
|
||||
|
||||
/* Same for read and write */
|
||||
#define FSMC_BTx_ACCMOD_A (0)
|
||||
#define FSMC_BTx_ACCMOD_B (1)
|
||||
#define FSMC_BTx_ACCMOD_C (2)
|
||||
#define FSMC_BTx_ACCMOD_D (3)
|
||||
|
||||
/* ACCMOD[29:28]: Access mode */
|
||||
#define FSMC_BTR_ACCMOD (1 << 28)
|
||||
#define FSMC_BTR_ACCMODx(x) (((x) & 0x03) << 28)
|
||||
|
||||
/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */
|
||||
#define FSMC_BTR_DATLAT (1 << 24)
|
||||
#define FSMC_BTR_DATLATx(x) (((x) & 0x0f) << 24)
|
||||
|
||||
/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
|
||||
#define FSMC_BTR_CLKDIV (1 << 20)
|
||||
#define FSMC_BTR_CLKDIVx(x) (((x) & 0x0f) << 20)
|
||||
|
||||
/* BUSTURN[19:16]: Bus turnaround phase duration */
|
||||
#define FSMC_BTR_BUSTURN (1 << 16)
|
||||
#define FSMC_BTR_BUSTURNx(x) (((x) & 0x0f) << 16)
|
||||
|
||||
/* DATAST[15:8]: Data-phase duration */
|
||||
#define FSMC_BTR_DATAST (1 << 8)
|
||||
#define FSMC_BTR_DATASTx(x) (((x) & 0xff) << 8)
|
||||
|
||||
/* ADDHLD[7:4]: Address-hold phase duration */
|
||||
#define FSMC_BTR_ADDHLD (1 << 4)
|
||||
#define FSMC_BTR_ADDHLDx(x) (((x) & 0x0f) << 4)
|
||||
|
||||
/* ADDSET[3:0]: Address setup phase duration */
|
||||
#define FSMC_BTR_ADDSET (1 << 0)
|
||||
#define FSMC_BTR_ADDSETx(x) (((x) & 0x0f) << 0)
|
||||
|
||||
/* --- FSMC_BWTRx values --------------------------------------------------- */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user