Header files for Doxygen group structure, layout changes to headings, example markup in stm32f1/ rcc

include/libopencm3/cm3/common.h

@@ -38,20 +38,4 @@ typedef uint64_t u64;
 #define MMIO32(addr)		(*(volatile u32 *)(addr))
 #define MMIO64(addr)		(*(volatile u64 *)(addr))
 
-/* Main page for the doxygen-generated documentation: */
-
-/**
- * @mainpage libopencm3 Developer Documentation
- *
- * The libopencm3 project (previously known as libopenstm32) aims to create
- * a free/libre/open-source (GPL v3, or later) firmware library for various
- * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
- * Atmel SAM3U, NXP LPC1000 and others.
- *
- * @par ""
- *
- * See the <a href="http://www.libopencm3.org">libopencm3 wiki</a> for
- * more information.
- */
-
 #endif

include/libopencm3/cm3/docmain.h

@@ -0,0 +1,64 @@
+/**
+ * @mainpage libopencm3 Developer Documentation
+ *
+ * The libopencm3 project (previously known as libopenstm32) aims to create
+ * a free/libre/open-source (GPL v3, or later) firmware library for various
+ * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
+ * Atmel SAM3U, NXP LPC1000 and others.
+ *
+ * @par ""
+ *
+ * See the <a href="http://www.libopencm3.org">libopencm3 wiki</a> for
+ * more information.
+
+LGPL License Terms @ref lgpl_license
+
+*/
+
+/** @page lgpl_license libopencm3 License
+
+libopencm3 is free software: you can redistribute it and/or modify
+it under the terms of the GNU Lesser General Public License as published by the Free
+Software Foundation, either version 3 of the License, or (at your option) any
+later version.
+
+libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
+PARTICULAR PURPOSE.  See the GNU Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public License along with this
+program.  If not, see <http://www.gnu.org/licenses/>.
+
+*/
+
+/** @defgroup LM3S
+Libraries for Texas instruments LM3S series.
+*/
+
+/** @defgroup LPC13xx
+Libraries for NXP Semiconductor LPC13xx series.
+*/
+
+/** @defgroup LPC17xx
+Libraries for NXP Semiconductor LPC17xx series.
+*/
+
+/** @defgroup STM32F
+Libraries for ST Microelectronics STM32F series.
+*/
+
+/** @defgroup STM32F1xx
+@ingroup STM32F
+Libraries for ST Microelectronics STM32F1xx series.
+*/
+
+/** @defgroup STM32F2xx
+@ingroup STM32F
+Libraries for ST Microelectronics STM32F2xx series.
+*/
+
+/** @defgroup STM32F4xx
+@ingroup STM32F
+Libraries for ST Microelectronics STM32F4xx series.
+*/
+

include/libopencm3/stm32/f1/doc-stm32f1.h

@@ -0,0 +1,13 @@
+/** @defgroup STM32F1xx_defines
+
+@brief Defined Constants and Types for the STM32F1xx series
+
+@ingroup STM32F1xx
+
+@version 1.0.0
+
+@date 24 May 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+

include/libopencm3/stm32/f1/rcc.h

@@ -1,3 +1,27 @@
+/** @file
+
+@ingroup STM32F1xx
+
+@brief <b>libopencm3 STM32F1xx Reset and Clock Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+
+@date 18 May 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/** @defgroup STM32F1xx_rcc_defines
+
+@brief Defined Constants and Types for the STM32F1xx Reset and Clock Control
+
+@ingroup STM32F1xx_defines
+
+LGPL License Terms @ref lgpl_license
+
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -230,6 +254,10 @@
 
 /* --- RCC_AHBENR values --------------------------------------------------- */
 
+/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_AHBENR_ETHMACENRX			(1 << 16)
 #define RCC_AHBENR_ETHMACENTX			(1 << 15)
 #define RCC_AHBENR_ETHMACEN			(1 << 14)
@@ -241,9 +269,14 @@
 #define RCC_AHBENR_SRAMEN			(1 << 2)
 #define RCC_AHBENR_DMA2EN			(1 << 1)
 #define RCC_AHBENR_DMA1EN			(1 << 0)
+/*@}*/
 
 /* --- RCC_APB2ENR values -------------------------------------------------- */
 
+/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_APB2ENR_ADC3EN			(1 << 15) /* (XX) */
 #define RCC_APB2ENR_USART1EN			(1 << 14)
 #define RCC_APB2ENR_TIM8EN			(1 << 13) /* (XX) */
@@ -259,9 +292,14 @@
 #define RCC_APB2ENR_IOPBEN			(1 << 3)
 #define RCC_APB2ENR_IOPAEN			(1 << 2)
 #define RCC_APB2ENR_AFIOEN			(1 << 0)
+/*@}*/
 
 /* --- RCC_APB1ENR values -------------------------------------------------- */
 
+/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_APB1ENR_DACEN			(1 << 29)
 #define RCC_APB1ENR_PWREN			(1 << 28)
 #define RCC_APB1ENR_BKPEN			(1 << 27)
@@ -284,6 +322,7 @@
 #define RCC_APB1ENR_TIM4EN			(1 << 2)
 #define RCC_APB1ENR_TIM3EN			(1 << 1)
 #define RCC_APB1ENR_TIM2EN			(1 << 0)
+/*@}*/
 
 /* --- RCC_BDCR values ----------------------------------------------------- */