lm4f: Add API for enabling/disabling peripherals clock source
The enum definitions are specified in the form
31:5 register offset from SYSCTL_BASE for the clock register
4:0 bit offset for the given peripheral
The names have the form [clock_type]_[periph_type]_[periph_number]
Where clock_type is
RCC for run clock
SCC for sleep clock
DCC for deep-sleep clock
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Alexandru Gagniuc
@@ -21,6 +21,7 @@
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#define LM4F_SYSTEMCONTROL_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/lm4f/memorymap.h>
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#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000)
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#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004)
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@@ -450,6 +451,273 @@
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/** PLL lock */
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#define SYSCTL_PLLSTAT_LOCK (1 << 0)
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/* =============================================================================
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* Convenience definitions for a readable API
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* ---------------------------------------------------------------------------*/
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/**
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* \brief Clock enable definitions
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*
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* The definitions are specified in the form
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* 31:5 register offset from SYSCTL_BASE for the clock register
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* 4:0 bit offset for the given peripheral
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*
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* The names have the form [clock_type]_[periph_type]_[periph_number]
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* Where clock_type is
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* RCC for run clock
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* SCC for sleep clock
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* DCC for deep-sleep clock
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*/
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typedef enum {
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/*
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* Run clock control
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*/
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RCC_WD0 = ((u32)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
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RCC_WD1,
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RCC_TIMER0 = ((u32)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
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RCC_TIMER1,
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RCC_TIMER2,
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RCC_TIMER3,
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RCC_TIMER4,
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RCC_TIMER5,
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RCC_GPIOA = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
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RCC_GPIOB,
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RCC_GPIOC,
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RCC_GPIOD,
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RCC_GPIOE,
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RCC_GPIOF,
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RCC_GPIOG,
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RCC_GPIOH,
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RCC_GPIOJ,
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RCC_GPIOK,
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RCC_GPIOL,
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RCC_GPIOM,
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RCC_GPION,
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RCC_GPIOP,
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RCC_GPIOQ,
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RCC_DMA = ((u32)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
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RCC_HIB = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
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RCC_UART0 = ((u32)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
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RCC_UART1,
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RCC_UART2,
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RCC_UART3,
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RCC_UART4,
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RCC_UART5,
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RCC_UART6,
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RCC_UART7,
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RCC_SSI0 = ((u32)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
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RCC_SSI1,
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RCC_SSI2,
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RCC_SSI3,
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RCC_I2C0 = ((u32)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
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RCC_I2C1,
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RCC_I2C2,
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RCC_I2C3,
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RCC_I2C4,
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RCC_I2C5,
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RCC_USB0 = ((u32)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
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RCC_CAN0 = ((u32)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
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RCC_CAN1,
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RCC_ADC0 = ((u32)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
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RCC_ADC1,
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RCC_ACMP0 = ((u32)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
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RCC_PWM0 = ((u32)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
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RCC_PWM1,
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RCC_QEI0 = ((u32)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
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RCC_QEI1,
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RCC_EEPROM0 = ((u32)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
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RCC_WTIMER0 = ((u32)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
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RCC_WTIMER1,
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RCC_WTIMER2,
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RCC_WTIMER3,
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RCC_WTIMER4,
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RCC_WTIMER5,
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/*
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* Sleep clock control
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*/
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SCC_WD0 = ((u32)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
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SCC_WD1,
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SCC_TIMER0 = ((u32)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
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SCC_TIMER1,
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SCC_TIMER2,
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SCC_TIMER3,
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SCC_TIMER4,
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SCC_TIMER5,
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SCC_GPIOA = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
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SCC_GPIOB,
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SCC_GPIOC,
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SCC_GPIOD,
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SCC_GPIOE,
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SCC_GPIOF,
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SCC_GPIOG,
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SCC_GPIOH,
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SCC_GPIOJ,
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SCC_GPIOK,
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SCC_GPIOL,
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SCC_GPIOM,
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SCC_GPION,
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SCC_GPIOP,
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SCC_GPIOQ,
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SCC_DMA = ((u32)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
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SCC_HIB = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
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SCC_UART0 = ((u32)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
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SCC_UART1,
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SCC_UART2,
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SCC_UART3,
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SCC_UART4,
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SCC_UART5,
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SCC_UART6,
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SCC_UART7,
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SCC_SSI0 = ((u32)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
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SCC_SSI1,
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SCC_SSI2,
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SCC_SSI3,
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SCC_I2C0 = ((u32)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
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SCC_I2C1,
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SCC_I2C2,
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SCC_I2C3,
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SCC_I2C4,
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SCC_I2C5,
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SCC_USB0 = ((u32)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
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SCC_CAN0 = ((u32)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
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SCC_CAN1,
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SCC_ADC0 = ((u32)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
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SCC_ADC1,
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SCC_ACMP0 = ((u32)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
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SCC_PWM0 = ((u32)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
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SCC_PWM1,
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SCC_QEI0 = ((u32)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
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SCC_QEI1,
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SCC_EEPROM0 = ((u32)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
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SCC_WTIMER0 = ((u32)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
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SCC_WTIMER1,
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SCC_WTIMER2,
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SCC_WTIMER3,
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SCC_WTIMER4,
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SCC_WTIMER5,
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/*
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* Deep-sleep clock control
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*/
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DCC_WD0 = ((u32)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
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DCC_WD1,
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DCC_TIMER0 = ((u32)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
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DCC_TIMER1,
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DCC_TIMER2,
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DCC_TIMER3,
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DCC_TIMER4,
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DCC_TIMER5,
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DCC_GPIOA = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
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DCC_GPIOB,
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DCC_GPIOC,
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DCC_GPIOD,
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DCC_GPIOE,
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DCC_GPIOF,
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DCC_GPIOG,
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DCC_GPIOH,
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DCC_GPIOJ,
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DCC_GPIOK,
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DCC_GPIOL,
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DCC_GPIOM,
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DCC_GPION,
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DCC_GPIOP,
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DCC_GPIOQ,
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DCC_DMA = ((u32)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
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DCC_HIB = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
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DCC_UART0 = ((u32)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
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DCC_UART1,
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DCC_UART2,
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DCC_UART3,
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DCC_UART4,
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DCC_UART5,
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DCC_UART6,
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DCC_UART7,
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DCC_SSI0 = ((u32)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
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DCC_SSI1,
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DCC_SSI2,
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DCC_SSI3,
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DCC_I2C0 = ((u32)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
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DCC_I2C1,
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DCC_I2C2,
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DCC_I2C3,
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DCC_I2C4,
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DCC_I2C5,
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DCC_USB0 = ((u32)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
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DCC_CAN0 = ((u32)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
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DCC_CAN1,
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DCC_ADC0 = ((u32)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
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DCC_ADC1,
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DCC_ACMP0 = ((u32)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
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DCC_PWM0 = ((u32)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
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DCC_PWM1,
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DCC_QEI0 = ((u32)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
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DCC_QEI1,
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DCC_EEPROM0 = ((u32)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
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DCC_WTIMER0 = ((u32)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
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DCC_WTIMER1,
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DCC_WTIMER2,
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DCC_WTIMER3,
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DCC_WTIMER4,
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DCC_WTIMER5,
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} clken_t;
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/* =============================================================================
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* Function prototypes
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* ---------------------------------------------------------------------------*/
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BEGIN_DECLS
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void periph_clock_enable(clken_t periph);
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void periph_clock_disable(clken_t periph);
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END_DECLS
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#endif /* LM4F_SYSTEMCONTROL_H */
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