139 lines
4.2 KiB
C
139 lines
4.2 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Chuck McManis <cmcmanis@mcmanis.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* This then is the initialization code extracted from the
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* sdram example.
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*/
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#include <stdint.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/fsmc.h>
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#include "clock.h"
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#include "sdram.h"
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/*
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* This is just syntactic sugar but it helps, all of these
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* GPIO pins get configured in exactly the same way.
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*/
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static struct {
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uint32_t gpio;
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uint16_t pins;
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} sdram_pins[6] = {
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{GPIOB, GPIO5 | GPIO6 },
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{GPIOC, GPIO0 },
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{GPIOD, GPIO0 | GPIO1 | GPIO8 | GPIO9 | GPIO10 | GPIO14 | GPIO15},
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{GPIOE, GPIO0 | GPIO1 | GPIO7 | GPIO8 | GPIO9 | GPIO10 |
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GPIO11 | GPIO12 | GPIO13 | GPIO14 | GPIO15 },
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{GPIOF, GPIO0 | GPIO1 | GPIO2 | GPIO3 | GPIO4 | GPIO5 | GPIO11 |
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GPIO12 | GPIO13 | GPIO14 | GPIO15 },
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{GPIOG, GPIO0 | GPIO1 | GPIO4 | GPIO5 |GPIO8 | GPIO15}
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};
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static struct sdram_timing timing = {
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.trcd = 2, /* RCD Delay */
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.trp = 2, /* RP Delay */
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.twr = 2, /* Write Recovery Time */
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.trc = 7, /* Row Cycle Delay */
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.tras = 4, /* Self Refresh Time */
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.txsr = 7, /* Exit Self Refresh Time */
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.tmrd = 2, /* Load to Active Delay */
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};
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/*
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* Initialize the SD RAM controller.
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*/
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void
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sdram_init(void) {
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int i;
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uint32_t cr_tmp, tr_tmp; // control, timing registers
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/*
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* First all the GPIO pins that end up as SDRAM pins
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*/
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rcc_periph_clock_enable(RCC_GPIOB);
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rcc_periph_clock_enable(RCC_GPIOC);
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rcc_periph_clock_enable(RCC_GPIOD);
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rcc_periph_clock_enable(RCC_GPIOE);
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rcc_periph_clock_enable(RCC_GPIOF);
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rcc_periph_clock_enable(RCC_GPIOG);
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for (i = 0; i < 6; i++) {
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gpio_mode_setup(sdram_pins[i].gpio, GPIO_MODE_AF, GPIO_PUPD_NONE,
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sdram_pins[i].pins);
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gpio_set_output_options(sdram_pins[i].gpio, GPIO_OTYPE_PP,
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GPIO_OSPEED_50MHZ, sdram_pins[i].pins);
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gpio_set_af(sdram_pins[i].gpio, GPIO_AF12, sdram_pins[i].pins);
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}
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/* Enable the SDRAM Controller */
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#if 1
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rcc_periph_clock_enable(RCC_FSMC);
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#else
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rcc_peripheral_enable_clock(&RCC_AHB3ENR, RCC_AHB3ENR_FMCEN);
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#endif
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/* Note the STM32F429-DISCO board has the ram attached to bank 2 */
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/* Timing parameters computed for a 168Mhz clock */
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/* These parameters are specific to the SDRAM chip on the board */
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cr_tmp = FMC_SDCR_RPIPE_1CLK;
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cr_tmp |= FMC_SDCR_SDCLK_2HCLK;
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cr_tmp |= FMC_SDCR_CAS_3CYC;
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cr_tmp |= FMC_SDCR_NB4;
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cr_tmp |= FMC_SDCR_MWID_16b;
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cr_tmp |= FMC_SDCR_NR_12;
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cr_tmp |= FMC_SDCR_NC_8;
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/* We're programming BANK 2, but per the manual some of the parameters
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* only work in CR1 and TR1 so we pull those off and put them in the
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* right place.
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*/
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FMC_SDCR1 |= (cr_tmp & FMC_SDCR_DNC_MASK);
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FMC_SDCR2 = cr_tmp;
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tr_tmp = sdram_timing(&timing);
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FMC_SDTR1 |= (tr_tmp & FMC_SDTR_DNC_MASK);
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FMC_SDTR2 = tr_tmp;
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/* Now start up the Controller per the manual
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* - Clock config enable
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* - PALL state
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* - set auto refresh
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* - Load the Mode Register
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*/
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sdram_command(SDRAM_BANK2, SDRAM_CLK_CONF, 1, 0);
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msleep(1); // sleep at least 100uS
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sdram_command(SDRAM_BANK2, SDRAM_PALL, 1, 0);
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sdram_command(SDRAM_BANK2, SDRAM_AUTO_REFRESH, 4, 0);
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tr_tmp = SDRAM_MODE_BURST_LENGTH_2 |
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SDRAM_MODE_BURST_TYPE_SEQUENTIAL |
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SDRAM_MODE_CAS_LATENCY_3 |
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SDRAM_MODE_OPERATING_MODE_STANDARD |
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SDRAM_MODE_WRITEBURST_MODE_SINGLE;
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sdram_command(SDRAM_BANK2, SDRAM_LOAD_MODE, 1, tr_tmp);
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/*
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* set the refresh counter to insure we kick off an
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* auto refresh often enough to prevent data loss.
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*/
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FMC_SDRTR = 683;
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/* and Poof! a 8 megabytes of ram shows up in the address space */
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}
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