153 lines
5.1 KiB
C
153 lines
5.1 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/rcc.h>
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#include <libopencm3/stm32/gpio.h>
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#include <libopencm3/stm32/timer.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/stm32/dac.h>
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#include <libopencm3/stm32/dma.h>
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/* Timer 2 count period, 16 microseconds for a 72MHz APB2 clock */
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#define PERIOD 1152
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/* Globals */
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uint8_t waveform[256];
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/*--------------------------------------------------------------------*/
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static void clock_setup(void)
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{
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rcc_clock_setup_hse_3v3(&hse_8mhz_3v3[CLOCK_3V3_168MHZ]);
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}
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/*--------------------------------------------------------------------*/
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static void gpio_setup(void)
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{
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/* Port A and C are on AHB1 */
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rcc_periph_clock_enable(RCC_GPIOA);
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rcc_periph_clock_enable(RCC_GPIOC);
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/* Set the digital test output on PC1 */
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gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO1);
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gpio_set_output_options(GPIOC, GPIO_OTYPE_PP, GPIO_OSPEED_2MHZ, GPIO1);
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/* Set PA4 for DAC channel 1 to analogue, ignoring drive mode. */
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gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO4);
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}
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/*--------------------------------------------------------------------*/
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static void timer_setup(void)
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{
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/* Enable TIM2 clock. */
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rcc_periph_clock_enable(RCC_TIM2);
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timer_reset(TIM2);
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/* Timer global mode: - No divider, Alignment edge, Direction up */
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timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
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TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
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timer_continuous_mode(TIM2);
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timer_set_period(TIM2, PERIOD);
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timer_disable_oc_output(TIM2, TIM_OC2 | TIM_OC3 | TIM_OC4);
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timer_enable_oc_output(TIM2, TIM_OC1);
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timer_disable_oc_clear(TIM2, TIM_OC1);
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timer_disable_oc_preload(TIM2, TIM_OC1);
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timer_set_oc_slow_mode(TIM2, TIM_OC1);
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timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_TOGGLE);
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timer_set_oc_value(TIM2, TIM_OC1, 500);
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timer_disable_preload(TIM2);
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/* Set the timer trigger output (for the DAC) to the channel 1 output compare */
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timer_set_master_mode(TIM2, TIM_CR2_MMS_COMPARE_OC1REF);
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timer_enable_counter(TIM2);
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}
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/*--------------------------------------------------------------------*/
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static void dma_setup(void)
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{
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/* DAC channel 1 uses DMA controller 1 Stream 5 Channel 7. */
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/* Enable DMA1 clock and IRQ */
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rcc_periph_clock_enable(RCC_DMA1);
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nvic_enable_irq(NVIC_DMA1_STREAM5_IRQ);
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dma_stream_reset(DMA1, DMA_STREAM5);
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dma_set_priority(DMA1, DMA_STREAM5, DMA_SxCR_PL_LOW);
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dma_set_memory_size(DMA1, DMA_STREAM5, DMA_SxCR_MSIZE_8BIT);
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dma_set_peripheral_size(DMA1, DMA_STREAM5, DMA_SxCR_PSIZE_8BIT);
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dma_enable_memory_increment_mode(DMA1, DMA_STREAM5);
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dma_enable_circular_mode(DMA1, DMA_STREAM5);
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dma_set_transfer_mode(DMA1, DMA_STREAM5, DMA_SxCR_DIR_MEM_TO_PERIPHERAL);
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/* The register to target is the DAC1 8-bit right justified data register */
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dma_set_peripheral_address(DMA1, DMA_STREAM5, (uint32_t) &DAC_DHR8R1);
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/* The array v[] is filled with the waveform data to be output */
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dma_set_memory_address(DMA1, DMA_STREAM5, (uint32_t) waveform);
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dma_set_number_of_data(DMA1, DMA_STREAM5, 256);
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dma_enable_transfer_complete_interrupt(DMA1, DMA_STREAM5);
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dma_channel_select(DMA1, DMA_STREAM5, DMA_SxCR_CHSEL_7);
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dma_enable_stream(DMA1, DMA_STREAM5);
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}
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/*--------------------------------------------------------------------*/
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static void dac_setup(void)
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{
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/* Enable the DAC clock on APB1 */
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rcc_periph_clock_enable(RCC_DAC);
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/* Setup the DAC channel 1, with timer 2 as trigger source.
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* Assume the DAC has woken up by the time the first transfer occurs */
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dac_trigger_enable(CHANNEL_1);
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dac_set_trigger_source(DAC_CR_TSEL1_T2);
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dac_dma_enable(CHANNEL_1);
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dac_enable(CHANNEL_1);
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}
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/*--------------------------------------------------------------------*/
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/* The ISR simply provides a test output for a CRO trigger */
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void dma1_stream5_isr(void)
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{
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if (dma_get_interrupt_flag(DMA1, DMA_STREAM5, DMA_TCIF))
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{
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dma_clear_interrupt_flags(DMA1, DMA_STREAM5, DMA_TCIF);
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/* Toggle PC1 just to keep aware of activity and frequency. */
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gpio_toggle(GPIOC, GPIO1);
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}
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}
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/*--------------------------------------------------------------------*/
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int main(void)
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{
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/* Fill the array with funky waveform data */
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/* This is for dual channel 8-bit right aligned */
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uint16_t i, x;
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for (i=0; i<256; i++)
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{
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if (i<10) x=10;
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else if (i<121) x=10+((i*i)>>7);
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else if (i<170) x=i/2;
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else if (i<246) x=i+(80-i/2);
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else x=10;
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waveform[i] = x;
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}
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clock_setup();
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gpio_setup();
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timer_setup();
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dma_setup();
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dac_setup();
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while (1) {
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}
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return 0;
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}
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