EMTime/libopencm3-examples
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Updated to use the new rcc_periph_clock_enable code

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This commit is contained in:
cmcmanis
2014-02-20 20:09:02 -08:00
committed by Piotr Esden-Tempski
parent ae9c116e30
commit e4d106dce6
11 changed files with 32 additions and 36 deletions
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4
examples/stm32/f4/stm32f4-disco/lcd-serial/console.c
View File

@@ -191,7 +191,7 @@ int console_gets(char *s, int len) {
void console_setup(int baud) {
/* MUST enable the GPIO clock in ADDITION to the USART clock */
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN);
rcc_periph_clock_enable(RCC_GPIOD);
/* This example uses PD5 and PD6 for Tx and Rx respectively
* but other pins are available for this role on USART2 (our chosen
@@ -213,7 +213,7 @@ void console_setup(int baud) {
* attach to different buses, and even some UARTS are attached to
* APB1 and some to APB2, again the data sheet is useful here.
*/
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_USART2EN);
rcc_periph_clock_enable(RCC_USART2);
/* Set up USART/UART parameters using the libopencm3 helper functions */
usart_set_baudrate(CONSOLE_UART, baud);

6
examples/stm32/f4/stm32f4-disco/lcd-serial/lcd-spi.c
View File

@@ -347,9 +347,7 @@ lcd_spi_init(void) {
* Set up the GPIO lines for the SPI port and
* control lines on the display.
*/
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPCEN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPFEN);
rcc_periph_clock_enable(RCC_GPIOC | RCC_GPIOD | RCC_GPIOF);
gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO2);
gpio_mode_setup(GPIOD, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO13);
@@ -364,7 +362,7 @@ lcd_spi_init(void) {
/* Implement state management hack */
nvic_enable_irq(NVIC_SPI5_IRQ);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI5EN);
rcc_periph_clock_enable(RCC_SPI5);
/* This should configure SPI5 as we need it configured */
tmp = SPI_SR(LCD_SPI);
SPI_CR2(LCD_SPI) |= (SPI_CR2_SSOE | SPI_CR2_RXNEIE);

10
examples/stm32/f4/stm32f4-disco/lcd-serial/sdram.c
View File

@@ -67,12 +67,8 @@ sdram_init(void) {
/*
* First all the GPIO pins that end up as SDRAM pins
*/
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPBEN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPCEN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPDEN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPEEN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPFEN);
rcc_peripheral_enable_clock(&RCC_AHB1ENR, RCC_AHB1ENR_IOPGEN);
rcc_periph_clock_enable(RCC_GPIOB | RCC_GPIOC | RCC_GPIOD |
RCC_GPIOE | RCC_GPIOF | RCC_GPIOG);
for (i = 0; i < 6; i++) {
gpio_mode_setup(sdram_pins[i].gpio, GPIO_MODE_AF, GPIO_PUPD_NONE,
@@ -83,7 +79,7 @@ sdram_init(void) {
}
/* Enable the SDRAM Controller */
rcc_peripheral_enable_clock(&RCC_AHB3ENR, RCC_AHB3ENR_FMCEN);
rcc_periph_clock_enable(RCC_FSMC);
/* Note the STM32F429-DISCO board has the ram attached to bank 2 */
/* Timing parameters computed for a 168Mhz clock */