EMTime/libopencm3-examples
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial commit.

Browse Source
This commit is contained in:
Piotr Esden-Tempski
2013-04-19 17:19:32 -07:00
commit 9d5526f773
324 changed files with 22845 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
examples/lpc43xx/hackrf-jellybean/ssp/Makefile Normal file
View File

@@ -0,0 +1,24 @@
##
## This file is part of the libopencm3 project.
##
## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
##
## This library is free software: you can redistribute it and/or modify
## it under the terms of the GNU Lesser General Public License as published by
## the Free Software Foundation, either version 3 of the License, or
## (at your option) any later version.
##
## This library is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU Lesser General Public License for more details.
##
## You should have received a copy of the GNU Lesser General Public License
## along with this library. If not, see <http://www.gnu.org/licenses/>.
##
BINARY = sspdemo
LDSCRIPT = ../jellybean-lpc4330.ld
include ../../Makefile.include

48
examples/lpc43xx/hackrf-jellybean/ssp/README Normal file
View File

@@ -0,0 +1,48 @@
------------------------------------------------------------------------------
README
------------------------------------------------------------------------------
This program exercises the SSP1 peripheral on Jellybean's LPC43xx.
Jellybean (connector)
P9 SPI
|-----------------|
| Pin2 Pin4 Pin6 |
||------| |
|| Pin1 |Pin3 Pin5 |
||------|----------|
|-------|
SSP1_MISO: Jellybean P9 SPI Pin6
SSP1_MOSI: Jellybean P9 SPI Pin4
SSP1_SCK: Jellybean P9 SPI Pin2
SSP1_SSEL: Jellybean P9 SPI Pin3
GND: Can be connected to P12 SD Pin1
PCLK clock source is PLL1 288MHz (from IRC 96MHz boot from SPIFI)
Freq = PCLK / (CPSDVSR * [SCR+1]).
By default (CPSDVSR=0 => Means MAX Divisor)
SSP1->CR0->SCR = 0x00 => CLK Freq 1.126MHz
SSP1->CR0->SCR = 0x01 => MOSI Freq 566.9KHz
...
Test Oscilloscpe:
SCR=0, CPSDVSR=32 => CLK 9.025MHz
SCR=1, CPSDVSR=2 => CLK 73MHz
SCR=2, CPSDVSR=2 => CLK 49MHz
SCR=4, CPSDVSR=2 => CLK 29MHz
SCR=8, CPSDVSR=2 => CLK 16MHz
SCR=16, CPSDVSR=2 => CLK 8.5MHz
SCR=32, CPSDVSR=2 => CLK 4.386MHz
SCR=64, CPSDVSR=2 => CLK 2.227MHz
SCR=1, CPSDVSR=64 => CLK 2.262MHz
Theory:
SCR=0, CPSDVSR=32 => 288MHz / (32*(0+1) = 9MHz
SCR=1, CPSDVSR=2 => 288MHz / (2*(1+1) = 72MHz
SCR=4, CPSDVSR=2 => 288MHz / (2*(4+1) = 28.8MHz
SCR=32, CPSDVSR=2 => 288MHz / (2*(32+1) = 4.364MHz
SCR=64, CPSDVSR=2 => 288MHz / (2*(64+1)) = 2.2154MHz
SCR=128, CPSDVSR=2 => 288MHz / (2*(128+1)) = 1.116MHz
SCR=1, CPSDVSR=64 => 288MHz / (64*(1+1)) = 2.25MHz

102
examples/lpc43xx/hackrf-jellybean/ssp/sspdemo.c Normal file
View File

@@ -0,0 +1,102 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/cgu.h>
#include <libopencm3/lpc43xx/ssp.h>
#include "../jellybean_conf.h"
static void gpio_setup(void)
{
/* Configure all GPIO as Input (safe state) */
GPIO0_DIR = 0;
GPIO1_DIR = 0;
GPIO2_DIR = 0;
GPIO3_DIR = 0;
GPIO4_DIR = 0;
GPIO5_DIR = 0;
GPIO6_DIR = 0;
GPIO7_DIR = 0;
/* Configure SCU Pin Mux as GPIO */
scu_pinmux(SCU_PINMUX_LED1, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_LED2, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_LED3, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_EN1V8, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT0, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT1, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT2, SCU_GPIO_FAST);
scu_pinmux(SCU_PINMUX_BOOT3, SCU_GPIO_FAST);
/* Configure SSP1 Peripheral (to be moved later in SSP driver) */
scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
scu_pinmux(SCU_SSP1_SSEL, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
/* Configure GPIO as Output */
GPIO2_DIR |= (PIN_LED1|PIN_LED2|PIN_LED3); /* Configure GPIO2[1/2/8] (P4_1/2 P6_12) as output. */
GPIO3_DIR |= PIN_EN1V8; /* GPIO3[6] on P6_10 as output. */
}
int main(void)
{
int i;
u8 ssp_val;
u8 serial_clock_rate;
u8 clock_prescale_rate;
gpio_setup();
/* Freq About 1.12MHz => Freq = PCLK / (CPSDVSR * [SCR+1]) with PCLK=PLL1=288MHz */
clock_prescale_rate = 2;
serial_clock_rate = 128;
ssp_init(SSP1_NUM,
SSP_DATA_8BITS,
SSP_FRAME_SPI,
SSP_CPOL_0_CPHA_0,
serial_clock_rate,
clock_prescale_rate,
SSP_MODE_NORMAL,
SSP_MASTER,
SSP_SLAVE_OUT_ENABLE);
ssp_val = 0x0;
while (1) {
ssp_write(SSP1_NUM, (u16)ssp_val);
gpio_set(GPIO2, GPIOPIN1); /* LED on */
for (i = 0; i < 1000; i++) /* Wait a bit. */
__asm__("nop");
gpio_clear(GPIO2, GPIOPIN1); /* LED off */
ssp_val++;
}
return 0;
}